|Publication number||US6995504 B2|
|Application number||US 10/320,238|
|Publication date||Feb 7, 2006|
|Filing date||Dec 16, 2002|
|Priority date||Aug 31, 2000|
|Also published as||US6733354, US7274138, US20030085650, US20060232186|
|Publication number||10320238, 320238, US 6995504 B2, US 6995504B2, US-B2-6995504, US6995504 B2, US6995504B2|
|Inventors||David A. Cathey, James J. Alwan|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (16), Non-Patent Citations (9), Classifications (26), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. patent application Ser. No. 09/652,630 filed Aug. 31, 2000, now U.S. Pat. No. 6,733,354.
The present invention was made with Government support under Contract No. DABT63-97-C-0001 awarded by the Department of Defense. The Government has certain rights in the invention.
The present invention relates to improved spacers for use with field emission displays (FEDs). U.S. Pat. No. 5,063,327 discloses a prior art method of fabricating spacers for use in FEDs. However, as will be discussed below, the spacers disclosed by the '327 patent are not ideal and there remains a need for improved spacers and for methods of making such improved spacers.
Prior to discussing spacers, the general background of FEDs will be briefly reviewed.
Faceplate 104 includes a glass plate 120, a transparent conductor 122, and a phosphor layer 124. Transparent conductor 122 is disposed on one major surface of glass plate 120, and phosphor layer 124 is disposed on transparent conductor 122. The faceplate 104 and baseplate 102 are spaced apart from one another and are disposed so that the phosphor layer 124 is proximal to the grid layer 112.
FED 100 also includes a plurality of spacers 130 disposed between the faceplate 104 and baseplate 102. The spacers 130 maintain the orientation between baseplate 102 and faceplate 104 so that the baseplate and faceplate are substantially parallel to one another. Outer walls (not shown) seal the outer periphery of FED 100 and the space between baseplate 102 and faceplate 104 is substantially evacuated (creating a vacuum of about 10−2 to 10−9 Torr). Since the space between faceplate 104 and baseplate 102 is substantially evacuated, atmospheric pressure tends to press baseplate 102 and faceplate 104 together. However, spacers 130 resist this pressure and maintain the spacing between baseplate 102 and faceplate 104.
FED 100 also includes a power supply 140 for (1) charging the transparent conductor 122 to a highly positive voltage (e.g., 3,500 Volts); (2) selectively charging selective ones of the column lines of the grid layer 112 to a positive voltage (e.g., 40 Volts); and (3) selectively charging selective ones of the row lines 118 to a negative voltage (e.g., −40 Volts).
In operation, voltages applied to the row lines 118, the grid layer 112, and the transparent conductor 122 cause emitters 108 to emit electrons 150 that travel along path 117 towards, and impact on, phosphor layer 124. Incident electrons 150 on phosphor layer 124 cause phosphor layer 124 to emit photons and thereby generate a visible display on faceplate 104.
The visible display of FED 100 is normally arranged as a matrix of pixels. Each pixel in the display is typically associated with a group of emitters 108, with all the emitters 108 in a group being dedicated to controlling the brightness of their associated pixel. For example,
Ideally, the spacers 130 have several important characteristics. First, it is important for the cross section of the spacers 130 to be relatively small compared with the area of each pixel. Ideally, the spacers 130 are characterized by a relatively high aspect ratio (i.e., the spacer's height is larger than its width). Typically, spacers 130 are about 200 to 2,000 microns high and about 25 microns wide. Such a high aspect ratio (1) provides sufficient spacing between the baseplate 102 and faceplate 104 to permit electrons traveling from emitters 108 towards faceplate 102 to acquire sufficient energy to cause phosphor layer 124 to emit photons and (2) minimizes the likelihood that electrons emitted by the emitters will be intercepted by the spacers rather than impacting the phosphor layer and thereby minimizes any effect that the spacers may have on the brightness of the display. The spacers 130 must also provide sufficient structural strength to resist the atmospheric pressure and thereby maintain the desired spacing between baseplate 102 and faceplate 104. It is also desirable for all spacers 130 to have the same height so they can provide uniform spacing between the baseplate 102 and the faceplate 104. It is also important for the spacers to be properly aligned with respect to the array of pixels so that dark regions in the display created where the spacers 130 contact the faceplate do not interfere with the display (e.g., it is desirable for the bottom of the spacers 130 to contact the grid layer 112 at selected locations that are between the apertures 116 and are equidistant from all the adjacent emitters). Since the spacers 130 are disposed within a vacuum, it is also important for the spacers to be formed from a vacuum compatible material (e.g., a material that does not outgas significantly).
The above-referenced '327 patent discloses a method of using photolithography to form the spacers for an FED. More specifically, the '327 patent discloses (1) disposing a layer of photosensitive polyimide over a baseplate (e.g., such as baseplate 102 as shown in FIG. 1); (2) disposing a mask between a radiation source and the polyimide layer; (3) exposing the masked polyimide layer to radiation; and (4) rinsing the exposed polyimide layer with an appropriate developer solution. The disclosed process “patterns” the polyimide layer or transforms the polyimide layer into a plurality of posts. Following a vacuum baking, the posts may be used as spacers in an FED. The spacers disclosed by the '327 patent suffer from several disadvantages. For example, polyimide is not an ideal photosensitive material. Also, polyimide is not an ideal material for use as a spacer in an FED.
In traditional photolithography, photoresist has been used to form only relatively thin features (e.g., one micron in height). However, recent work in the development of Micro Electro-Mechanical Systems (MEMS) has led to development of photoresists that can be used to form high aspect features. One such popular photoresist is known commercially as “SU-8”. SU-8 comprises bisphenol, which is an a/novolac epoxy resin, and is manufactured by Shell Chemical. Guérin et al. suggested in “SU-8 photoepoxy: A new material for FDP and PDP applications” (L. J. Guérin, C. W. Newquist, H. Lorenz, Ph. Renaud, Institute for Microsystems, Swiss Federal Institute of Technology) that photoresist could be used to form high aspect posts, however, such posts do not have the necessary structural strength for forming spacers in FEDs. Also, such posts are likely to outgas significant amounts of gas and are therefore not suitable for use in a vacuum environment. It would therefore be desirable to develop techniques for using photoresist to form posts that (1) are vacuum compatible, (2) have a high aspect ratio, and (3) provide sufficient structural strength to operate as spacers in a FED.
These and other objects are provided by an improved method for forming spacers in an FED. In one aspect of the invention, the method uses photoresist as a mold for forming spacers in an FED. Photolithographic techniques permit the photoresist mold to be precisely positioned with respect to other elements of the FED.
In one aspect of the invention, a layer of photoresist is used to form an array of high aspect photoresist posts. These posts are not suitable for use as spacers themselves, but they can be used according to the invention as a mold for forming the spacers. The posts are then coated with a layer of coating material (e.g., silicon oxide or silicon nitride). This forms an array of high aspect columns of the coating material. The high aspect columns may then be further treated (e.g., the posts of photoresist material may be removed) to form spacers for use in an FED. Such spacers are vacuum compatible (i.e., the coating material does not outgas significantly), are structurally strong, and can be accurately located so as not to degrade the quality of the display.
In another aspect, the photoresist posts may be treated with silicon, so that the silicon penetrates into the photoresist posts, and then exposed to reactive oxygen so that the oxygen and silicon react to form a coating of silicon oxide around the posts. Such posts may also be used as spacers in an FED.
In still another aspect, the invention provides an FED in which the spacers are formed as columns of coating material.
Still other objects and advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description wherein several embodiments are shown and described, simply by way of illustration of the best mode of the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not in a restrictive or limiting sense, with the scope of the application being indicated in the claims.
For a fuller understanding of the nature and objects of the present invention, reference should be made to the following detailed description taken in connection with the accompanying drawings in which the same reference numerals are used to indicate the same or similar parts wherein:
Following step 210, step 212 is performed in which selected portions of the photoresist are exposed to radiation. This step is preformed in accordance with conventional photolithography. Normally, a patterned photographic mask is positioned between the photoresist and a radiation source. When the radiation source is activated, apertures in the mask allow emitted radiation to illuminate portions of the photoresist while the remainder of the mask casts a shadow on the rest of the photoresist. Incident radiation affects the illuminated portion of the photoresist making the illuminated portions more (in a positive working photoresist) or less (in a negative working photoresist) susceptible to etching by certain chemical etchants. The invention discussed herein may be used with either positive or negative working photoresists. Following radiation exposure, in step 214 the photoresist is exposed to an appropriate chemical etchant. In the case of a positive working photoresist, the etchant removes the portions of the photoresist that were exposed to the radiation and in the case of a negative working photoresist, the etchant removes the portions of the photoresist that were shielded from exposure to the radiation.
Following step 214, step 216 is performed in which a layer of coating material is formed on the substrate and posts.
Following step 216, step 218 is performed in which the coating material is subjected to an anisotropic etch that etches substantially faster in the vertical direction than in the horizontal direction. In the field of FEDs, this type of anisotropic etch may be performed by using a reactive gas plasma between 0 and 10 Torr pressure in parallel with directional ion bombardment of substrate 310. In the case where layer 316 is SiO2 a flourine containing chemistry may be used.
Following step 218, step 220 is performed in which the columns are subjected to an etch that removes the cured photoresist posts 314.
In one embodiment of the invention, the columns 318″ (for example as shown in
The photoresist 314 essentially acts as a mold permitting formation of the high aspect columns 318″. The use of photolithography to form the columns 318″ as described herein (1) advantageously allows the columns to be located on the substrate 310 with a high degree of precision (e.g., to position each column 318″ equidistant from each adjacent emitter) and (2) advantageously insures that the heights of all the columns 318″ will be substantially equal (since all the photoresist posts used to form the columns 318″ are formed from a single layer of material, it is easy to insure that the heights of all the posts, and therefore the heights of all the resulting columns 318″, are substantially equal). Also, the coating material 316 (e.g., silicon oxide) used to form the columns 318″ (1) is a vacuum compatible material and will not outgas significantly and therefore will not disturb the vacuum between the faceplate and the baseplate and (2) possesses sufficient structural strength to maintain the spacing between the faceplate and the baseplate of the FED.
In other embodiments some steps of method 200 may be eliminated. For example, rather than forming columns 318″ (as shown in FIGS. 3F and 3G), columns 318 (as shown in
Following step 516, step 518 is performed in which the posts are exposed to reactive oxygen (e.g. by using oxygen feed gas to create a plasma in an environment with 13.56 MHz generation and below 10 Torr pressure.) Preferably, in this step the posts are exposed to an oxygen based plasma that includes reactive oxygen atomic species. In this atmosphere, atoms of oxygen bond with the silicon that has previously penetrated into the photoresist posts and forms a silicon oxide coating around the photoresist posts. These coated posts may then be used as spacers in an FED. In variations on this embodiment, it may be advantageous to thermally treat (e.g., heat to about four hundred twenty five degrees Celsius for about three to four hours) the photoresist posts before, after, or both before and after, exposing them to reactive oxygen.
Since certain changes may be made in the above apparatus without departing from the scope of the invention herein involved, it is intended that all matter contained in the above description or shown in the accompanying drawing shall be interpreted in an illustrative and not a limiting sense.
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|U.S. Classification||313/495, 445/24, 313/292, 313/482, 313/257, 445/25|
|International Classification||H01J1/62, H01J9/18, H01J9/24, H01J29/86, H01J31/12, H01J29/02|
|Cooperative Classification||H01J9/18, H01J9/242, H01J29/864, H01J2329/8645, H01J29/028, H01J9/185, H01J2329/864, H01J31/123|
|European Classification||H01J9/18B, H01J29/02K, H01J31/12F, H01J29/86D, H01J9/24B2, H01J9/18|
|Dec 16, 2002||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: MERGER;ASSIGNOR:MICRON DISPLAY TECHNOLOGY, INC.;REEL/FRAME:013593/0176
Effective date: 19971216
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CATHEY, DAVID A.;REEL/FRAME:013593/0681
Effective date: 20001212
|May 6, 2008||CC||Certificate of correction|
|Jul 8, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Sep 20, 2013||REMI||Maintenance fee reminder mailed|
|Feb 7, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Apr 1, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140207