US 7000212 B2
Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a hierarchical general interconnect architecture in which: (1) reliance on single-length general interconnect lines is avoided; (2) the next greater length of general interconnect line is at least double-reach length (triple span); and (3) yet greater lengths of general interconnect line (e.g., Deca-Reach Length, or 11-span) can feed signals into logic blocks indirectly through switching resources of the shorter length, general interconnect line rather than feeding such signals directly into the logic blocks through their own respective switching resources. Additionally, the yet greater lengths of general interconnect line (e.g., Deca-Reach Length) have a fewer number of signal tap points on them than the number of logic blocks spanned by such longer ones of the general interconnect lines. Navigation limiting rules may be established to reduce the number of drive buffers needed for driving signals onto the longer ones of the general interconnect lines. In one embodiment, there are no drive buffers for middle tap points of the longer ones of the general interconnect lines.
1. A field programmable gate array (FPGA) comprising:
(a) a plurality of nodes;
(b) a plurality of general interconnect lines that can be used to transmit interconnect-conveyed signals from respective source nodes to corresponding destination nodes, wherein said general interconnect lines include:
(b.1) a first plurality of first span length lines each respectively spanning a first span length and each having a first number of tap points, where the first span length is at least that spanning three of said processing/routing nodes and the tap points in said first number of tap points respectively couple to the at least three of the nodes spanned by the respective first span length line; and
(b.2) a second plurality of second span length lines each respectively spanning a second span length and each having a second number of tap points, where the second span length is greater than the first span length so that each respective, second span length line spans more nodes than the number of nodes spanned by the first span length lines, and where the tap points in said second number of tap points respectively couple to less than all the nodes spanned by the respective second span length line.
2. The FPGA of
(a.1) said programmable nodes are processing/routing nodes each having one or more programmably selectable, logic functions and/or one or more programmably selectable, data storage functions and one or more programmably selectable, interconnect-signal routing functions; and
(b.1) said plurality of general interconnect lines can be used to transmit interconnect-conveyed signals from respective source nodes to corresponding destination nodes by way of corresponding interconnect-signal routing functions selected in the source and destination nodes and by way of corresponding interconnect-signal routing functions selected in intervening nodes if any.
3. The FPGA of
(b.3) the ratio of the first span length to the second span length is less than about 1/2.
4. The FPGA of
(b.3) the ratio of the first span length to the second span length is about 2/10.
5. The FPGA of
(b.3) the ratio of the first number of tap points to the second number of tap points is about 1/1.
6. The FPGA of
(b.2a) the second span length spans at least 11 of said processing/routing nodes.
7. The FPGA of
(b.1a) the first span length spans 3 of said processing/routing nodes.
8. The FPGA of
(b.2b) second number of tap points is 3.
9. The FPGA of
(b.2a) the tap points in said second number of tap points are symmetrically distributed between ends of each respective second span length line.
10. The FPGA of
(a.1) said nodes include buffered drive resources for driving respective ones of said second span length lines and input receiving resources for receiving signals from associated ones of the general interconnect lines; and
(b.2a) for each respective second span length line at least two of the tap points in said second number of tap points are coupled to corresponding buffered drive resources while at least one of the tap points is not coupled to a corresponding buffered drive resource.
11. The FPGA of
(b.2a1) for each respective second span length line at least two terminal end tap points in said second number of tap points are coupled to corresponding buffered drive resources, the terminal end tap points being disposed at opposed ends of the respective second span length line.
The application is a continuation-in-part (CIP) of U.S. application Ser. No. 10/194,771 filed Jul. 12, 2002 and incorporates by reference the disclosure of said parent application.
The following copending U.S. patent applications are owned by the owner of the present application, and their disclosures are incorporated herein by reference:
(A) Ser. No. 10/090,209 filed Mar. 4, 2002 as a divisional of Ser. No. 09/626,094 which was previously filed Jul. 26, 2000 by Om P. Agrawal et al. and originally entitled, “VARIABLE GRAIN ARCHITECTURE FOR FPGA INTEGRATED CIRCUITS”; and
(B) Ser. No. 10/194,771 filed Jul. 12, 2002 by Om P. Agrawal et al. and originally entitled, “FPGA DEVICES HAVING REGISTER-INTENSIVE ARCHITECTURE, REGISTER-ABLE FEED-THROUGHS, MULTI-STAGE INPUT SWITCH MATRIX AND METHODS OF USING SAME”.
The disclosures of the following U.S. patents are incorporated herein by reference:
(A) U.S. Pat. No. 6,470,485 based on Ser. No. 09/692,694 filed Oct. 18, 2000 by Richard T. Cote, et al. and originally entitled, Scalable and Parallel Processing Methods and Structures for Testing Configurable Interconnect Network in FPGA Device; and
(B) U.S. Pat. No. 6,097,212 issued Aug. 1, 2000 to Om P. Agrawal et al, (filed as Ser. No. 08/948,306 on Oct. 9, 1997) and entitled, Variable Grain Architecture for FPGA Integrated Circuits.
The present disclosure of invention relates to circuits which have repeated configurable logic and configurable interconnect structures provided therein and to methods for configuring the same. Examples of such circuits include Field Programmable Gate Arrays (FPGA's).
The disclosure relates more specifically to problems which may be associated with efficient implementation of a scalable, general-use programmable interconnect between repeat logic blocks such as those provided within an integrated circuit monolith that contains a field programmable gate array (FPGA).
Like many other kinds of integrated circuits (IC's), those with programmable types of interconnect have historically continued to grow in terms of circuit density and complexity. Signal-processing speed has also tended to increase. As a result, the following attributes have become areas of growing concern: the robustness of the programmable interconnect, its ability to avoid signal traffic congestion, and its ability to avoid excessive consumptions of electrical power at localized points (e.g., due to high frequency driving of high capacitance loads).
Typically, designers try to throw in larger numbers of “general interconnect” lines and greater varieties of such into the programmable routing resources of FPGA's in order to try to assure that the various programmable logic sections (e.g., CLB's or Configurable Logic Blocks) in the IC will be able to acquire a wide variety of input signals and/or deliver respective output signals from/to other such CLB's and/or from/to I/O Blocks (IOB's) in timely and deterministic fashion; this being done so that appropriate communication can take place between such spaced-apart logic or other sections of the IC as may be required for programmably implementing desired logic functions. “General interconnect” lines are those which are not dedicated for use only by specific drive circuits or are not dedicated for specific functions (e.g., carrying memory address signals). Such general interconnect lines can be assigned by place-and-route software for use by any of a multitude of signal sources and/or for any of a multitude of functions.
The brute force solution of simply adding more and more general interconnect lines of different lengths and orientations into a programmable IC is all well and good. However, as circuit and interconnect densities grow it becomes more difficult to make efficient use of circuit resources while at the same time comporting with limitations on power consumption. For example, it may not be wise to drive a high frequency signal onto a relatively long gi-line (a general interconnect line with relatively large electrical capacitance) merely to couple the signal from one CLB to an immediately adjacent CLB. A shorter interconnect line may be more efficient. Most of the circuit space consumed by the length of the relatively long gi-line (e.g., an octal length line) will be wasted. Also, energy will be wasted in driving the greater capacitance of the long gi-line at high frequency. On the other hand, if there are too many relatively short gi-lines (e.g., those with a length of say, one CLB tile; defined as 1×CL below) then a large signal propagation time may be disadvantageously incurred if a signal has to be transported a relatively long distance by use of such short-haul gi-lines. The delay will be due to the many routing switches that are disposed along the way for provided programmable routing from each short gi-line (e.g., 1×CL) to the next. Aside from loading the routing lines, the many routing switches disadvantageously consume circuit space which might otherwise be used for providing higher logic density.
It is difficult to find a correct balance of interconnect resources. It is difficult to determine what mix of long-haul and short-haul gi-lines will efficiently implement all different kinds of designs that are to be programmably implemented in an FPGA.
Practitioners skilled in the art of once-programmable or re-programmable logic arrays such as Field Programmable Gate Arrays (FPGA's) have come to recognize the benefits of using a varied-granularity of interconnects wherein conductors of differing lengths (e.g., double-length, quad-length, etc.) are used, and where the conductors may further be of differing orientations, and where the types of interconnect may have other differing attributes (including differing drive capabilities such as tristateable, or not) in accordance with concepts introduced for example, in U.S. Pat. No. 5,185,706 issued Feb. 9, 1993 to Om P. Agrawal et al. To some extent, the growing lists of different kinds of interconnect (e.g., short-haul general interconnect, medium-haul general interconnect, long-haul general interconnect, dedicated non-general interconnect, etc.) has become a curse. Place-and-route software has to contend with a growing list of different kinds of interconnect and different navigation options available for each kind of interconnect resource at each position in the programmable circuitry. This creates a scalability problem.
Structures and methods may be provided in accordance with the present disclosure of invention for overcoming one or more of the above-described problems.
In accordance with one aspect of the present disclosure, FPGA's are structured to have a hierarchical type of general interconnect wherein: (1) reliance on single-length general interconnect lines (1×CL lines, described below) is avoided; (2) the next greater length of general interconnect line is at least double-reach length (2×RL, described below); and (3) yet greater lengths of general interconnect line (e.g., 10×RL, described below) can feed signals into logic blocks (e.g., CLB's) indirectly through switching resources of the shorter length, general interconnect line (e.g., 2×RL lines) rather than feeding them directly into the logic blocks through their own respective switching resources. In other words, when it comes to feeding input signals into the logic and/or storage resources that are, so-to-speak “housed” within a logic block construct, general interconnect entry is made by way of the “local streets” (e.g., 2×RL lines) rather than directly from longer-haul “elevated avenues” or “bridges” (e.g., 10×RL lines) of the general interconnect. Exit from the houses can be differently handled from entrance into the houses. In one embodiment, although general interconnect entrance has to be made by way of the shorter “street” conductors, exit (signal output) can be made directly from a logic block to an adjacent tap point of a corresponding “elevated avenue” (e.g., a 10×RL line) without consuming a local street for getting that signal out.
In accordance with a further aspect of the present disclosure, the number of signal injection/extraction points (tap points) on the relatively longer ones of the general interconnect lines is less than the number of logic blocks spanned by such relatively longer general interconnect lines. In other words, the longer general interconnect lines (“elevated avenues”) are sparsely tapped. In one embodiment, for example, a general-interconnect line which spans 11 logic blocks (a so-called 10×RL line) has only 3 tap points: two at its ends and one in the middle. Another further aspect is that not all the taps of the longer general interconnect lines are buffered. In other words, the taps of the longer general interconnect lines (“avenues”/“bridges”) are sparsely buffered. In one embodiment, for example, only the two end taps of a 10×RL line are driven by buffers configured for handling the larger electrical capacitance of a 10×RL line (as opposed to a shorter 2×RL line) the middle tap of the 10×RL line is unbuffered.
Other aspects of the disclosure will become apparent from the below detailed description.
The below detailed description section makes reference to the accompanying drawings, in which:
A relatively simplistic layout is shown in
One of the CLB's in
Other interconnect buses FPGA 100 may be conceptualized as being stacked on top of the 1×CL buses even though not all are shown. The various longer-length buses may be thought of as being stacked on top of one another and atop the 1×CL lines in the respective channels. Thus the 102.2 a and 102.4 a layers of switchbox 102 are understood to respectively have 2×CL and 4×CL conductors extending from them even though not shown at corner 102. Such 2×CL and 4×CL horizontal conductors are revealed in the respective rows of switchbox sections 102.2 b and 102.4 c. In one embodiment, a 102.8 a layer is included in each switchbox (e.g., 102L) and this further layer has 8×CL conductors (octal length segments) extending from it. One could also have hexadecimal length, general interconnect lines (16×CL) and so forth. Internals of the switchboxes (e.g., 102) are designed in accordance with the routing navigation rules, where the latter define how signals may hop from one general interconnect line to the next (e.g., from a 1×CL to another 1×CL or from a 4×CL to a 1×CL).
In summary, it may be understood from
With so many different kinds of general interconnect segments (e.g., 1×CL, 2×CL, 4×CL, etc.) present in each of the vertical and horizontal interconnect channels, and with the number of intersections increasing in successive design generations, an exponentially growing problem presents itself to the place-and-route software 90. The latter software has to tackle the difficult task of complying with the navigation rules 95 of the FPGA 100 and of deciding how to efficiently route each signal through the various kinds of general interconnect resources such that all signals get to their intended destinations in timely fashion without wasting circuit space or power. The problem is exacerbated if routing navigation options (95) inside and/or between each of the hypothetical switchbox layers (e.g., 102.1 a, 102.2 a, 102.4 a) vary according to the layer or layers involved (e.g., 1×CL-to-1×CL, 1×CL-to-2×CL, 2×CL-to-2×CL, 1×CL-to-4×CL, etc.)
Because each switchbox layer consumes circuit space and power, it becomes desirable to provide a general interconnect architecture that allows for a reduced number of general interconnect types and a reduced number of signal tap points (points where signals are injected into or extracted from interconnect lines).
The Double-Reach Length lines are also denoted as 2×RL lines and each has 3 signal tap points corresponding to the 3 “nodes” spanned by the 2×RL line. For example, the 2×RL line identified as 202 has respective left, middle and right tap points: tp2.1, tp2.2 and tp2.3. Each 2×RL line has a span of 3 nodes, meaning that each such 2×RL line runs adjacent to, and can immediately connect to just 3 switchboxes (e.g., 260) of its respectively spanned 3 nodes (e.g., 210, 211 and 212 for line 202). Note that the length of a 2×RL line can be just that of about two GLB tiles because extension into only about half of each end tile may be required before terminating into a PIP. (A GLB is a form of logic block. In some instances, alternative names may be assigned to such a repeated, programmable function unit, such as for example, “PFU”.) The short-haul general interconnect lines (e.g., 2×RL's) of the illustrated architecture may be considered to be “densely tapped” because there is a tap point for every node that is “spanned” by the short-haul line. Such short-haul general interconnect lines (e.g., 2×RL's) are intended to function as the primary workhorses of the overall, general interconnect structure. They are the local public “streets” through which entry may be made into the private node houses, where the private node houses each contain specific logic and/or storage resources as well as signal routing resources.
The Deca-Reach Length lines are further denoted as 10×RL lines and each has 3 signal tap points. For example, the single 10×RL line shown at 201 as respective left, middle and right tap points: tp10.1, tp10.2 and tp10.3. Each 10×RL line has a span of 11 processing nodes, meaning that each such 10×RL line runs adjacent to, and could (but does not necessarily) immediately connect to just 11 switchboxes (e.g., 260) of its respectively spanned 11 nodes (e.g.,210–219, where only 7 of the 11 are shown and 215, 217 represent the other 4). This 11-node spanning attribute of a Deca-line may be better seen for the 10×RL line 201′ shown in
Although it is not explicitly noted in
An advantage to having a hierarchical, general interconnect of the type introduced in
At the same time, the output arrows on the “Right” (R) Double driving line, 222 b of node 210 may represent either the first signal, or it may represent a second result signal (also from bus 262) that is being output from corresponding processing (240) in node 210 and being coupled into left-end tap point, tp2.4. The first or second result signal may then travel via the right side, 2×RL line 203 to destination nodes 213 and 214. Either of nodes 213 and 214 may alternatively serve as the signal source while node 210 and/or the other of 213–214 serves as the destination for a signal conveyed by this right side, 2×RL line 203. Thus, by using its respective Left and Right Double-driving connections (222 a and 222 b), a given node (210) can conveniently send either of first and second result signals (each derived from bus 262 and coupled via line 222 a or 222 b) respectively to Left and/or Right adjacent pairs of destination nodes (211–212 and 213–214) or it can send a same result signal to the four adjacent pairs of nodes (211–212 and 213–214), this being done while consuming just two 2×RL lines (202, 203) and the associated PIP's (programmable interconnect points) in switchbox 260.
Signals may cascade from one 2×RL line to the next. Thus, the Left distal node 211 of
For identification purposes, T-shaped termination icons are used in the schematics to represent the Left and Right (or Top and Bottom) Terminal ends of the illustrated 2×RL or 10×RL lines. Thus, T-shaped icons 292 a, 292 b represent the terminal ends of the first mentioned, Double-Reach Length line, 202. T-shaped icons 293 a, 293 b represent the terminal ends of the second mentioned, 2×RL line, 203. Similarly, T-shaped icons 291 a, 291 b represent the terminal ends of horizontal Deca-Reach Length line 201. This first 10×RL line, 201 may be viewed as an elevated, high speed bridge that allows a local street signal to quickly leap over a few local streets and jump from a first node (say 218) to a node spaced 10 slots away (say 219). In one embodiment, the middle node (e.g., 210) of a given Deca-Reach Length line (e.g., 201) cannot pump a buffered signal up to the elevated bridge (201) above it. Thus the middle node (e.g., 210) cannot use the middle-tap (tp10.2) above it as a fast path connection. It can however, send an unbuffered signal up to the bridge. This is useful for cases where the programmable connection does not need relatively short propagation times. More on this below.
Referring to the internal structures illustrated within processing/routing node 210 of
Among the output couplings of the OSM's there is a first bus 262 which connects to a Doubles-driving section of a Duo-Deca switchbox 260. Another of these couplings is a second bus 264 which connects to a Decas-driving section of the DuoDeca switchbox 260. One possible routing of a GLB result signal is that of passing out from bus 262, moving through the duo-deca switchbox 260, and to the Right Double tap point tp2.4 via path 222 b. The result signal may then be conveyed by 2×RL line 203 to either one or both of processing nodes 213 and 214 for further processing. Another possible routing of the same or another GLB result signal is from bus 262, through the duo-deca switchbox 260, and to the Left Double tap point tp2.3 via path 222 a. The result signal may then be conveyed by 2×RL line 202 to either one or both of nodes 211 and 212 for further processing.
Yet another possible routing of the same or different result signals is from the Block OSM, through bus 264, through the Decas-driving section of switchbox 260, and to a North (N) tap point tp10.N via Deca-drive buffer 265. This can be done without consuming a local 2×RL line. The buffered result signal may then be conveyed by the Northerly-extending 10×RL line (only partly shown) to one or more, farther spaced away processing/routing nodes and associated 2×RL lines. Similarly, node 218 can send an Eastwardly-heading signal from its internal East Deca drive buffer (not shown, but understood to be the counterpart of buffer 268) so that the buffered signal hops through Double-Reach Length line 201 to descend out from sparse tap points, tp10.2 and/or tp10.3 for further routing and/or processing by respective nodes 210 and 219. The respective output signals which are “elevated” into the adjacent tap point of the corresponding 10×RL line for longer-haul hopping to a spaced away, next tap point on the 10×RL line and/or for farther away destinations, do not need to consume a local 2×RL line. Thus, the local 2×RL lines (the local “streets) may be used for simultaneously carrying other signals. Although the “Deca-reach” name of line 201 implies for one embodiment, a span length extending into or through 11 nodes (see
A possible embodiment could have 50×RL bridges with 3 tap points each in combination with 10×RL bridges and 2×RL local streets. A far-hopping signal would make a programmably navigated drop from a 50×RL bridge (not shown) down to a 10×RL bridge and then another programmably navigated drop from the 10×RL line to one or more 2×RL lines. Note for the case of the 10×RL lines illustrated in
Because the ratio of tap points to spanned nodes is less than 100% for the “Deca-reach” (or other higher level ones of the gi-bridging lines), signals drop down from such 10×RL bridging lines (or other such higher level gi-lines) into the neighboring nodes (e.g., from 201 down into 210–219) by descending through the associated Double-reach (or other such lower level ones of the “local street” gi-lines) and then finally into the “housed” switching and/or other resources of the local node(s). More specifically, assume that node 218 had driven a result signal into 10×RL line 201 (via node 218's equivalent of buffer 268). Assume further that node 212 is to receive the result signal produced by node 218 where routing is by way of bridge line 201. The deca-transmitted signal would travel from left tap point tp10.1 to the middle tap point tp10.2 and then descend from that middle tap point tp10.2 into switchbox 260 of node 210 via line 221. Switchbox 260 would then route the descending signal by way of its Left Double-driving line 222 a onto the left side, 2×RL line 202. The descending signal would then continue through the Double's middle tap point, tp2.2 into node 212. Since the descending signal is consuming the one 2×RL line: 202 anyway, if node 211 is also to receive the same descending signal, node 211 can do so via the consumed 2×RL line, 202 and its Left tap point tp2.1. Alternatively or additionally, node 211 could receive a different signal via its Left Double-accessing line 211 a. In one embodiment, there are many more 2×RL lines and 10×RL lines than just the few sample ones illustrated in
If node 214 is also to receive the same result signal from node 218, where routing is by way of Deca line 201, a similar descent could be made through the appropriate 2×RL line (e.g., line 203). More specifically, the deca-transmitted signal that descends from middle tap point tp10.2 and via line 221 into switchbox 260 could be further routed by switchbox 260 to the Right Double-driving line 222 b and onto 2×RL line 203. The descending signal would then continue through that Double's right tap point, tp2.6 into node 214. An aspect of the hierarchical, general interconnect architecture is therefore that the “Deca-reach” (or other such higher level one of the gi-lines) does not directly couple its Deca-conveyed signals directly into each of the adjacent processing nodes (e.g., 211–219). Instead, the deca-conveyed signal drops down through the sparse population of Deca tap points (e.g., 10.1, 10.2, 10.3) to a shorter gi-line (e.g., a Double) in the hierarchy and the descent continues until the signal reaches the lowest such type of gi-line, which in the illustrated case are the heavily-tapped, 2×RL lines. Every processing/routing node (e.g., 210–219) should connect to at least one such, shortest type of gi-line. Every longer type of gi-line should have at least 3 tap points each connecting to a node whose switchbox (260) provides routing to a shorter type of gi-line. Thus, all Deca-transmitted signals (and/or signals transmitted by other such, longer gi-lines) should be able to descend through the hierarchy and reach any desired node. Within the desired node, the deca-conveyed signal may then continue by a such as path 232 a and through the doubles section of box 260 to make its way via av path such as 233 into the ISM (235) of the desired node. In one embodiment, the combination of Northerly-extending, Southerly-extending, Easterly-extending, and Westerly-extending 10×RL lines that terminate at a given node (e.g., 373 of
Another aspect of the hierarchical, general interconnect architecture relating to the “Deca-reach” (or other such higher level ones of the gi-lines) is that such longer gi-lines can route their signals from one such Deca-line to the next by way of buffered paths provided in the switchboxes (260). A deca-conveyed signal may pass laterally to a next 10×RL line as follows: coming in via an appropriate drop point (say 10.2 for purpose of illustration here) the signal moves down path 221 and into the Deca's-driving section of box 260. The signal then continues along one or more parts of path 261 for buffered output through a respective one or more of Deca-drivers such as 265 (North), 266 (South), 267 (West) and 268 (East). In one embodiment, a Deca-conveyed signal which is acquired from a middle, deca tap point (tp10.2) can be buffer driven onwards only to the end taps of orthogonally-extending Deca-lines (e.g., North and South), not to parallel wise extending Deca-lines (e.g., East and West). On the other hand, a Deca-conveyed signal which is acquired from an end, deca tap point (e.g., tp10.1) can be buffer driven to cascade further in all four directions (E, W, N, S). A PIP within the duo-deca switchbox 260, however, may allow an unbuffered result signal to be switched into the middle tap point tp10.2 of the associated Deca-line. This is so because the PIP's of one embodiment are implemented as pass-gates with programmably-selectable direction of signal flow. In other words, they can each be programmed to function as a non-connect, or as an input or as an output.
In one embodiment (see
It may be seen in
Additionally, and more importantly, even nodes such as 215′ that are missed by the immediate reach of Deca-tap accessed Doubles like 202′ and 204′ can be reached by cascading the signal through just one more Double, like 203′. The flow could be from tap point tp′10.1, through node 210′, along Double 202′ and then through node 214′ to reach 215′ via Double 203′. Alternatively, the flow could be from tap point tp′10.2, through node 273, along Double 204′ and then through node 271 to reach 215′ via Double 203′. So there are at least two paths. The delay is no more than that of one Deca (201′) and two Doubles (e.g., 202′ and 203′). Thus all 10 of the further nodes spanned by a Deca-line can be reached with a delay of no more than that of one Deca and two Doubles.
Moreover, at least all 11 of the spanned nodes (e.g., 210′ plus 214′–215′, 271–275, 281–283) of a given 10×RL line (e.g., 201′) can be reached by a signal carried on that given Deca-line by consuming no more than six (6) 2×RL lines (e.g., 202′–207′) for bringing the deca-carried signal down from the elevated-avenue level to the “street” level for input into the at least all 11 nodes. If one of the spanned nodes (e.g., 210′) is the source of the deca-carried signal, then no more than five (5) 2×RL lines (e.g., 203′–207′) need be consumed for reaching 11 further nodes associated with the consumed Deca-line (201′) where the eleventh extra node (284) is reachable because it is spanned by the end Double-line (207′).
In one embodiment, each set of Northerly-extending, Southerly-extending, Easterly-extending, and Westerly-extending 10×RL lines that terminate at a given node (e.g., 373 of
Note that the translation and rotation option does not have to involve the whole diamond shaped region. It is available for destination nodes within any other-wise shaped subsection of the diamond-like shaped region since any subset of destination nodes contained within the diamond-like shaped region are reachable via general interconnect with the ceiling delay of no more than a ceiling amount of one Deca-Reach Length line and three (3) Double-Reach Length lines within the first of the concentrically-expandable diamond shapes. Stated otherwise, signal propagation timing symmetry may be provided by the general interconnect structure so that, despite rotation about the central node or other relocation of the destination nodes relative to the central node, as long as the destination nodes remain within the concentrically-expandable diamond shape, it can be guaranteed that the signal propagation time need not exceed the predefined optimal ceiling value of the diamond shape if just the general interconnect is used for interconnecting the source to destination nodes of a corresponding circuit design section, where the design section is to be programmably-implemented inside the diamond shape region of the FPGA. Because the diamond shape region repeats in symmetrical fashion essentially about all core nodes of the FPGA, a given circuit design section can be relatively translated and/or rotated within the-core area of the FPGA without exceeding the optimal ceiling value of the diamond shape. (The ceiling value is not the maximum general interconnect delay within the diamond shape. Instead, it is the minimum for reaching any node within the diamond shape while using just the general interconnect. The place-and-route software is free to use other types of interconnect such as the direct-connect structures in combination with the general interconnect.)
In addition to, or as an alternative to relative placement of circuit nodes within the concentric, diamond-shaped regions, the place-and-route software may elect to horizontally cascade a Deca-carried signal from a first 10×RL line such as 201′ to one or a plurality of further 10×RL lines such as 208′ and 209′. This may be done for example by using the Right Deca driver in node 283 for repowering and injecting the signal obtained from tap point tp′10.3 into tap point tp′10.4 and/or it may be done by using the Left Deca driver in node 210′ for repowering and injecting the signal obtained from tap point tp′10.1 into tap point tp′10.8. If a particular signal is to be broadcast to many nodes in a row or column of the FPGA array rather than being programmably navigated to a specific few nodes with one or a few Deca-hops, then it may be advisable to use longlines (MaxRL lines) or Global lines rather then the hierarchical general interconnect structure.
Noting again that nodes 211′, 215′ and 281 of
The above has been mostly a one-dimensional look at the signal routing capabilities of the 10×RL and 2×RL lines. However, such hierarchical general interconnect lines should extend two—dimensionally across the FPGA, such as in respective horizontal interconnect channels (HIC's) and vertical interconnect channels (VIC's—see
Various different permutations of routing options (navigation rules) could be provided by the switchbox (not shown) inside node 373. One particular such navigation rule is shown in the legend denoted as “To-Deca Routing Rules of Node 37 x” and is understood to apply to all the nodes of the corresponding embodiment. Besides being able to receive an input signal and route it via one or more of the 2×RL lines (not shown) of node 373, a “T” line can output a buffered signal that has been obtained from a programmably selected one of the following elements of node 373: its B line, its L line, its R line, its Hm line and its internal Block OSM (BOSM). The BOSM supplies a result signal generated by processing in the GLB (not shown, see
A second routing rule which may be used in an embodiment 300′ of
Within the illustrated VIC 401, elements 401 a, 401 b, 401 x, 401 g and 401 f respectively refer to: (a) corresponding 10×RL lines (deca-reach length lines), (b) corresponding 2×RL lines (duo-reach length lines), (x) corresponding MaxRL lines (maximum-reach length unidirectional lines), (g) global reach lines, and (f) local, intra-GLB feedback lines (FB's) and dedicated, inter-GLB direct-connect lines (DC's). Elements 402 a, 402 b, and 4021 x of the illustrated HIC 402 respectively refer according to their suffixes to same kinds of lines that instead extend horizontally. As can be seen, the horizontal duo's and longs (402 b and 402 x) have conductors that define adjacent interconnect lines (AIL's) of ISM blocks such as 424. The vertical duo's and longs (401 b and 401 x) also have conductors that define AIL's of respective ISM blocks such as 424. Horizontal and vertical deca's (10×RL lines in groups 401 a and 402 a) do not participate in this embodiment 400 as AIL's of any ISM block such as 424. Instead, the switchboxes (e.g., SB 424) and associated 2×RL lines must be used in this embodiment as highway entrance and exit ramps (metaphorically speaking) for moving signals out of the 10×RL lines by way of local roads (metaphorically speaking) that are defined by corresponding 2×RL lines (e.g., 401 b, 402 b) extending into same ones of the duo-deca switchboxes (e.g., 426). See also the duo-deca switchbox 460′ of
As can be further seen in
Referring briefly to
For the horizontal row in which illustrated tile 490 a (GLB-A) resides, there will again be four conjoined versions of the, illustrated horizontal (H) longline OSM section 482 a, each coupled via 4 respective tristate drivers (not shown) to four respective ones of a total of 16 MaxRL lines in HIC 402′. Any-GLB (e.g., 491 a) can output up to four of its result signals to any desired four of the 16 horizontal MaxRL lines associated with conjoined, horizontal-longlines OSM sections 482 a. Each MaxRL line (e.g., 498) may couple bidirectionally and on a tristated-basis, via an associated Input/Output Block (e.g., IOB 482) with a package terminal or pin 483. A package-external signal may therefore be imported into the FPGA from pin 483 and along MaxRL line 498 to any one or more of the GLB's (e.g., 491 b) lying adjacent to that longline. The externally-sourced signal may then be fedthrough the ISM-1 and ISM-2 stages of the one or more longline-adjacent GLB's to state-storing registers (e.g., 408 a of
The illustrated longlines (MaxRL lines, 401 x, 420 x in
Element 411 represents a respective one or a set of buffers for driving a W1 result signal of GLB 401″ respectively to a direct connect line, DCa and/or to a local feedback line, FBa, as well as forwarding the W1 signal to the GLB's associated Block Output Switch Matrix (BOSM) 450″. In one embodiment, lines DCa and FBa are parts of a continuous, single conductor that is driven by a single line-driving buffer.
As seen in
It may be seen that a highly-flexible, building block (a CBB or Configurable Building Block 402″) can be provided by the combination of each lookup unit (e.g., 405A) and its associated plurality of state-storing registers (e.g., 408 a, 409 a) and the interposed, registers-feeding means (e.g., 407 a). That CBB structure 402″ may be augmented with the inclusion therein of a primary feedthrough line (FTa) feeding into the registers-feeding means and/or with the inclusion therein of other signal lines (e.g., 406 a) feeding into the registers-feeding means (e.g., 407 a). The functionality of that CBB structure 402″ may also be augmented with the provision of a multi-stage, input-signals acquiring means (e.g., 430″–440″) which selectively supplies the CBB structure 402″ with corresponding input term signals (e.g., a0–a3 and FTa).
It may be understood from
Selected ones of the acquirable first-stage signals (431–439) of
Referring still to
In the illustrated embodiment, the Block OSM 450″ (BOSM) feeds into the main duo-deca switchbox 460″. The latter switchbox 460″ can be user-programmed to route the BOSM's output signals 462 and 464 respectively onto the adjacent duo-reach general interconnect lines (2×RL's) 433 and onto deca-reach general interconnect lines (10×RL's) 437. Additionally, the duo-deca switchbox 460″ can programmably route signals between various ones of the 2×RL and 10×RL lines passing through that switchbox 460″.
A first plurality of 48 ‘taps’ are provided on the first-stage ISM 430″ for accessing adjacent and horizontal ones of the 2×RL's. A second plurality of 48 more ‘taps’ are provided on the first-stage ISM 430″ for accessing adjacent and vertical ones of the 2×RL's. These 96 taps allow the first-stage ISM 430″ to selectively acquire signals from a respective 96 duo-reach access wires associated with bus 433 (and with duo-deca switchbox 460″). The selected subset of the 96 tap-able duo signals (433) that may be acquired by ISM-1 can then be routed to ISM-2 (440″) via the interstage bus 435. Although
While substantially equivalent coupling into the associated BOSM 450″ is provided for all eight (8) of the respective GLB result signals W0, W1, . . . , Z1 that are output pair-wise and respectively from the four Configurable Building Blocks (CBB's, e.g., 402) shown in
The illustrated, Longline OSM's 480″ (LOSM) may be collectively thought of as comprising an intersecting set of four horizontal, matrix input lines (H4) and twenty-four vertical, matrix output lines (V24) whose intersections are fully populated by a set of ninety-six PIP's. As a result, any of the W0, X0, Y0 and Z0 signals may be routed to any one of twenty-four tristateable buffers associated with GLB 201. The latter tristateable buffers (486) receive their respective inputs from output lines 482″ and 484 of the H&V longline OSM's 480″. Symbols 485–486 represent the set of twenty-four (x24) tristateable longline drivers and their respective output enable terminals (OE). In one embodiment, 16 of the twenty-four MaxRL's that can be driven by the HVOSM 480″ extend horizontally along the corresponding horizontal interconnect channel (HIC) adjacent to GLB 401″ while the remaining 8 extend vertically along the corresponding vertical interconnect channel (VIC) adjacent to GLB 401″.
An Input/Output Block (IOB) 420″ is drawn as a dashed box in
Given the unique clustering of immediate destinations for deca-conveyed signals at two of the three tap points on each 10×RL line (e.g., in
At this juncture, it may be beneficial to explain the term “strive” as it applies to what place-and-route software does. It is understood by those skilled in the art of FPGA configuration and of place-and-route software that many design factors may work in unison with, or in opposition to each other while place-and-route software is executing (run time) so as to pull the placement of two or more design components (e.g., where each design component, in the case of the present disclosure, may consume a GLB or a building block inside a GLB) either together toward a shared region of the FPGA or apart. The same concepts apply to routing operations. Because the placements of various design components get shuffled and their routings are re-done as place-and-route operations “anneal” into a convergent place-and-route solution, it is often the case that placement-directed and/or routing-directed “urging factors” are brought into competitive play with one another for urging respective design components to be placed in certain relations to one another and connected in one way or another. It is difficult to know in advance which urging factors will win and which will lose. Thus, the best that could be said in this regard is that certain urging factors should be “attached” to the placement and routing rules that might affect the re-partitionable components of a tightly-packed, and therefore-clusterizable, circuit design so as cause the place-and-route software to “strive” to partition the design appropriately and pack the components, and adjust their relative placements in close together GLB's so as to try to exploit the general interconnect (e.g., 2×RL and 10×RL lines) described herein. There is no guarantee that such will ultimately happen in a given run of the place-and-route software and for a given design implementation problem.
In one embodiment, there are no bridges other than the FT's for transferring signals from MaxRL lines to other interconnect conductors (e.g., 2×RL lines, 10×RL lines—if passed from the BOSM and through a switchbox). Accordingly, the feedthroughs (FT's) must be used in that embodiment if a signal that is being broadcast on a given MaxRL line is to be further distributed orthogonally or otherwise by other GLB-interconnect lines. The 2×RL and/or 10×RL lines may be used for such distribution of a given signal from a MaxRL line to a cluster of GLB's.
While not illustrated in detail, it is within the contemplation of the disclosure to provide within computer-readable media (e.g., floppy diskettes, CD-ROM, DVD-ROM) and/or within manufactured and/or transmitted data signals, FPGA-configuring bit streams for programmably configuring a hierarchical general interconnect in accordance with the above disclosure and/or to provide computer-understandable instructions to computers for causing the computers to perform automated place-and-route operations for the automated generation of FPGA configuration data in accordance with the present disclosure.
Reservation of Extra-Patent Rights, Resolution of Conflicts, and Interpretation of Terms
After this disclosure is lawfully published, the owner of the present patent application has no objection to the reproduction by others of textual and graphic materials contained herein provided such reproduction is for the limited purpose of understanding the present disclosure of invention and of thereby promoting the useful arts and sciences. The owner does not however disclaim any other rights that may be lawfully associated with the disclosed materials, including but not limited to, copyrights in any computer program listings or art works or other works provided herein, and to trademark or trade dress rights that may be associated with coined terms or art works provided herein and to other otherwise-protectable subject matter included herein or otherwise derivable herefrom.
If any disclosures are incorporated herein by reference and such incorporated disclosures conflict in part or whole with the present disclosure, then to the extent of conflict, and/or broader disclosure, and/or broader definition of terms, the present disclosure controls. If such incorporated disclosures conflict in part or whole with one another, then to the extent of conflict, the later-dated disclosure controls.
Unless expressly stated otherwise herein, ordinary terms have their corresponding ordinary meanings within the respective contexts of their presentations, and ordinary terms of art have their corresponding meanings within the relevant technical arts and within the respective contexts of their presentations herein.
The present disclosure is to be taken as illustrative rather than as limiting the scope, nature, or spirit of the subject matter claimed below. Numerous modifications and variations will become apparent to those skilled in the art after studying the disclosure, including use of equivalent functional and/or structural substitutes for elements described herein, use of equivalent functional couplings for couplings described herein, and/or use of equivalent functional steps for steps described herein. Such insubstantial variations are to be considered within the scope of what is contemplated here. Moreover, if plural examples are given for specific means, or steps, and extrapolation between and/or beyond such given examples is obvious in view of the present disclosure, then the disclosure is to be deemed as effectively disclosing and thus covering at least such extrapolations.
Given the above disclosure of general concepts and specific embodiments, the scope of protection sought is to be defined by the claims appended hereto. The issued claims are not to be taken as limiting Applicant's right to claim disclosed, but not yet literally claimed subject matter by way of one or more further applications including those filed pursuant to 35 U.S.C. §120 and/or 35 U.S.C. §251.