US 7007056 B2 Abstract A memory address generating method in which a memory bank index and an address control signal, that are required for a series of FFT processes in which a plurality of butterfly input samples are concurrently read from the same number of memory banks, a butterfly calculation is performed thereon by using the plurality of butterfly input samples, and the results are concurrently stored at the same position with the input samples, are calculated within a fixed small delay time by using a differential parity counter.
Claims(25) 1. A memory address generating method comprising: a plurality of butterfly input samples are concurrently read from the same corresponding number of sample memory banks, a butterfly calculation is performed by using the plurality of butterfly input samples, and a memory bank index and an address control signal required for a series of Fast Fourier Transform (FFT) processes for storing the results at the same position as that of the input samples, are calculated within a fixed small delay time by using a differential parity counter, wherein the differential parity counter comprises: a multiplexer unit for calculating a parity change value for every clock cycle of a data counter; a NOT gate for inverting an output signal of the multiplexer unit; an AND gate unit for calculating a count of the data counter and outputting a signal to control the multiplexer unit; a flip-flop for storing a current parity value (pr); and an XOR gate for XORing the current parity value and a parity chance value (q
0) outputted from the NOT gate to calculate the next parity value (in_pr), and storing the next parity value (in_pr) in the flip-flop.2. The method of
3. The method of
4. The method of
5. The method of
6. The method of
7. The method of
8. The method of
9. A memory address generating method comprising: a data input step for receiving a time domain data for every clock cycle and concurrently storing it in a sample memory bank-0 and a sample memory bank-1; a butterfly calculation step for reading two time domain data from the sample memory bank-0 and the sample memory bank-1 and performing a butterfly calculation thereon according to each stage together with a twiddle factor, and concurrently storing frequency domain data in each sample memory bank as two resultant data; a data output step for receiving the two frequency domain data and outputting it to an output terminal one by one for every clock cycle through a multiplexer; and generating a memory address of the sample memory bank using a differential parity counter for calculating a parity as a bank index of the sample memory, wherein the differential parity counter comprises: a multiplexer unit for calculating a parity change value for every clock cycle of a data counter; a NOT gate for inverting an output signal of the multiplexer unit; an AND gate unit for calculating a count of the data counter and outputting a signal to control the multiplexer unit; a flip-flop for storing a current parity value (pr); and an XOR gate for XORing the current parity value and a parity chance value (q
0) outputted from the NOT gate to calculate the next parity value (in_pr), and storing the next parity value (in_pr) in the flip-flop.10. The method of
11. The method of
12. The method of
13. A sample memory address generating apparatus comprising: a sample memory bank-0 and a sample memory bank-1 in which input and output data at each stage of a butterfly calculation are stored at the same position or read therefrom; a sample memory address generator for generating a memory address of the sample memory bank, wherein the memory address generator comprises a differential parity counter comprising: a multiplexer unit for calculating a parity change value for every clock cycle of a data counter; a NOT gate for inverting an output signal of the multiplexer unit; an AND gate unit for calculating a count of the data counter and outputting a signal to control the multiplexer unit; a flip-flop for storing a current parity value (pr); and an XOR gate for XORing the current parity value and a parity chance value (q
0) outputted from the NOT gate to calculate the next parity value (in_pr), and storing the next parity value (in_pr) in the flip-flop.14. The apparatus of
a coefficient memory for storing a twiddle factor, coefficient of the butterfly calculation;
a coefficient memory address generator for generating an address of the coefficient memory;
a butterfly calculator for receiving the data from the sample memory bank and the coefficient from the coefficient memory, and performing a butterfly calculation on them;
a multiplexer for receiving the data outputted from the sample memory bank and a bank index from the memory address generator, and outputting an FFT calculation result; and
a controller for outputting a counter value to control an operation of the apparatus.
15. The apparatus of
a butterfly counter deforming unit for calculating an address of the sample memory bank.
16. A memory address generating apparatus comprising: a sample memory bank-0 and a sample memory bank-1 for concurrently storing or reading an input data and an output data of a butterfly calculation operation, a sample memory address generator for generating a parity and an address of the sample memory bank and outputting them; a butterfly calculator for concurrently reading input data of the sample memory bank, performing a butterfly calculation on them, and outputting and storing the calculation result in the sample memory bank; and a multiplexer for receiving the data outputted from the sample memory bank and a bank index from the sample memory address generator, and outputting a Fast Fourier Transform (FFT) calculation result; wherein the memory address generator comprises a differential parity counter for calculation a parity as a bank index having a fixed small delay time and a butterfly counter deforming unit for calculating an address, so as to have the same memory bank index and address in inputting and outputting data at each stage: wherein the differential parity counter comprises: a multiplexer unit for calculating a parity change value for every clock cycle of a data counter; a NOT gate for inverting an output signal of the multiplexer unit; an AND gate unit for calculating a count of the data counter and outputting a signal to control the multiplexer unit; a flip-flop for storing a current parity value (pr); and an XOR gate for XORing the current parity value and a parity chance value (q
0) outputted from the NOT gate to calculate the next parity value (in_pr), and storing the next parity value (in_pr) in the flip-flop.17. The apparatus of
a controller for generating a counter value to control an operation of the apparatus in a fast Fourier transforming operation.
18. The apparatus of
a data counter for increasing a data count (d
6˜d0) in a positive direction from ‘0’ for every clock cycle;a butterfly counter for increasing a butterfly count (b
5˜b0) in a positive direction for every clock cycle; anda pass shift register (p
6˜p0) for performing a shift operation for every pass stage.19. The apparatus of
a coefficient memory for storing a twiddle factor, butterfly calculation coefficient; and
a coefficient memory address generator for generating an address of the coefficient memory.
20. The apparatus of
21. The apparatus of
a multiplexer for selecting one of a specific one bit (d
0) of the data counter and a parity change value (g1);a multiplexer for selecting one of a specific one bit (d
2) of the data counter and a parity change value (g2) and outputting it as the parity change value (g1); anda multiplexer for selecting one of a specific bit (d
4) of the data counter and a parity change value (g3=d6) and outputting it as the parity change value (g2).22. The apparatus of
an AND gate for ANDing two specific bits (d
0) (d1) of the data counter and outputting its result as a first control signal of the multiplexer unit;an AND gate for ANDing two specific bits (d
2) (d3) of the data counter and outputting its result as a selected control signal of the multiplexer unit; andan AND gate for ANDing two specific bits (d
4) (d5) of the data counter and outputting its result as a third control signal of the multiplexer unit.23. The apparatus of
24. The apparatus of
25. The apparatus of
Description 1. Field of the Invention The present invention relates to a fast Fourier transform (FFT) system, and more particularly, to an effective memory address generating apparatus and method for implementing a calculation module of a fast Fourier transform (FFT). 2. Description of the Background Art In general, according to a Fourier theorem that one signal can be expressed as the sum of an infinite number of sinusoidal signals, a signal in the time domain or the frequency domain can be transformed to the corresponding domain through a Fourier transform and an inverse Fourier transform. A discrete Fourier transform (DFT) transforms a discrete temporal signal expressed as a linear combination of sinusoidal signals having different frequencies into a frequency domain signal of sinusoidal signals and magnitude, which is widely adopted in a digital signal analysis and their fields of application. A fast Fourier transform (FFT), devised to reduce the complexity of the discrete Fourier transform (DFT), is an algorithm minimizing calculation complexity by using a symmetry characteristic of the discrete Fourier transform when the number of input samples is the square value of ‘2’. This algorithm is widely used as a practical application of the discrete Fourier transform. The fast Fourier transform is divided into a decimation in frequency (DIF) algorithm and a decimation in time (DIT) algorithm depending on a derivation method of a formula, and the DIT algorithm, which is widely used, will be mainly described in the present invention. As shown in As shown in The FFT calculation method will now be described. First, time domain input data is stored according to a predetermined order. At this time, the input data storing order is that an input data index is represented as a binary number and the order of the value is reversed, which is called a bit reversed addressing. Thereafter, the inputted data is processed according to the butterfly calculation determined for each stage like the flow of data as shown in At this time, the calculated frequency domain output data of the FFT is stored in ascending order from ‘0’ and outputted, unlike the input data. However, the FFT method still suffers from many problems with respect to an algorithm operation for implementing faster and more effective hardware in spite of being effective compared to the DFT method. A method for implementing the FFT algorithm at a high speed will now be taken as an example. M. C. Pease (M. C. Pease, “Organization of large scale Fourier processors” J. Assoc. Comput. Mach. Vol. 16, pp. 474–482, July 1969) has proposed a memory operating method that concurrently reads and writes a memory for a fast processing speed. This method stores mutually different input/output data of the butterfly calculation operation in different memory banks (a divided memory unit) in order to concurrently read and write them. As shown in Accordingly, the whole data are divided and stored in two memory banks, and an input and an output of the butterfly operation are mutually different memory banks over the entire stage. Meanwhile, D. Cohen (D. Cohen, “simplified control of FFT hardware” IEE Trans. Acoust., Speech Signal Processing, vol. ASSP-24, pp. 577–579, Dec. 1976) and L. G. Johnson (L. G. Johnson, “Conflict free memory addressing for dedicate FFT hardware” IEEE Trans. Circuits Syst. II, vol. 39, pp 312–316, May 1992) have proposed a fast and effective FFT hardware implementing method on the basis of the memory operating method such as in However, in case of such method, the index calculation of the memory bank uses the general parity calculation method. Thus, if the size of the FFT is increased, there is a large delay time in calculating a parity, so that this method is not suitable for implementing a fast FFT hardware. In addition, Y. Ma (Y. Ma, “An effective memory addressing scheme for FFT processors,” IEEE Trans. Signal Processing, vol.47, pp. 907–911, March 1999) and L. Wanhammar (Y. Ma and L. Wanhammar, “A Hardware Efficient Control of Memory Addressing for High-Performance FFT processors,” IEEE Trans. Signal Processing, vol. 48, No.3, March 2000) have proposed a fast FFT memory operating method in which the calculation of a bank index is fast and simple, instead of using an in-place method (an input and an output of calculation are stored in the same position) such as in the aforementioned method proposed by M. C Peace. However, this method has problems in that it is difficult to implement an algorithm, a register is additionally required besides a given memory since it does not employ the in-place method, and an FFT structure of a pipeline method is necessarily used, causing a latency time. Therefore, an object of the present invention is to provide a memory address generating apparatus and method that are capable of simplifying a calculation process by performing a data input and output by using the same memory bank index and address at each stage of a butterfly calculation. Another object of the present invention is to provide a memory address generating apparatus and method that are capable of calculating a parity value by using a differential parity counter having a fixed small delay time regardless of the size of the FFT. Still another object of the present invention is to provide a memory address apparatus and method that are capable of implementing an algorithm with only a minimum memory without using a register, by using an in-place method and which is adaptable to an FFT hardware with a structure which performs a butterfly calculation in a single clock cycle. To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a memory address generating apparatus including: a plurality of sample memory bank structures in which an input data and an output data are stored at the same position or read therefrom at each stage of a butterfly calculation; and a memory address generator for calculating a memory bank index and an address within a fixed small delay time in order to generate an address of the sample memory bank. To achieve the above objects, there is also provided a memory address generating method in which a memory bank index and an address control signal, that are required for a series of FFT calculations in which a plurality of butterfly input samples are concurrently read from the same number of memory banks, a butterfly calculation is performed thereon by using the plurality of butterfly input samples, and the results are concurrently stored in the same position as the input samples, are calculated within a fixed small delay time by using a differential parity counter. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. As shown in As for the sample memory banks-0 and -1 As shown in The sample memory address generator Accordingly, the sample memory address generator The differential parity counter The multiplexer unit The AND gate unit The butterfly counter deforming unit The memory address generating method of the present invention will now be described. As shown in That is, a memory bank index and an address control signal, that are required for a series of FFT processes in which butterfly input samples of the sample memory banks-0 and -1 The memory address generating method of the present invention will now be described in more detail by taking an 8-point FFT of a DIT algorithm as an example. First, a data input step of the present invention is as follows. A time domain data, an input value of an FFT, is stored in the sample memory banks At this time, as the output value of the data counter of the controller For example, on the assumption that a binary representation of the data counter This can be generalized and adopted to the N-point FFT as follows. On the assumption that a binary representation of the data counter is {d(n−1), d(n−2), . . . , d Thereafter, a butterfly calculation process of the present invention is as follows. A butterfly calculation is performed on the data stored in the sample memory banks That is, two data are read from each of the sample memory banks At this time, an input address and an output address of the sample memory banks For example, on the assumption that a binary representation of the pass shift register That is, in performing a butterfly calculation at an arbitrary stage, an input address and an output address of the sample memory bank-0 At this time, as the input and output addresses of the sample memory bank-1 This is generalized as defined above and adopted to the N-point FFT as follows. On the assumption that a binary representation of the pass shift register That is, the input and output addresses a(m) of the sample memory bank-1 A data output process according to the butterfly calculation is as follows. A frequency domain data stored in the sample memory bank-0 and -1 At this time, as the data counter For example, on the assumption that a binary representation of the data counter is {d This is generalized as defined above and adopted to the N-point FFT as follows. On the assumption that a binary representation of the data counter Meanwhile, as shown in First, in the differential parity counter At this time, the multiplexer unit Thereafter, an output value (g This operation is repeatedly performed as the clock proceeds, of which waveforms for output values of each part are as shown in As shown in As shown in As so far described, the memory address generating apparatus and method of the present invention have many advantages. That is, for example, first, the memory address allocation method is improved so that a high speed FFT hardware irrespective of the size of the FFT can be implemented while concurrently reading and writing an input and output data of a butterfly. Secondly, since a circuit having a fixed small delay time irrespective of the FFT size is used for a parity calculation required for the memory bank, the slow parity calculation problem according to the method proposed by D. Cohen and L. G. Johnson is solved. Thirdly, the memory bank of the input and output data and the address value are identical to each other, and a circuit for calculating the value can be simply implemented. Thirdly, since the present invention employs the in-place method, a use of memory is minimized in implementing an FFT hardware, Fourthly, the algorithm of the present invention can be also adopted to an FFT hardware with a structure performing a butterfly calculation in a single clock cycle, not a pipeline structure. Lastly, besides the DIT method as described above, the present invention can be also adopted to the DIF method and an FFT having various radix values. Thus, the memory address generating apparatus and method of the present invention can be adopted to an orthogonal frequency division multiplexing (OFDM) modulation method in a high speed digital communication sector, a frequency domain equalizer (FDE), and a frequency domain echo canceller so as to realize a high speed operation at the same cost. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalence of such metes and bounds are therefore intended to be embraced by the appended claims. Patent Citations
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