US 7010738 B2 Abstract A combinational circuit comprises: a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2
^{m}) (m is an integer equal to or greater than 2), wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, according to the present invention, these multipliers each include an adder connected between an AND calculator and an output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common.Claims(19) 1. A combinational circuit comprising:
a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2
^{m}), where m is an integer equal to or greater than 2,wherein said multipliers include
an input side XOR calculator,
an AND calculator, and
an output side XOR calculator, and wherein said multipliers share said input side XOR calculator.
2. The combinational circuit according to
3. The combinational circuit according to
an error location calculator that calculates an error location for a digital signal transmitted using wavelength division multiplexing, and
for an error value calculator.
4. The combinational circuit according to
5. The combinational circuit according to
6. The combinational circuit according to
7. A combinational circuit for performing a logical sum calculation for Galois extension field GF(2
^{m}), where m is an integer equal to or greater that 2, comprising:
a plurality of multipliers, each of which includes an adder connected between an AND calculator and an output side XOR calculator,
wherein said output side XOR calculator is used in common, and
wherein outputs of said AND calculators in said multipliers are added by said adders, and addition results are calculated by said output side XOR calculator that is used in common.
8. The combinational circuit according to
9. The combinational circuit according to
an error location calculator for calculating an error location for a digital signal transmitted using wavelength division multiplexing, and
an error value calculator.
10. The combinational circuit according to
11. The combinational circuit according to
12. The combinational circuit according to
13. An encoder including the combinational circuit according to
14. A decoder including the combinational circuit according to
15. A semiconductor device used for processing a digital signal, said device comprising:
input means, for receiving a coded digital signal;
processing means, for processing said coded digital signal and for calculating coefficients of error locator polynomial and coefficients of error value polynomial; and
output means, for outputting a digital signal obtained by correcting errors using said coefficients of error locator polynomial and said coefficients of error value polynomial,
wherein said input means is constituted by a sequential circuit, and said processing means is constituted by a combinational circuit, and
wherein said combinational circuit includes:
a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2
^{m}), where m is an integer equal to or greater than 2,wherein said multipliers include
an input side XOR calculator,
an AND calculator, and
an output side XOR calculator, and
wherein said multipliers share said input side XOR calculator.
16. The semiconductor device according to
17. The semiconductor device according to
18. The semiconductor device according to
19. A semiconductor device used for processing a digital signal, said device comprising:
input means, for receiving a coded digital signal;
processing means, for processing said coded digital signal and for calculating coefficients of error locator polynomial and coefficients of error value polynomial; and
output means, for outputting a digital signal obtained by correcting errors using said coefficients of error locator polynomial and said coefficients of error value polynomial,
wherein said input means is constituted by a sequential circuit, and said processing means is constituted by a combinational circuit, and
wherein said combinational circuit includes:
a logical sum calculator for a Galois extension field GF(2
_{m}), where m is an integer equal to or greater than 2,wherein said multipliers include an adder connected between said AND calculator and said output side XOR calculator,
wherein said output side XOR calculator is used in common, and
wherein outputs of said AND calculators in said multipliers are added by said adders, and addition results are calculated by said output side XOR calculator that is used in common.
Description 1. Field of the Invention The present invention relates to a combinational circuit, and an encoder, a decoder and a semiconductor device that use this combinational circuit. More specifically, the present invention relates to a combinational circuit that can effectively correct errors, especially in a fast optical communication field, and an encoder, a decoder and a semiconductor device that use this combinational circuit. 2. Brief Description of the Prior Art Importance of Fast and Superior Error Correction Technique In consonance with the expansion of the Internet and the development of e-business, the rate of increase in the volume of data computers can handle and their speed has accelerated. Accordingly, there is a demand for increasing speed of data transfer among computers, and in line with this demand, optical communication that yields transfer speed of up to 40 Gbps is becoming popular. However, for such a fast communication method such as the optical communication method, to maintain an acceptable error rate at system level requires that the reliability of data communication be further increased in proportion to the amount of data processed by a computer. Important techniques, called error correction coding techniques, have been devised to improve data reliability employing high-level mathematics to automatically correct errors caused by a variety of factors (e.g., noise along a channel). Popular known techniques are Hamming code and Reed-Solomon code, both of which are frequently employed. Basically, Hamming codes correct single bit errors, but their correction capability is low. For instance, with Hamming codes, if a single bit error is detected, the error is corrected, but if the detected error covers two bits, only the error detection portion of the process is performed, no correction is made. However, setting up an error correction process for an error correction system using Hamming code is simple, and it is well known that by performing the error correction process in parallel, a processing speed that greatly exceeds 1 Gbps (one billion bits per second) can be obtained. On the other hand, Reed-Solomon code is a superior error correction technique possessing high correction capabilities and can be used to correct errors appearing as units (symbols) comprising multiple contiguous bits. At present, however, because of the complicated calculations that are frequently required, using Reed-Solomon code to perform correction processes in parallel is difficult; and even when pipeline processes using data having eight-bit width are performed at 100 MHz, for example, only processing speed of around 800 Mb/s can be obtained. Currently, therefore, since the speed attainable with conventional techniques using Reed-Solomon codes is not suitable for fields in which high processing speed is required, these techniques are employed mainly for fields to which comparatively low data processing speed is acceptable, such as the low speed communication field and the data storage-unit field for the production of hard disks or secondary storage devices, CD-ROMs, for example. Error Correction Technique Required by a Fast Optical Communication Field As part of a fast optical communication technique for data communication by computers, by the recently popular Internet as a backbone, a terabit per second fast communication system that employs WDM (Wavelength Division Multiplexing) and DWDM (Dense WDM), which has improved wavelength division multiplexing levels, has been introduced based on the SONET technique, according to which frames having a predetermined length are synchronously and sequentially transmitted. As the wavelength division multiplexing levels for the above described optical data communication is increased, crosstalk occurs between wavelengths that are near each other. To cope with this crosstalk, FEC (Forward Error Correction) is employed as an error correction method for communication in long distance (Long Haul) optical wavelength division multiplexing. In ITU-T G.975, the ITU (International Telecommunication Union) standardized the use of interleaved (255, 239)RS code (code length n=255 bytes) of m=8 (8 bits/symbols), and in G.709, the Digital Wrapper standard for defining the FEC frame structure is employed. According to the Digital Wrapper standard, for example, low-speed serial Reed-Solomon code circuits are arranged in parallel to achieve a necessary processing capability, and for this, interleaving of Reed-Solomon codes is an indispensable technique. Prior Art for Fast and High-Level Error Correction Techniques Independent of the need for optical communication, parallel fast decoding using Reed-Solomon code has been studied using a combinational circuit. Since the decoding circuit in When the decoding circuit in However, the decoding circuit in According to OC-768 SONET, this is a large problem, because assuming the 16 interleave defined by ITU-G709 is employed as an input/output interface for the decoding circuit, a fast processing speed of 300 MHz or higher is expected. Therefore, as one attempt, the decoder in However, even when the process is converted into a pipeline, the decoding circuit in For the calculation of error locations and error values used for the decoder, a large number of calculations in the Galois extension field GF(2 During the studies of the error correction calculation algorithm, the Yule-Walker equation that is defined for the Galois extension field GF(2 In addition, when a combinational circuit that can carry out the decoding of Reed-Solomon codes is applied for an actual system, it is preferable that an algorithm be provided that can be applied for the decoding of Reed-Solomon codes having an arbitrary minimum distance in order to obtain a process that can be widely used and to remove superfluous, additional circuits or processes. Especially in the optical communication field, since the use of (255, 239) Reed-Solomon code is standardized by the ITU, an algorithm is required that can efficiently decode the Reed-Solomon code where the maximum number of correctable errors is 8 and the minimum distance is 17. In order to solve the mathematical problem posed by the Yule-Walker equation by using a hardware combinational circuit having a size that permits it to be implemented, increase in the circuit size must be suppressed, and an algorithm that can reduce the number of multipliers and a combinational circuit that can efficiently employ this algorithm are required. That is, a combinational circuit is needed that has an implementable size and that performs high-speed processing, and that includes the error correction device and the error correction algorithm described above. To resolve the above shortcomings, it is one object of the present invention to provide an efficient combinational circuit for processing interleaved Reed-Solomon codes, and a signal processor and a semiconductor device that use this combinational circuit, for fast optical communication (40 Gbps or higher), or more specifically, for SONET using wavelength division multiplexing communication, in which sequential data are transferred as synchronous frames. That is, according to the invention, a combinational circuit, which has a high processing capability (low latency and high throughput), and an encoder, a decoder and a semiconductor device that employ the combinational circuit are provided. It is another object of the present invention to provide a flexible combinational circuit that can process interleaved Reed-Solomon codes without losing the above described characteristics, and an encoder, a decoder and a semiconductor device that employ the combinational circuit. It is an additional object of the present invention to provide a combinational circuit that sequentially outputs error words at high speed and at a constant cycle rate, regardless of error patterns (error values and error locations) of each interleaved received word, and an encoder, a decoder and a semiconductor device that employ the combinational circuit. It is a further object of the present invention to provide a combinational arithmetic circuit, circuits over a Galois extension field GF(2 To perform the decoding of Reed-Solomon codes by a combinational circuit and to apply this combinational circuit to an actual system, it is a still further object of the present invention to provide a combinational circuit that can provide a flexible process that can be applied for the decoding of Reed-Solomon codes having an arbitrary minimum distance and interleave configurations without an additional circuit or process being required, and to provide an encoder, a decoder and a semiconductor device that employ the combinational circuit. The above objects can be achieved by providing a combinational circuit according to the present invention, and an encoder, a decoder and a semiconductor device that employ the combinational circuit. According to the present invention, a combinational circuit comprises: -
- a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2
^{m}) (m is an integer equal to or greater than 2), - wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. In the combinational circuit of this invention, the input of the multipliers is commonly used. The combinational circuit is used for an error location calculator that calculates error locations for a digital signal transmitted using wavelength division multiplexing, and for an error value calculator. Syndromes obtained by the coded digital signal are input. The combinational circuit of this invention is used for decoding, error correction or encryption. The combinational circuit of the invention is used for a coding circuit and a decoding circuit for cryptography.
- a plurality of multipliers, independently performing two or more multiplications for coded digital signals in a Galois extension field GF(2
According to the invention, a combinational circuit performing logical sums for a Galois extension field GF(2 Further, according to the invention, an encoder and a decoder including the combinational circuit are provided. According to the invention, a semiconductor device used for processing a digital signal comprises: -
- input means, for receiving a coded digital signal;
- processing means, for processing the coded digital signal and for calculating coefficients of an error locator polynomial and coefficients of an error value polynomial; and
- output means, for outputting a digital signal by correcting errors using the error locator polynomial and the error value polynomial,
- wherein the input means is constituted by a sequential circuit, and the processing means is constituted by a combinational circuit. In this invention, the combinational circuit comprises:
- a plurality of multipliers, independently performing two or more multiplications for coded digital signals over a Galois extension field GF(2
^{m}) (m is an integer equal to or greater than 2), - wherein the multipliers include an input side XOR calculator, an AND calculator, and an output side XOR calculator, and wherein the multipliers share the input side XOR calculator. Further, in this invention, the combinational circuit comprises: a logical sum calculator for a Galois extension field GF(2
^{m}) (m is an integer equal to or greater than 2), and the multipliers each include an adder connected between the AND calculator and the output side XOR calculator, wherein the output side XOR calculator is used in common, and wherein the outputs of the AND calculators in the multipliers are added by the adders, and the addition results are calculated by the output side XOR calculator that is used in common. In the semiconductor device of the invention, the input of the multipliers is commonly used, and the input side XOR calculator is used in common by the multipliers. The combinational circuit is used for an error location calculator, for calculating error locations for a digital signal transmitted using wavelength division multiplexing, and for an error value calculator. The semiconductor device of this invention is used for decoding, error correction or encryption.
The preferred embodiment of the present invention will now be described by referring to the accompanying drawings. Note, however, that the present invention is not limited to this embodiment. Section In this invention, the digital signal ID input to the decoder in In the decoder design in the invention in As is shown in In the decoder in The error locator polynomial Λ(x) and the error value polynomial Er(x), which are output by the processor In the decoder in In the decoder of the invention in The method or the algorithm of the invention for the error locator polynomial calculation will, along with the combinational circuit, be described in detail later. An explanation will now be given for the function and the operation of the error value polynomial calculator Selection of an Error Value Calculation Algorithm According to the invention, an algorithm that can directly evaluate not only error locations but also error values through the calculation of the 0(t)-degree polynomial (linear calculation) is applied for the decoding of interleaved Reed-Solomon codes. At this time, in the algorithm used for this invention, the division necessary for an error value calculation is not performed for each error location on a critical path that is output following the evaluation of a polynomial, but by using only one calculation for each code word before the evaluation of a polynomial. Therefore, the values obtained by the polynomial evaluation can be directly output as error values at high speed at a constant cycle rate. Further, it has been found that the degree of the error value polynomial Er(x) can be reduced to the t− Various error value polynomials can be used for the decoding algorithm or the decoding method of the invention. In the explanation of the function and the operation of the invention, the following example is employed wherein when e errors have occurred at i The error value polynomial Er The above process can be performed by using the following decoding algorithm or decoding method. First, the denominator is written by Λ The error locations a When the above determinant is employed, the denominator of Er As is described above, when these new relations are employed, the output unit The following configuration is employed to constitute a fast, small coding circuit that can also cope with interleaved codes based on the above error value calculation algorithm. (1) Use of Fast Input Unit and Output Unit (Linear Operating Circuit) First, in consideration of the structure of the code (the number of interleaves), the bus width of an input/output interface and the number of clocks, a polynomial evaluation (linear operating) circuit, which is connected to the input side to calculate syndromes, and a polynomial evaluation (linear operating) circuit, which is connected to the output side to evaluate error locations and error values, are implemented as fast sequential circuits that employ a cyclic structure that comes from the fact that RS codes are cyclic codes, and that perform a pre-process and a post-process for (n, k) Reed-Solomon code at an arbitrary number of clocks from 1 to n. Especially effective for the invention is the fact that the above described structure is also employed for an error value evaluation portion that is a critical path for the conventional method. According to the structure of the invention, a decoding circuit can be provided as an interface that can flexibly cope not only with an input digital signal that has 255 bytes for each code word, but also with ones that have 1, 3, 5, 15, 17, 51 and 85 bytes. Table 1 shows the relation between the width of a digital signal input to the decoding circuit and the processing clock required for this input width.
As is shown in Table 1, although the required number of clocks is increased as the width of the input digital signal is reduced, the decoder of the invention can flexibly cope with it. In addition, in this invention, an arbitrary input/output byte width other than those in Table 1 can be selected for each code word. For example, an input/output width of eight bytes can be coped with when the code length is n=256 bytes by adding a one byte dummy at the end. (2) Connection to a Non-Linear Operating Circuit In this invention, a plurality of input units (3) Three-Stage Pipeline Operation System That Employs the Non-Linear Operating Circuit in the Center in a Time Sharing Manner According to the present invention, the entire decoder is operated as a three-stage pipeline formed from a linear operating circuit (syndrome calculation), a non-linear operating circuit (calculation of coefficients for error locator and error value polynomials) and a linear operating circuit (evaluation of error locations and error values), and the non-linear operating circuit of a low latency is employed in a time sharing manner by serially providing syndromes for code words for the calculation of interleaved code. Therefore, it is possible to provide efficient decoding of interleaved codes whose processing capability per circuit size is high. In the OC-768 case, for example, in order to operate the three-stage pipeline, the non-linear operating circuit in the center must complete the process for each interleaved code word at a latency of about 40 ns. When the combinational circuit is implemented by the most advanced semiconductor technique (0.18 μm or better), the above decoder can be provided as an ASIC semiconductor device. More specifically, in the invention, fast decoder and error correction devices, the sizes of which fall within an acceptable range, can be provided by synergistic effects obtained by: (1) the use of a fast input unit Section The processor Configuration of a Single Parallel-Multiplier While many studies have been made of a single multiplier, a parallel multiplier (Mastrovito Multiplier), which is constituted as a combinational circuit, not as a sequential circuit, is a field of active research. For a conventional parallel multiplication circuit (hereinafter, in this specification, referred to simply as a multiplier), there are two configuration types: the AND-XOR type and the XOR-AND-XOR type, which can be converted into each other. It should be noted, however, that the AND-XOR type is generally employed when a circuit is provided for only a single multiplication. This is because while the AND-XOR type has been well studied and various methods for obtaining a small circuit have been proposed, there is no guarantee that the circuit size for the XOR-AND-XOR type will be reduced (or may be increased), and the reduction effects can not be obtained that would compensate for the expenditure of the effort a complicated design operation would entail. The AND-XOR type and the XOR-AND-XOR type will be further described. (1) AND-XOR Type This is a typical method used for performing calculations in the same manner as are calculations performed with figures written down on paper, and generally a circuit of this type is employed. Specifically, the coefficients of two (m−1)th degree polynomials, which are multiplication arguments, are combined to prepare m (2) XOR-AND-XOR Type Generally, according to the Boolean algebra rule (A and B) xor (A and C)=A and (B xor C), it is possible for the XOR calculation in the residue operation unit of the AND-XOR circuit to be moved in front of the AND for use as a variable pre-processor (input side XOR calculator). Thus, the XOR-AND-XOR multiplication circuit can be obtained. For moving the XOR calculation, when an even number of the same redundant terms are added to the XOR of the residue operation unit (output side XOR calculator) by the properties A xor A=0 and B xor 0=B, many XOR calculations may be moved to the front-end as a pre-processor. Since this operation can be employed, various methods for moving the XOR are available, in addition to the simple application of the distributive law. Therefore, multiple AND-XOR types are present even with the same basis or irreducible polynomial. The number of gates in the XOR-AND-XOR type can vary, and may become either greater or smaller than that in the AND-XOR type. Another method is known whereby the number of XOR gates is systematically reduced by choosing a special basis, such as the Composite Field Multiplier that will be described below. (3) A Method for Constructing an XOR-AND-XOR Type that can be Applied Only for a Limited Field (Composite Field Multiplier) The composite field multiplier is a multiplier construction method that can be used only in a special case, such as where m is a composite number and the basis used for the representation of an element in a field may not be an ordinary basis (such as polynomial basis or normal basis). This method will now be described in detail. When m is a composite number, extension field GF(2 Configuration of a Combinational Circuit According to the Invention Using Ordinary Multipliers In Table 2 shows the numbers of gates that are included in multiplication circuits for a Galois extension field GF(2
AS can be seen from Table 2, as far as only a single multiplier is concerned, the circuit sizes for cases a. to c. are increased when compared with the size of the conventional composite field multiplier, and are not the minimum size. As is described above, when the three-stage XOR-AND-XOR structure is simply employed for a single multiplier, in some cases the circuit size may be increased. Multiplier Structure for a Combinational Circuit According to the Invention Generally, optimization of Boolean algebra is difficult when many multiplications and logical sum calculations are performed together. However, in consideration of the use of the combinational circuit as the processor The outputs of the AND groups Further, in the invention, when the XOR groups Therefore, when, based on the multiplication circuits in Table 2, a part of the decoder is to be constituted by the combinational circuit in
It is apparent from a. to c. in Table 3, that even if the single multiplier is not intentionally minimized, the overall size of the circuit can be reduced. In the embodiment in Section A detailed explanation will now be given for an error correction algorithm that is used by the decoding circuit and the error correction device of the invention. Overview of the Conventional Example A. Conventional Method for Solving the Yule-Walker Equation or for Obtaining an Error Locator Polynomial, and a Problem Associated With These Methods According to the invention, it is necessary to find an efficient algorithm for a combinational circuit to calculate the following simultaneous linear equation, which is defined over GF(2 In this simultaneous linear equation, the matrix on the left has a regular structure wherein the same elements are arranged obliquely to the right (the direction irtersecting the diagonal line), and is called a Hankel matrix. Generally, this type of equation is called a Yule-Walker equation, and it is known that this equation is widely applied for various fields, such as the error correction code theory, time-series analysis and signal processing. In the error correction algorithm, the Yule-Walker equation appears in the portion for determining an error locator polynomial. Therefore, according to the present invention, the algorithm for obtaining the solution for the Yule-Walker equation is applied as an error correction algorithm for decoding the Reed-Solomon codes. The well known methods for solving the Yule-Walker equation are, for example, the algorithm proposed by Levinson and the algorithm proposed by Levinson-Durbin. These algorithms start calculating with a matrix of the smallest size l and recursively determine the solution of an equation wherein the size of a matrix is greater. The number of calculations required by these two algorithms is of order of l Further, as the object of the invention, especially relative to the decoding of the Reed-Solomon codes, an error locator polynomial is determined by obtaining the solution to the Yule-Walker equation. The conventional methods for solving the Yule-Walker equation can be, for example, the Peterson method, the Berlekamp-Massey method and the Euclid method. These methods are used to calculate the coefficients of an error locator polynomial by calculations of which the number is polynomial order with respect to the maximum number of correctable errors t. However, when the Berlekamp-Massey method and the Euclid method are represented by a combinational circuit, the following problems occur. First, for the Berlekamp-Massey method, it is inevitable that multiple conditional branches should be included in the algorithm. Therefore, to expand this algorithm for a combinational circuit, for the same reason as described above, the circuit size would be increased in accordance with the number of combinations. As for the Euclid method, while the multiplication and division of the polynomial are the essential part of the algorithm and, the degree of a polynomial that appears in the denominator of the division can not be identified in advance, so that there is room for generating a conditional branch. Furthermore, clue to the conditional branches, the circuit size is accordingly increased, as it is for the Berlekamp-Massey method. B. Policy for Calculating the Yule-Walker Equation and an Error Locator Polynomial that is Appropriate for a Combinational Circuit Since, as is described above, the Levinson(-Durbin) method, the Berlekamp-Massey method and the Euclid method include conditional branches, a problem has arisen in how to provide these methods as combinational circuits. In order to implement the Yule-Walker equation by a combinational circuit, an algorithm that has no conditional branching must be found, and this is an essential object for the algorithm of the invention. In this case, the Peterson method known for decoding of the Reed-Solomon codes can be used as the algorithm of the invention. Using the Peterson method, the Yule-Walker equation can be solved directly, and the solution of the Yule-Walker equation can be represented as determinants by the Cramer formula:
Therefore, determinants Λ However, when the expansion of the determinants is provided by using a circuit, the required number of multipliers is dramatically increased as t is increased, so that it is difficult for the determinants to be directly expanded. Therefore, in this invention, the number of calculations is reduced by the recursive structure of the Hankel matrix. The calculation of Λ When the calculation algorithm for Λ For comparison, a method devised by Koga will now be described as another method for recursively calculating the Hankel matrix. According to the method by Koga, new error locator polynomial To calculate this new error locator polynomial, the Hankel matrix All of the above described conventional methods have the following problems. First, for the algorithm used in As for the Koga algorithm, the Q determinant defined by Koga is symmetrical, and a reduction in the number of multipliers is carried out. However, there is a limitation on the use of the Koga algorithm; this algorithm can be applied for BCH codes or Reed-Solomon codes only when the minimum distance is an even number. Although it is disclosed in the Koga algorithm that this limitation can be eased, such an application example is limited to the binary, narrow sense BCH code. According to the invention, since the combinational circuit is applied for an optical communication system, it is required as an object that the decoding of the (255, 239) Reed-Solomon code (minimum distance=17) be efficiently carried out by the combinational circuit. Therefore, an algorithm is needed that can perform an efficient calculation by a specific method, regardless of whether the minimum distance is an odd or even number. C. Definitions of Terms Used for this Invention Before a detailed explanation is given for the algorithm of this invention, definitions for the terms used for this invention will be given. (1) Syndrome Generally, when a primitive element of the Galois extension field GF(2 Then, the polynomial (transmission polynomial) that has as coefficients a coded sequence having the length n is defined as
At this time, the coded transmission sequence is represented as systematic code, of which k information symbols are located on the left and h=n−k check symbols follow these symbols. The minimum distance d The following decoding algorithm is given for making an estimation of the original transmission sequence based on a received sequence. (2) Calculation of Syndromes and Detection of an Error Assume that errors have occurred, and that the locations of the errors are denoted by i Then, the reception polynomial Y(x) is employed to calculate the following syndromes:
In this case, since W(a (3) Determination of the Number of Errors and the Location of Errors Assume that the number of errors that occur is 1 and that the location of the error is i Further, Λ The unknown quantities Λ This is nothing but the Yule-Walker equation explained in section A. While at this step “1 ” is an unknown number, it is known that when the number of errors that actually occurred is 1≦e≦t, the Hankel matrix on the left is regular when l=e and is irregular when t≧l>e. Therefore, for l=1, . . . , t, only the determinants for the Hankel matrix on the left need be calculated, and a maximum integer that is not 0 can be defined as the number of errors e. When the above equation is solved with 1=e, the error locator polynomial can be obtained. In this invention, to specify error locations, the error locators, i.e., the roots of error locator polynomial Λ 4. Calculation of Error Values Error values can be obtained by solving the following Vandermonde simultaneous linear equations:
In this case, polynomial S(x), having a syndrome as a coefficient, is defined as
This is called the Forney algorithm. When the error locations and the error values are obtained, only these need be subtracted from an input digital signal, so that a digital signal for which errors were corrected can be output. D. Algorithm to Solve Yule-Walker Equation of this Invention The object of the present inventors is to find an efficient algorithm that employs the combinational circuit to obtain the solution for the following Yule-Walker equation, defined over GF(2 In this invention, by the Cramer formula the solution for the Yule-Walker equation is represented as the determinant form shown in In order to calculate determinants in Jacobi's Formula A=(a In this invention, the following equation
The calculation of Λ First, Λ By careful examination of this determinant, Λ When Jacobi's formula is employed, the calculation of Λ The general form of the algorithm for the recursive calculation of Γ 0. Γ 1. when 1>2, i=1,
2. when 1>2, i=1, . . . , l−1, first, one auxiliary amount for describing the algorithm is defined. When {i Specifically, det [{i In this equation, det [{0, 1, . . . , 1−2}−{l- 3. Generally, det[{ E. Application of the Algorithm of the Invention for the Decoding of the Reed-Solomon Code An explanation will now be given for the embodiment wherein the algorithm of the invention for solving the Yule-Walker equation described in D is applied for the Reed-Solomon codes. Generally, it is assumed that the order of the Yule-Walker equation (the number of unknown quantities) is known. However, for the decoding of the Reed-Solomon codes, since the order is also unknown, this must also be determined. (1) Calculation of Γ When a sequence of syndromes, S D. During this Calculation,
(2) Determination of the Number of Errors Assume that the number of errors that actually occurred is represented as e. Based on the value of
(3) Determination of an Error Locator Polynomial When e<t is established as the result of the determination of the number of errors, since Λ Since the error locator is the zero point of the error locator polynomial, the error locators are values unchanged by multiplication of the coefficients of the error locator polynomial by a constant. Therefore, the following quantity
At this time, according to the algorithm proposed by the present inventors, in appearance, syndrome S It is therefore understood that, of the terms that appear during the cofactor expansion of Λ F. Example of Application of the Error Correction Algorithm of the Invention for the Decoding of Reed-Solomon Codes An explanation will now be given for a case wherein the error correction algorithm explained in E. is employed for the decoding of Reed-Solomon code for t=4. When t=4, according to the invention the following equations are determined. It should be noted that for simplification the determinant is represented as det [{i (1) Calculation of Γ The calculation results obtained by the invention are shown in (2) Determination of the Number of Errors Since {tilde over (Λ)} (3) Determination of an Error Locator Polynomial When, for example, e=2 is ascertained using the calculation in (2), the error locator a When e=4 is ascertained, as is described above, the error locator can be obtained by
It should be noted that, as is described above, the term including the syndrome S G. Calculation Circuit when the Algorithm of the Invention is Applied for the Calculation of an Error Locator Polynomial The functions of the blocks in Following this, the circuit block The algorithm of the invention has been used for the combinational circuit in order to perform fast decoding of the Reed-Solomon codes. However, the algorithm of the invention can also be used for a sequential circuit in order to reduce the circuit size. H. Circuit Size when the Algorithm of the Invention is Used for the Decoding of the Reed-Solomon Codes An explanation will now be given for the size of a circuit when the algorithm of the present invention is used for the decoding of the Reed-Solomon codes. As is described above, the calculation of square roots and the calculation of squares can be performed by a circuit having substantially the same cost as an addition circuit, and compared with a multiplier, the cost required is very small. The present inventors have focused only on the multipliers, and discussed the number of multipliers that are required. Table 4 shows the number of multipliers required by the algorithm of the invention in a range extending from t=1 to t=8. In Table 4, for comparison, the number of multipliers required for each of the conventional examples 1 and 2 is also shown.
As is apparent from Table 4, while taking the required number of multipliers into account, the algorithm proposed in this invention is superior in all number of errors t to the algorithm (conventional example 2) proposed by Koga. Further, the use of an algorithm for the decoding of (255, 239) Reed-Solomon code (t=8) is especially important for the optical communication field; however, the Koga algorithm can not be so employed because the minimum distance of Reed-Solomon code is an odd number (=17). Since the algorithm of the invention can be used for Reed-Solomon codes having an arbitrary minimum distance, it can also be used for (255, 239) Reed-Solomon code. This is shown in Table 5.
The calculation algorithm in conventional example 1 (Katayama-Morioka) can also be used for Reed-Solomon code having an arbitrary minimum distance. However, from the viewpoint of the required number of multipliers into account, when t is equal to or greater than 4, the algorithm proposed in this invention requires a smaller number of multipliers than does the algorithm of conventional example 1. It has especially been found that when t=8, the algorithm of the invention can reduce the number of multipliers by about 50%. And as for a circuit size, when t=8, 10K gates are currently required for the calculation of the error values. For conventional example 1 about 80K gates seem to be required, while the employment of the algorithm of the invention can reduce the gates for the calculation of an error polynomial to about 40K gates. The process block As is described above, according to the present invention, it is possible to provide a combinational circuit that can extremely efficiently correct errors in the fast optical communication field, and an encoder, a decoder and a semiconductor device that employ this combinational circuit.
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