|Publication number||US7022592 B2|
|Application number||US 10/678,783|
|Publication date||Apr 4, 2006|
|Filing date||Oct 3, 2003|
|Priority date||Oct 3, 2003|
|Also published as||US20050073015|
|Publication number||10678783, 678783, US 7022592 B2, US 7022592B2, US-B2-7022592, US7022592 B2, US7022592B2|
|Inventors||Wen-Ting Chu, Yeur-Luen Tu|
|Original Assignee||Taiwan Semiconductor Manufacturing Company, Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (4), Classifications (18), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to the field of semiconductor devices, and more specifically, to semiconductor devices having a split-gate transistor.
Complementary metal-oxide-semiconductor (CMOS) technology is the dominant semiconductor technology used for the manufacture of ultra-large scale integrated (ULSI) circuits today. Size reduction of the semiconductor structures has provided significant improvement in the speed, performance, circuit density, and cost per unit function of semiconductor chips over the past few decades. Significant challenges are faced as the sizes of CMOS devices continue to decrease.
One such problem is seen in devices that utilize poly-oxide structures. For example, split-gate transistors, which are commonly used in memory devices, are generally formed by depositing a polysilicon layer on a wafer. A masking material, such as silicon nitride (Si3N4), is formed and patterned on the polysilicon wafer to define areas that are to become a poly-oxide and a floating gate of the split-gate transistor. The exposed portions of the polysilicon are oxidized, and the masking material is removed. The poly-oxide regions act as a mask during an etching process to remove the unwanted polysilicon. The split-gate transistor is completed by forming an inter-poly oxide layer and a control gate.
During oxidation, however, the polysilicon has a tendency to oxidize along the grain boundaries of the polysilicon. In smaller designs, particularly in designs in which sharp, straight edges are desired, the oxidation along grain boundaries results in irregular etching patterns of the unwanted polysilicon. In some cases, the oxidation along grain boundaries can cause the polysilicon to bridge between elements, thereby rendering the devices inoperative. This phenomena is increasingly troublesome as device sizes decrease.
Therefore, there is a need for semiconductor devices having poly-oxide structures with a reduced amount of oxidation along grain boundaries.
These and other problems are generally reduced, solved or circumvented, and technical advantages are generally achieved, by embodiments of the present invention which provides a semiconductor device having a polysilicon layer treated with ammonia.
In one embodiment of the present invention, a method of forming a polysilicon structure is provided. A polysilicon layer is formed on a substrate and treated with ammonia. The polysilicon layer may then be oxidized. The ammonia treatment reduces the amount of oxidation that occurs along the grain boundaries of the polysilicon layer.
A masking layer may be applied to the polysilicon layer prior to oxidation, thereby limiting the portions of the polysilicon layer that becomes oxidized. In one embodiment, the masking layer is a layer of silicon nitride that has been patterned.
In another embodiment, an apparatus comprising a polysilicon layer treated with ammonia and a poly-oxide layer formed on the polysilicon layer.
In yet another embodiment, a split-gate transistor is provided wherein the floating gate is a polysilicon layer that has been treated with ammonia. The polysilicon layer is then oxidized to form the poly-oxide layer of the split-gate transistor.
In yet another embodiment, a polysilicon layer treated with ammonia is provided, such that the polysilicon layer may be used to fabricate semiconductor devices. The polysilicon layer treated with ammonia may be used to create a split-gate transistor and memory devices.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that embodiments of the present invention provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
For example, one embodiment of the present invention is a memory device having a split-gate transistor, such as a flash electrically erasable and programmable read-only memory (flash EEPROM). Accordingly, the discussions that follow describe a process of fabricating semiconductor structures having a split-gate transistor that may be used to fabricate a flash EEPROM. Embodiments of the present invention, however, may be used for forming semiconductor structures other than split-gate transistors.
The oxide layer 112 may be formed by, for example, an oxidation process. The oxidation step may be, for example, a wet or dry oxidation process such as wet or dry thermal oxidation in an ambient comprising an oxide, H2O, NO, or a combination thereof, or by chemical vapor deposition (CVD) techniques using tetra-ethyl-ortho-silicate (TEOS) and oxygen as a precursor. Preferably, the oxide layer 112 is formed by a wet thermal oxidation process and is about 70 Å to about 150 Å in thickness.
The polysilicon layer 114 is formed on the wafer 100 and will be patterned in subsequent processing steps. The polysilicon layer 114 is generally a semiconductor material such as polysilicon, amorphous silicon, or the like. The polysilicon layer 114 may be deposited doped (e.g., furnace deposition of an in-situ doped polysilicon) or un-doped. If the polysilicon layer 114 is deposited undoped, the polysilicon layer 114 may be doped after the polysilicon layer 114 is formed. The polysilicon layer 114 may be doped with an N-type ion implant process or a P-type ion implant process for fabricating NMOS or PMOS devices, respectively.
The polysilicon layer 114 is subjected to an ammonia (NH3) treatment. It should be noted that the ammonia treatment may be performed before or after doping of the polysilicon layer 114. The ammonia treatment may be performed by, for example, a thermal anneal (e.g., thermal anneal or a rapid thermal anneal (RTA)) in an ammonia ambient. Preferably, the ammonia treatment is performed by a thermal anneal process at a temperature of approximately 700° to 1000° C. for about 5 minutes to about 300 minutes. More preferably, however, the thermal anneal is performed at a temperature of about 800° C. for about 30 minutes.
The hard mask 210 is preferably patterned by applying, exposing, and developing a photoresist mask (not shown). After the photoresist mask has been patterned, an etching step is performed to remove unwanted portions of the hard mask 210. In the preferred embodiment in which the hard mask 210 comprises Si3N4, one commonly used method of etching the hard mask 210 is dry etch process such as, for example, a reactive ion etch (RIE).
In an alternative embodiment, the ammonia treatment may be performed after the hard mask 210 has been formed and patterned, prior to performing the following oxidation step.
It should be noted that polysilicon treated with ammonia decreases the tendency of the polysilicon to oxidize along the grain boundary. By restricting the amount of oxidation along the grain boundary, the polysilicon bridging is reduced when etching the polysilicon layer 114.
It should be noted that the poly-oxide regions 310 act as a mask during the removal of the hard mask 210, protecting the underlying polysilicon from removal. In the preferred embodiment in which the hard mask 210 comprises Si3N4, the hard mask 210 may be removed, for example, in a wet dip in dilute hydrofluoric acid. Another commonly used wafer cleaning solution is a mixture of concentrated sulphuric acid and hydrogen peroxide, commonly referred to as piranha solution. A phosphoric acid solution of phosphoric acid (H3PO4) and water (H2O) may also be used to remove the hard mask 210.
Thereafter, standard processes may be used to complete fabrication of the semiconductor device. For example,
Although particular embodiments of the invention have been described in detail, it is understood that the invention is not limited correspondingly in scope, but includes all changes, modifications, and equivalents coming within the spirit and terms of the claims appended hereto. For example, different materials may be used for substrates, masks, and other structures, different structures may be fabricated, and the like. Accordingly, it is understood that this invention may be extended to other structures and materials, and thus, the specification and figures are to be regarded in an illustrative rather than a restrictive sense.
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|Citing Patent||Filing date||Publication date||Applicant||Title|
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|U.S. Classification||438/488, 257/E27.103, 257/E21.209, 438/494, 257/E21.682|
|International Classification||H01L21/28, H01L21/8247, H01L29/76, H01L31/113, H01L27/108, H01L27/115, H01L21/3205|
|Cooperative Classification||H01L21/28273, H01L27/115, H01L27/11521|
|European Classification||H01L21/28F, H01L27/115, H01L27/115F4|
|Oct 3, 2003||AS||Assignment|
Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.,
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHU, WEN-TING;TU, YEUR-LUEN;REEL/FRAME:014590/0118
Effective date: 20031003
|Sep 2, 2009||FPAY||Fee payment|
Year of fee payment: 4
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Year of fee payment: 8