US 7028282 B2 Abstract A set of high speed interconnect lines for an integrated circuit has an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line set incorporates a series of interconnect lines, wherein shorter run lines are routed between longer run lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without increasing the line-to-line capacitance. The capacitances, resistances, and RC time constants can be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform propagation delay.
Claims(44) 1. A method of adjusting an integrated circuit for a reduced conductor capacitance, comprising:
routing a first subset of generally longer conductors of a set of generally parallel and physically proximate conductors; and
selectively routing a second subset of generally shorter conductors of the set of generally parallel and physically proximate conductors to reduce conductor to conductor capacitance,
such hat in a plan view each member of the second subset of generally shorter conductors is routed beside a member of the first subset of longer conductors such that a space occupied by the shorter conductor is not filled by another conductor or component for a remaining portion of the generally parallel run length of the longer conductor when the shorter conductor reaches the end of its generally parallel run length, providing increased lateral separation.
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6. A method of adjusting an integrated circuit for a reduced conductor capacitance, comprising:
routing a first subset of generally longer conductors of a set of generally parallel and physically proximate conductors;
selectively routing a second subset of generally shorter conductors of the set of generally parallel and physically proximate conductors to reduce conductor to conductor capacitance,
such that in a plan view each member of the second subset of generally shorter conductors is routed beside a member of the first subset of longer conductors such that a space occupied by the shorter conductor is not filled by another conductor or component when the shorter conductor reaches the end of its generally parallel run length, providing increased lateral separation; and
coupling the set of conductors to receive a set of control signals.
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12. A method of adjusting an integrated circuit for a reduced interconnect line RC time constant, comprising:
routing a first subset of generally longer interconnect lines of a set of generally parallel and physically proximate interconnect lines;
selectively routing a second subset of generally shorter interconnect lines of the set of generally parallel and physically proximate interconnect lines to reduce interconnect line to interconnect line capacitance,
wherein each member of the second subset of generally shorter interconnect lines is routed beside a member of the first subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component for a remaining portion of the generally parallel run length of the longer conductor when the shorter interconnect line reaches the end of its generally parallel run length; and
selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance.
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17. A method of adjusting an integrated circuit for a reduced interconnect line RC time constant, comprising:
routing a first subset of generally longer interconnect lines of a set of generally parallel and physically proximate interconnect lines;
selectively routing a second subset of generally shorter interconnect lines of the set of generally parallel and physically proximate interconnect lines to reduce interconnect line to interconnect line capacitance,
wherein each member of the second subset of generally shorter interconnect lines is routed beside a member of the first subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length;
selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance; and
coupling the set of interconnect lines to receive a set of control signals.
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22. A method of adjusting an integrated circuit for a reduced interconnect line RC time constant, comprising:
routing a first subset of generally longer interconnect lines of a set of generally parallel and physically proximate interconnect lines;
selectively routing a second subset of generally shorter interconnect lines of the set of generally parallel and physically proximate interconnect lines to reduce interconnect line to interconnect line capacitance,
wherein each member of the second subset of generally shorter interconnect lines is routed beside a member of the first subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length;
selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance; and
wherein selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance comprises, adjusting only the cross sectional area of members of the first subset of generally longer interconnect lines.
23. A method of adjusting an integrated circuit for a reduced interconnect line RC time constant, comprising:
selectively routing a second subset of generally shorter interconnect lines of the set of generally parallel and physically proximate interconnect lines to reduce interconnect line to interconnect line capacitance,
wherein each member of the second subset of generally shorter interconnect lines is routed beside a member of the first subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length;
selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance; and
wherein selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance comprises, adjusting only the cross sectional area of members of the first subset of generally longer interconnect lines, such that the cross sectional area of each member of the subset of generally longer interconnect lines is increased after the shorter interconnect lines routed beside them reach the end of their generally parallel run length.
24. A method of adjusting an integrated circuit for a reduced conductor capacitance, comprising:
forming a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, with each conductor having a first capacitance, C
_{B}, due to a bulk substrate capacitance and a second capacitance, C_{L}, due to conductor to conductor capacitance effects; routing a subset of generally longer than average conductors of the set of conductors; and
reducing the second capacitance, C
_{L}, due to conductor to conductor capacitance effects by routing a subset of generally shorter than average conductors of the set of conductors, such that in a plan view each member of the subset of the generally shorter conductors is routed beside a member of the subset of the generally longer conductors such that a space occupied by the generally shorter conductor is left open when the generally shorter conductor reaches the end of its generally parallel run length, providing a larger lateral separation. 25. The method of
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28. A method of adjusting an integrated circuit for a reduced interconnect line RC time constant, comprising:
forming a set of interconnect lines of differing lengths implemented in close physical proximity and running generally in parallel to each other with each interconnect line having a line resistance, R
_{L}, a first capacitance, C_{B}, due to a bulk substrate capacitance, and a second capacitance, C_{L}, due to interconnect line to interconnect line capacitance effects, such that the interconnect line has a RC time constant of R_{L }(C_{B}+C_{L}); routing a subset of generally longer than average interconnect lines of the set of interconnect lines; and reducing the second capacitance, C
_{L}, due to interconnect line to interconnect line capacitance effects by routing a subset of generally shorter than average interconnect lines of the set of interconnect lines, wherein an average RC time constant of the set of interconnect lines is reduced by routing each member of the subset of shorter interconnect lines beside a member of the subset of longer interconnect lines such that a space occupied by the shorter interconnect line is left unfilled when the shorter interconnect line reaches the end of its generally parallel run length. 29. The method of
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_{L }by varying the cross sectional area of members of the set of interconnect lines.33. The method of
_{L }by varying the cross sectional area of members of the subset generally longer than average interconnect lines.34. The method of
_{L }with the increase in C_{L }for increasing the interconnect line cross sectional area.35. The method of
_{L }with the increase in C_{L }and C_{B }for increasing the interconnect line cross sectional area so that the RC time constant of R_{L }(C_{B}+C_{L}) proximates a minimum.36. The method of
_{L }by varying the cross sectional area of members of the subset generally longer than average interconnect lines, such that the cross sectional area of each member of the subset of generally longer interconnect lines is increased after the shorter interconnect lines routed beside them reach the end of their generally parallel run length.37. A method of adjusting the interconnect line capacitance of a memory device comprising:
forming an address interface coupled to a first I/O buffer circuit;
forming a first interconnect circuit coupled to the first I/O buffer circuit;
forming a data interface coupled to a second I/O buffer circuit;
forming a second interconnect circuit coupled to the second I/O buffer circuit;
forming a control interface coupled to a third I/O buffer circuit;
forming a third interconnect circuit coupled to the third I/O buffer circuit; and
routing each of the first, second and third interconnect circuits such that, for each of the first, second and third interconnect circuits, a set of interconnect lines of differing lengths implemented in close physical proximity and running generally in parallel to each other in a plan view, wherein a subset of generally longer than average interconnect lines, and a subset of generally shorter than average interconnect lines, are routed such that each member of the subset of the generally shorter interconnect lines is routed beside a member of the subset of the generally longer interconnect lines such that a space occupied by the generally shorter interconnect line is not filled by another interconnect line or component when the generally shorter interconnect line reaches the end of its generally parallel run length.
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Description This is a divisional application of U.S. patent application Ser. No. 09/905,055, filed Jul. 12, 2001, now U.S. Pat. No. 6,571,380, issued May 27, 2003, titled “INTEGRATED CIRCUIT WITH LAYOUT MATCHED HIGH SPEED LINES” and commonly assigned, the entire contents of which are incorporated herein by reference. The invention relates to integrated circuits, and more particularly, to circuits with high speed interconnect lines. As the operating frequencies on modem integrated circuits have become increasingly higher, signal propagation timing constraints have become increasingly stricter. This is particularly the case for synchronous integrated circuits, where signals are expected at interfaces and inputs at specific times. A major source of signal propagation delay in modern integrated circuits is delay from resistive and capacitive loading. This potential for signal propagation delay due to RC loading has become even more of a predominant issue with the decreasing device sizes, spacing, and operating voltages of modern components. The primary object of most common types of modern integrated circuit construction techniques is to increase operating speed and frequencies of integrated circuit device components by reducing device component sizes and operating voltages. While accomplishing this goal, however, the reduced device sizes decrease interconnect line cross section area, which has the effect of-increasing the individual line resistances. The same reduction in feature size reduces the line-to-line spacing, increasing the interconnect line capacitance due to line-to-line capacitance effects. Both these effects adversely influence the RC loading of the interconnect lines in integrated circuits. This increased RC loading interferes with signal propagation speed and increase the likelihood of timing faults when the circuit is in operation. Line resistance and line-to-line capacitance is particularly an issue in high speed lines that have longer run lengths or drive external buffers. Relatively long run lines typically have high RC time constants because of increased individual line resistance and capacitance, due to line length, line-to-line spacing, and bulk silicon effects. The increased line capacitance and resistance of such long run lines typically require the use of increased line voltage to counteract the increased RC time constant they engender and increase timing constraints. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system to reduce line-to-line capacitive effects and increased RC time constants in integrated circuits with reduced feature size. Additionally, there is a need for the ability to reduce interconnect line capacitance, and to have matched delays and RC time constants across grouped long run lines. The above-mentioned problems with integrated circuit interconnect resistive and capacitive loading, and other problems, are addressed by the present invention and will be understood by reading and studying the following specification. In one embodiment, an integrated circuit comprises a set of interconnect lines of differing lengths implemented in close physical proximity, and running generally in parallel to each other, wherein the set of interconnect lines comprise, a subset of interconnect lines with a longer parallel run length than average for the set, and a subset of interconnect lines with a shorter parallel run length than average for the set, wherein each member of the subset of shorter run length interconnect lines is routed in between two members of the subset of longer run length interconnect lines, such that a space in between two members of the subset of longer run length interconnect lines left open when the short run line reaches the end of its parallel run length. In another embodiment, an integrated circuit comprises an active circuit, a set of distributed circuits, and a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, wherein each member of the set of distributed circuits is coupled to at least one member of the set of distributed circuits, and wherein the set of conductors comprises, a subset of generally longer than average conductors, and a subset of generally shorter than average conductors, such that in a plan view each member of the subset of shorter conductors is routed beside a member of the subset of longer conductors wherein a space occupied by the shorter conductor is not filled by another conductor or component when the shorter conductor reaches the end of its generally parallel run length, providing increased lateral separation. In a further embodiment, a memory device comprises an address interface coupled to a first I/O buffer circuit, a first interconnect circuit coupled to the first I/O buffer circuit and to an address register, a data interface coupled to a second I/O buffer circuit, a second interconnect circuit coupled to the second I/O buffer circuit, a control interface coupled to a third I/O buffer circuit, and a third interconnect circuit coupled to the third I/O buffer circuit, wherein the first, second and third interconnect circuits each comprise a set of interconnect lines of differing lengths, implemented in close physical proximity, and running generally in parallel to each other, a subset of generally longer than average interconnect lines, and a subset of generally shorter than average interconnect lines, such that, in a plan view, each member of the subset of shorter interconnect lines is routed beside a member of the subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length, providing increased lateral separation. In yet another embodiment, an integrated circuit comprises an active circuit, a set of distributed circuits, and a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, and each conductor having a line resistance, R A method of adjusting an integrated circuit for a reduced conductor capacitance comprises routing a first subset of generally longer conductors of a set of generally parallel and physically proximate conductors, and selectively routing a second subset of generally shorter conductors of the set of generally parallel and physically proximate conductors to reduce conductor to conductor capacitance, such that in a plan view each member of the second subset of generally shorter conductors is routed beside a member of the first subset of longer conductors such that a space occupied by the shorter conductor is not filled by another conductor or component when the shorter conductor reaches the end of its generally parallel run length, providing increased lateral separation. Another method of adjusting an integrated circuit for a reduced interconnect line RC time constant comprises routing a first subset of generally longer interconnect lines of a set of generally parallel and physically proximate interconnect lines, selectively routing a second subset of generally shorter interconnect lines of the set of generally parallel and physically proximate interconnect lines to reduce interconnect line to interconnect line capacitance, wherein each member of the second subset of generally shorter interconnect lines is routed beside a member of the first subset of longer interconnect lines such that a space occupied by the shorter interconnect line is not filled by another interconnect line or component when the shorter interconnect line reaches the end of its generally parallel run length, and selectively adjusting the cross sectional area of each member of the set of generally parallel and physically proximate interconnect lines to reduce an inherent interconnect line resistance. A further method of adjusting an integrated circuit for a reduced conductor capacitance comprises forming a set of conductors of differing lengths implemented in close physical proximity and running generally in parallel to each other, with each conductor having a first capacitance, C An additional method of adjusting an integrated circuit for a reduced interconnect line RC time constant comprises forming a set of interconnect lines of differing lengths implemented in close physical proximity and running generally in parallel to each other with each interconnect line having a line resistance, R In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims. The resistance of a given interconnect line in an integrated circuit is a product of its cross sectional area, resistivity of the material comprising the interconnect line, and the length of the interconnect. The longer an interconnect line, the higher its inherent resistance for a given cross sectional area and material. The larger the cross sectional area, the lower the resistance of the interconnect line for a given length and material. However, increasing the cross sectional area of an interconnect line also has the effect of increasing its inherent capacitance with other components, which can be an undesired result. In general, there are two sources of capacitance loading for an interconnect line in an integrated circuit, capacitance to the bulk silicon of the integrated circuit, and capacitance to other interconnect lines physically close by. The capacitance of an interconnect line to the bulk silicon of an integrated circuit can be described as a function of permittivity, line width, line length, and the thickness of the oxide insulator layer the interconnect line is placed on. Line-to-line capacitance is an effect that increases with decreasing feature size and line spacing. Line-to-line capacitance is generally a product of line height, line-to-line spacing, permittivity, and the length of the space that the interconnect line is run in close proximity to another line. Line-to-line capacitance is cumulative and has with modern reduced feature size integrated circuits increased to become a non-trivial effect and to be considered with the capacitive effect of the bulk silicon on an interconnect line. The RC time constant of a given interconnect line that effects the interconnect line's signal delay properties is a product of the inherent line resistance, R, and any inherent line capacitance, C, that is due to both the bulk silicon effects and the line-to-line capacitance. These undesired input RC time constants add to the propagation delay of signals through the circuit at a given signal voltage level, and can cause problems with setup and hold timing requirements for the signal. The interconnects ( Unfortunately, increasing the area of an interconnect will also have the effect of increasing the line capacitance to both the bulk silicon substrate and the line-to-line capacitance. Thus, increasing the cross sectional area of an interconnect line to reduce the line resistance and therefore the RC time constant of the line will meet a point of diminishing returns, where the increased line capacitance will cancel out any reduction in the line resistance in its effect on the interconnect line RC time constant. However, if a balance in this resistance and capacitance is sought, the effect can be used to reduce the overall RC time constant to a minimum for a given interconnect line. The ability to change the RC time constant of a given interconnect line by adjusting its cross sectional area can also be combined with another embodiment of the present invention as shown in the circuits of In In In implementation of the circuits of The non-volatile memory device of As shown in A high speed interconnect line group for an integrated circuit is described, having an improved line-to-line capacitance and overall RC time constant. The high speed interconnect line group incorporates a series of interconnect lines wherein shorter run lines are routed between longer run interconnect lines. As the short run interconnect lines reach their destination and fall away they open up the line spacing on the remaining interconnect lines and improve the line-to-line capacitance that dominates capacitive effects in modern reduced feature size integrated circuits. Additionally, the cross sectional area of the interconnect lines can be increased to lower the line resistance of longer run lines and compensate for the line capacitance without critically increasing the line-to-line capacitance of these lines and adversely affecting the overall line RC time constant. The described invention allows line capacitances, resistances, and RC time constants to be optimized for a single line of a group or for the entire group of interconnect lines, providing a low average value or a uniform value across all lines for uniform signal propagation delay across all of the optimized group. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement, which is calculated to achieve the same purpose, may be substituted for the specific embodiment shown. This application is intended to cover any adaptations or variations of the present invention. Therefore, it is manifestly intended that this invention be limited only by the claims and the equivalents thereof. Patent Citations
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