|Publication number||US7030596 B1|
|Application number||US 10/728,021|
|Publication date||Apr 18, 2006|
|Filing date||Dec 3, 2003|
|Priority date||Dec 3, 2003|
|Publication number||10728021, 728021, US 7030596 B1, US 7030596B1, US-B1-7030596, US7030596 B1, US7030596B1|
|Inventors||David C. Salerno, Mark G. Jordan|
|Original Assignee||Linear Technology Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (93), Non-Patent Citations (99), Referenced by (148), Classifications (6), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to power converter circuits. More particularly, the present invention relates to methods and circuits for power converters that automatically transition into and out of a low power consumption mode based on load current.
Voltage regulators, also known as power converters, provide a regulated output voltage from a voltage source that may be poorly-specified or fluctuating, or that may be at an inappropriate amplitude for the load. Such regulators may employ a switching circuit that includes one or more switching elements coupled in series or in parallel with the load. The switching elements may be, for example, power metal-oxide semiconductor field-effect transistor (MOSFET) switches.
Control circuitry regulates the output voltage and the current supplied to the load by cycling the switch circuit between ON and OFF states. The duty cycle of the switch circuit controls the flow of power to the load, and can be varied by a variety of methods. For example, the duty cycle can be varied by (1) fixing the pulse stream frequency and varying the ON or OFF time of each pulse, (2) fixing the ON or OFF time of each pulse and varying the pulse stream frequency, or (3) a combination thereof.
To vary the ON or OFF time of each pulse or the pulse stream frequency, the control circuitry may monitor the regulator's output voltage and generate a feedback signal Ve that is proportional to the difference between the regulator's output voltage and the regulated voltage. Ve may be used to provide either “voltage-mode” or “current-mode” regulation. In voltage-mode regulation, Ve and a periodic sawtooth waveform Vs may be provided as inputs to a comparator, the output of which controls the duty cycle of the switch circuit. In current-mode regulation, a voltage Vi may be generated that is proportional to the current in the output inductor, and Vi and Ve may be provided as inputs to a comparator, the output of which controls the duty cycle of the switch circuit.
Synchronous switching regulators include at least two switching elements that typically are driven by non-overlapping drive signals to supply current at a regulated voltage to a load. Synchronous switching regulators that use power MOSFET switches frequently are used in portable battery-powered electronic products and thermally-sensitive products. These regulators convert the typically fluctuating input voltage to a regulated output voltage. Such regulators provide high operating efficiency and thus long battery life with little heat generation.
One problem with switching regulators is that the efficiency of the regulator decreases as the load current is reduced to low levels due to switching and quiescent losses. This is particularly problematic in battery-powered applications, which may spend much of their operating time in a low power draw mode (i.e., when load current demand is low).
To maintain high efficiency at light load, thereby increasing battery life, switching power converters may transition from a NORMAL operating mode, e.g., a fixed frequency pulse-width modulation (PWM) mode of operation, to a low power consumption mode in which switching and quiescent losses are significantly reduced. One example of a low power consumption mode is a BURST mode operation, which sometimes also is referred to as a type of pulse frequency modulation with intermittent bursts of pulses. In BURST mode, the voltage regulator operates sufficiently long to bring the output voltage into regulation, after which the converter transitions into SLEEP mode. In SLEEP mode, all switching stops and all the active switching elements are maintained OFF for a period of time that varies as a function of load current, the quiescent current of the converter is reduced, and the load is supported by energy stored in an output capacitor. During SLEEP, additional components of the power converter can be but need not be turned OFF. When the output voltage decreases below a threshold level, e.g., 1% below the regulated value, the converter “awakens” from SLEEP mode and resumes switching until the output voltage again is within regulation limits, at which point the converter resumes SLEEP mode. Alternatively, some switching power converters may transition directly from NORMAL operation to SLEEP mode, maintaining all active switching elements OFF and reducing quiescent current to reduce power consumption. In this manner, high efficiency can be maintained over a wide range of load current since the time spent in SLEEP mode increases as the load current demand is reduced.
When the power converter is subjected to heavier loads, however, NORMAL operating mode, in which the converter switch continuously alternates between an ON state and an OFF state to maintain the output voltage at the regulated level, may be more beneficial than BURST mode operation. Accordingly, the converter may be configured for transition between NORMAL operating mode and BURST mode as the load varies.
Some applications may be able to provide a mode control signal, giving the converter “advance warning” of an impending increase or decrease in load. There are other applications in which a user cannot provide this control, and the converter must be able to switch between modes automatically, based on load, while maintaining regulation.
Preferably, a burst mode control circuit would have means of sensing average load current and switch between modes automatically based on a user-programmed current threshold. It would also respond quickly to sudden load changes, and easily be controlled by the host for manual operation, while requiring a minimum number of components.
There are a number of existing methods for implementing automatic mode control (see, e.g., U.S. Pat. No. 5,481,178 to Wilcox et al.). One method used by current mode converters is to sense load current by monitoring output voltage from a feedback error amplifier. When this voltage drops below a predetermined level, indicating a certain peak inductor current, the converter goes into SLEEP mode. The converter comes out of the SLEEP mode when the output voltage has dropped below a pre-defined threshold. Thereafter, the converter wakes up and resumes switching. The major problem with this method is that the error voltage is an indication of peak inductor current, not average load current. This may cause the mode transition point to vary as much as 10:1, as a function of the VIN/VOUT ratio, inductance, and switching frequency. It also is restricted to converters using current mode control.
Another method is described in the datasheet for Unitrode's UC1874 buck regulator. The UC1874 employs fixed frequency average current mode control and improves light load efficiency with a programmable standby mode during which the MOSFET drivers and the oscillator are disabled. The UC1874 senses average output current by monitoring voltage from a feedback error amplifier. When that voltage, which is indicative of the average output current, drops below a programmable voltage threshold, the converter transitions into the standby mode. One problem with the UC1874 is that the output signal from the error amplifier is accurate only during steady state conditions. During transient conditions, the output voltage from the error amplifier may not be an accurate indication of the average output current due to potential lags in responsiveness that result from employment of average current-mode control.
Another mode control method and circuit is based on the sensing of discontinuous inductor current as an indication of light load. This circuit is not easily programmable, and is subject to large mode threshold variation with VIN, VOUT, inductance, and switching frequency. Furthermore, such a circuit also may require a larger, more expensive inductor having a greater inductance to achieve the desired load transition threshold.
In view of the foregoing, it would be desirable to provide methods and circuits for controlling a voltage regulator having a smooth and repeatable transition between operating modes.
It also would be desirable to provide methods and circuits for automatic transition of a voltage regulator into and out of a low power consumption mode at a mode transition point or threshold that can be set independently of input voltage, output voltage, inductance, and switching frequency.
It further would be desirable to provide methods and circuits for automatic transition of a voltage regulator into and out of a low power consumption mode in which the mode transition point or threshold is easily programmable.
It even further would be desirable to provide methods and circuits for automatic transition of a voltage regulator into and out of a low power consumption mode that may be used in conjunction with voltage mode or current mode control to vary the duty cycle of a switch.
In addition, it would be desirable to provide methods and circuits for transition between operating modes by manual override.
In view of the foregoing, it is an object of the present invention to provide methods and circuits for controlling a voltage regulator having a smooth and repeatable transition between operating modes.
It also is an object of the present invention to provide methods and circuits for automatic transition of a voltage regulator into and out of a low power consumption mode at a mode transition point or threshold that can be set independently of input voltage, output voltage, inductance, and switching frequency.
It further is an object of the present invention to provide methods and circuits for automatic transition of a voltage regulator into and out of a low power consumption mode in which the mode transition point or threshold is easily programmable.
It even further is an object of the present invention to provide methods and circuits for automatic transition of a voltage regulator into and out of a low power consumption mode that may be used in conjunction with voltage mode or current mode control to vary the duty cycle of a switch.
In addition, it is an object of the present invention to provide methods and circuits for transition between operating modes by manual override.
These and other objects of the present invention are accomplished by providing methods and circuits that automatically transition a power converter into and out of a low power consumption mode based on load current demand by monitoring output current and averaging the monitored output current to develop a signal indicative of average output current. In one embodiment, a synchronous switching regulator is provided having a circuit that monitors and averages the regulator's output current, creating a voltage signal indicative of the average output current. When the indicative voltage is greater than a user-programmable mode transition threshold, indicating a high load current demand, the voltage regulator commands a NORMAL operating mode (e.g., fixed frequency mode) in which the output voltage is maintained at the regulated level by continuously adjusting inductor current IL. When the indicative voltage is less than the user-programmable mode transition threshold, indicating a low load current demand, the voltage regulator commands BURST mode. A user may easily program the average output current, and thereby the load current demand, at which mode transition occurs by selection of a resistor. Advantageously, the methods and circuits of the present invention permits the duty cycle of the voltage regulator to be controlled using either current mode or voltage mode control.
Embodiments also may be configured to permit a user to override the automatic mode transition and manually or digitally control transition into and out of BURST mode.
Further features of the present invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description, in which:
To increase the efficiency of a power converter, the present invention comprises methods and circuits that may be integrated into the power converter circuit to automatically transition the power converter into BURST mode when load current demand is low and out of BURST mode when the load current demand is high. The present invention, an illustrative embodiment of which is shown in
In particular, power converter control circuit 10 regulates the output voltage VOUT by controlling the converter output current such that the average output current supplied to output capacitor COUT is sufficient to support the current drawn from the output capacitor by the load at an output voltage VOUT within a desired range of a nominal regulated value. When load current demand is low, average output current IOUT,AVG also is low. Likewise, when load current demand is high, so too is the average output current. Accordingly, BURST mode control circuit 12 of the present invention senses low load current demand by sensing low average output current.
In the embodiment of the present invention illustrated in
In particular, VBURST is fed into the inverting input of hysteretic comparator 20 and compared to a reference voltage that is fed into the non-inverting input of hysteretic comparator 20. When VBURST falls below a first user-programmable mode transition threshold, indicating a light load current demand, hysteretic comparator 20 outputs a signal HIGH that commands converter control circuit 10 to operate in BURST mode. Hysteresis of comparator 20 prevents oscillation between modes due to ripple voltage on capacitor 18. The capacitance of capacitor 18 preferably is selected to reduce ripple to less than the hysteresis of comparator 20. When VBURST increases beyond a second, higher user-programmable mode transition threshold, indicating a heavy load current demand, hysteretic comparator 20 outputs a signal LOW that is fed back to power converter control circuit 10 to transition out of BURST mode and command NORMAL operation of the converter. Illustrative NORMAL operational modes include fixed frequency or variable frequency operation with continuous or discontinuous current, e.g., as described with respect to the voltage converter of FIG. 1 of U.S. Pat. No. 5,481,178 to Wilcox et al. As used herein, the term “user-programmable” refers to the capability of varying parameters of the power converter with external components.
In accordance with one aspect of the present invention, a user may program power converter control circuit 10 to transition into and out of BURST mode at a desired average output current by a calculated or empirical selection of an appropriate value for the resistance of programming resistor 16. In particular, programming resistor 16 (RBURST) may be selected based on the following equation:
R BURST =K*V REF /I BURST
where K is the mirror ratio IOUT/IM, VREF is the reference voltage at the non-inverting input of hysteretic comparator 20, and IBURST approximately is the average output current and, and thus the load current, at which the power converter transitions into and out of BURST mode, neglecting the small voltage ripple across capacitor 18 and the hysteresis of comparator 20.
For example, if K is 2000:1, VREF is 1.0V, and RBURST is 10 kΩ, power converter control circuit 10 transitions into and out of BURST mode at an average output current of approximately 200 mA, neglecting the small voltage ripple across capacitor 18 and the hysteresis of comparator 20. Accordingly, for load current demands greater than approximately 200 mA, BURST mode control circuit 12 would command converter control circuit 10 to operate in NORMAL mode. However, when the load current demand decreases to less than approximately 200 mA, BURST mode control circuit 12 would automatically transition converter control circuit 10 to BURST mode operation. Of course, one of ordinary skill in the art would appreciate that the current ratio, reference voltage and resistance values may be modified based on design choice.
Advantageously, the design of the present invention permits a user to easily program the mode transition point independently of input voltage VIN, output voltage VOUT, inductance, or switching frequency. Furthermore, the high-efficiency circuit of the present invention may be integrated with any converter topology (e.g., buck, boost, inverter, or combinations thereof) and used with either current or voltage mode control.
Programming resistor 16 and filtering capacitor 18 may be replaced by other known user-programmable filter circuits that average the pulsed nature of mirrored current IM to generate an output signal that may be employed by hysteretic BURST comparator 20 to automatically transition power converter control circuit 10 into and out of BURST mode. The mode transition control circuit of
In accordance with another aspect of the present invention, BURST mode control circuit 12 may be configured to permit manual transition of the voltage regulator into and out of BURST mode. More specifically, a user may force circuit 12 to operate in BURST mode by sinking the BURST PIN to ground or to operate in NORMAL mode by pulling the BURST PIN up to a voltage greater than VREF (but preferably no greater than VOUT). To facilitate manual transition, user-actuable switch 22 optionally may be provided, as illustrated in
When the power converter of
MOSFETs 30 and 32 respectively are driven by drivers 40 and 42, which in turn are controlled by one-shot circuit 44. One-shot circuit 44 provides an OFF pulse of constant duration during which time MOSFET 30 is held OFF and MOSFET 32 is held ON, causing inductor current IL to decrease. At the termination of the OFF pulse, one-shot circuit 44 provides an ON pulse during which time MOSFET 30 is held ON and MOSFET 32 is held OFF, causing the inductor current to increase. Accordingly, one-shot circuit 44 alternately turns active switch elements 30 and 320N and OFF to provide an alternating supply of current to inductor 36 and output capacitor 38.
The duty cycle of one-shot circuit 44 is controlled by current comparator 46, which compares a feedback voltage VFB that is proportional to output voltage VOUT with a voltage representative of inductor current IL. Resistor divider 48A/48B (R1/R2 respectively) divides output voltage VOUT to generate feedback voltage VFB. Inductor current IL is monitored by differential amplifier 50 disposed across resistor 52, which in turn is disposed in series with inductor 36.
In NORMAL mode, the voltage regulator of
Accordingly, the power converter of
In accordance with the present invention, when hysteretic BURST comparator 20 determines that the average output current, and thus the load current demand, has decreased below the current level that corresponds to the mode transition threshold set by programming resistor 16 and offset by the hysteresis of BURST comparator 20, the BURST comparator outputs a logic HIGH, and the power converter transitions into BURST mode. While in BURST mode, feedback error amplifier 54 operates as a SLEEP comparator to transition the voltage converter into and out of SLEEP mode responsive to output voltage VOUT. When SLEEP comparator 54 determines that output voltage VOUT is greater than a SLEEP threshold, e.g., 1% greater than the desired regulated voltage level, comparator 54 outputs a logic LOW.
That signal is inverted by inverter 55 and combined with the logic HIGH signal output by BURST comparator 20 to cause AND gate 56 to command transition of the voltage regulator into SLEEP mode, during which the switching transistors of the power converter are kept OFF. To further reduce power consumption during SLEEP and/or BURST mode, and thereby increase efficiency, the regulator circuit can be but need not be configured to turn OFF other circuit components which are not needed while the regulator is in SLEEP and/or BURST mode. During SLEEP mode, energy stored in output capacitor 38 maintains output voltage VOUT substantially at the regulated voltage and supports load current demand.
When SLEEP comparator 54 determines that output voltage VOUT is less than a WAKE threshold, e.g., 1% less than the desired regulated voltage level, comparator 54 trips and outputs a logic HIGH signal that wakes up the converter to start a new BURST cycle and recharge output capacitor 38 in BURST mode until SLEEP comparator 54 again outputs logic LOW. To recharge output capacitor 38, the power converter may be configured to alternately turning switch transistors 30 and 320N and OFF so as to vary the duty cycle. Alternatively, the power converter may be configured to maintain P-MOSFET 30 ON and maintain N-MOSFET 32 OFF
When SLEEP comparator 54 again determines that output voltage VOUT is greater than the SLEEP threshold, SLEEP comparator 54 outputs a logic LOW that puts the circuit back in SLEEP mode. The rate at which the regulator “wakes up” to recharge output capacitor COUT automatically adapts to the load current demand. The above-described procedure of waking up the converter and returning the power converter to sleep after recharging the capacitor is repeated as long as the load current demand is below the current threshold that corresponds to the user-programmable mode transition threshold.
When hysteretic BURST comparator 20 determines that the voltage at the BURST pin (VBURST), which is indicative of the average output current and the load current demand, is greater than the user-programmable mode transition threshold, BURST comparator 20 outputs a logic LOW, which transitions the voltage regulator out of BURST mode into NORMAL operation. Since the BURST mode signal feeding into AND gate 56 now is at a logic LOW, AND gate 56 may no longer command the converter to enter SLEEP mode regardless of the output of SLEEP comparator 54, which now reverts to function as an error amplifier.
Accordingly, the power converter of
Advantageously, the mode transition point of the voltage regulator of the present invention is not subject to considerable variation, and therefore is repeatable. This is due to the fact that the automatic burst mode control circuit of the present invention is responsive to the average output current directly and not the output voltage, which (in a current mode control circuit) could cause the mode transition point to vary as much as 10:1 as a function of input and output voltage, inductance, switching frequency and noise. Furthermore, since the burst mode control circuit of the present invention directly monitors output current and averages the monitored output current to generate a signal indicative of the average thereof, the present burst mode control circuit responds quickly and accurately to changes in load current demand even during transient conditions.
It will be apparent to one of ordinary skill in the relevant art that one-shot constant OFF-time circuit 44 may be replaced with a pulse-width modulator circuit either of the type well-known in the art or otherwise, the pulse-width modulator circuit providing a pulse-width modulated signal in response to a control signal. Alternatively, one-shot constant OFF-time circuit 44 also may be replaced with a one-shot constant ON-time circuit or a variable OFF-time circuit that provides a variable OFF-time control signal dependent on, e.g., output voltage VOUT and input voltage VIN. U.S. Pat. Ser. No. 5,481,178 to Wilcox et al. describes one example of such a variable OFF-time circuit that may be used to reduce the generation and emission of audible noise from inductor 36 at low input voltages. Alternatively, the voltage regulator of
Similarly, if the load current demand exceeds the output current supplied by the power converter during the forced BURST mode operation described above with respect to
In alternative embodiments, AND gate 73 may accept additional inputs and thereby require additional conditions to be satisfied before switch 70 is activated to couple voltage source 60 to filtering capacitor 18. For example, as shown in
To provide frequency compensation when the converter transitions from BURST mode to NORMAL operation, the converter also may incorporate compensation network 62 having, e.g., compensation resistor 64 in series with compensation capacitor 66. In BURST mode, SLEEP comparator 54 is disconnected from compensation network 62. This improves the converter's response when returning to NORMAL operation by preventing compensation capacitor 66 from discharging during BURST mode. In applications in which the converter may operate in BURST mode for extended periods, compensation network 62 may be clamped by clamp 68 in BURST mode, again preventing compensation capacitor 66 from discharging.
In operation, when the load current demand is high, hysteretic BURST comparator 20 outputs a logic LOW that commands the converter circuit to operate in a NORMAL mode and switch 70 to disconnect voltage source 60 from charging filtering capacitor 18. The converter then regulates the output voltage and current so that inductor current IL is regulated at a level required to support the load. When load current demand decreases, however, the duty cycle of switch 34 also decreases responsive thereto. The resulting reduction in the average output current delivered to output capacitor 38 to support the load is reflected in voltage VBURST at the BURST PIN. Once VBURST has decreased to a voltage level below the first user-programmable mode transition threshold, hysteretic BURST comparator 20 outputs a logic HIGH, which is fed to AND gate 72 along with the inverted output of under-voltage comparator 58. Thereafter, the converter circuit is commanded to operate in BURST mode.
The logic HIGH output of BURST comparator 20 also is fed to AND gate 73 along with the logic LOW output of under-voltage comparator 58 to maintain disablement of switch 70, and thereby maintain an open connection between voltage source 60 and filtering capacitor 18. As discussed above, under-voltage comparator 58 may revert to a logic LOW when output voltage VOUT is recharged back to the regulated level in NORMAL operating mode.
In BURST mode, AND gate 72 outputs a logic HIGH signal that opens switch 74 to disconnect compensation network 62 from the remainder of the regulator circuit, and closes switch 76 to connect clamp 68 to compensation network 62 and thereby prevent compensation capacitor 66 from discharging. The logic HIGH signal from AND gate 72 also is fed to AND gate 56, which now may command the regulator circuit to transition into SLEEP mode responsive to output signal 54A of SLEEP comparator 54. As described hereinabove, when the converter circuit is in BURST mode and output voltage VOUT is greater than the SLEEP threshold, e.g., 1% above the desired output voltage, SLEEP comparator 54 outputs a logic LOW that commands the converter circuit to operate in SLEEP mode. However, when the converter circuit is in BURST mode and output voltage VOUT decreases to be less than a WAKE threshold, e.g., 1% less than the desired output voltage, SLEEP comparator 54 outputs a logic HIGH that wakes up the converter to recharge output capacitor 38 until SLEEP comparator 54 again outputs a logic LOW.
When load current demand suddenly increases, output capacitor 38 may be unable to sustain output voltage VOUT approximately at the regulated level. If output capacitor 38 suddenly and quickly is discharged, output voltage VOUT may decrease at a rate faster than the rate at which filtering capacitor 18 is recharged by mirror current IM. When output voltage VOUT decreases to a level less than the under-voltage mode transition threshold, e.g., 3–4% below that of the desired output voltage, under-voltage comparator 58 trips and outputs a logic HIGH. This signal then is fed to AND gate 72, which immediately transitions the converter out of BURST mode. The logic HIGH output of the under-voltage comparator also is fed to AND gate 73, which commands switch 70 to close, connecting voltage source 60 to filtering capacitor 18. Voltage source 60 then quickly charges filtering capacitor to a voltage that is greater than the second user-programmable mode transition threshold. This in turn causes the hysteretic comparator to output a logic LOW that opens switch 70, disconnecting voltage source 60 from filtering capacitor 18. Thereafter, the regulator circuit operates in NORMAL operating mode until VBURST once again drops below the programmed mode transition threshold, indicating that the average output current (and thus the load current demand) is low, at which time the above-described cycle repeats.
In addition to the buck topology described above, the high-efficiency BURST mode control circuit of the present invention also may be integrated with switching regulators of different topologies. For example,
Each phase of switching regulator 80 respectively is associated with one of four power blocks 81, delineated by dashed lines in
Switching regulator 80 is powered by a voltage source, e.g., a battery, coupled to input terminal 88. Each power block 81 is coupled to its respective input pin 90, which in turn is externally coupled to its respective inductor 92, input terminal 88 and common input capacitor 93. To disable any of the phases, the inductor corresponding to that phase may be eliminated. This permits a user to reduce cost and board area in applications that do not require the full power capability of voltage regulator 80, or where peak efficiency may not be as important as cost and size.
When the power converter of
Oscillator 98 may be synchronized with an external clock applied to SYNCIN pin 106, and configured to provide an output synchronization pulse that is 180° out of phase from the frequency provided to divider/generator 100 to facilitate synchronization of two voltage regulators. For example, the output synchronization pulse of a first voltage regulator 80 may be provided to SYNCIN pin 106 of a second voltage regulator 80 to create an 8-phase converter, in which the BURST mode control circuits of the voltage regulators may be disabled for some applications by pulling up on the BURST pin. For example, if a user expects the load current demand to dwell approximately at the current level that corresponds to the user-programmable mode transition threshold for a prolonged period of time, then a user may consider disabling the BURST mode control circuits of the voltage regulators.
The fixed frequency pulses generated by oscillator 98 and 4-phase generator 100 then may be provided to pulse width modulator 108 of each power block 81, the duty cycle of which may be current mode controlled. In one embodiment, a feedback voltage indicative of output voltage VOUT is fed into error amplifier 110, e.g., a transconductance amplifier. Error amplifier 110 compares the feedback voltage to a reference voltage and outputs error signal Ve. Comparator 112 then compares error voltage Ve and optionally a signal indicative of a user-programmable maximum current limit level to a signal indicative of the peak current, which optionally may be slope-compensated. The peak current signal may be obtained from current mirror 114, which is configured to mirror a fraction of the current flowing through N-MOSFET 96 with little or no current loss. The maximum current limit level may be user-programmed by coupling current limit resistor 116 between ground and over-current protection circuit 118, examples of which are well-known to one of ordinary skill in the art. PWM 108 then controls the duty cycle of voltage regulator 80 responsive to the output of comparator 112, turning each pair of P-MOSFET 94 and N-MOSFET 960N and OFF as appropriate to adjust inductor current IL and thereby regulate output voltage VOUT.
Accordingly, the power converter of
In accordance with the present invention, switching regulator 80 also includes a BURST mode control circuit to automatically transition regulator 80 into and out of BURST mode. As discussed hereinabove with respect to
In particular, like the BURST mode control circuit of
As with the converter described with respect to
In an optional embodiment, after the SLEEP comparator commands transition out of SLEEP mode, voltage regulator 80 may be configured to delay the transition by a predetermined finite amount of time, e.g., 5 us, to permit bias currents to charge the components of the voltage regulator that were turned OFF during SLEEP mode up to a known operational state, i.e., become “smart.” After the end of the delay period, MOSFETS 94 and 96 may be enabled for switching.
To recharge output capacitor 84 during BURST mode, voltage regulator 80 is configured to shut down oscillator 98, and alternately turn MOSFETs ON and OFF so that (1) the ON time of P-MOSFET 94 and the OFF time of N-MOSFET 96 are determined by the time it takes inductor current IL to reach a peak current limit that is internally fixed independently of current-limit programming resistor 116; and (2) the OFF time of P-MOSFET 94 and the ON time of N-MOSFET 96 are determined by the time it takes inductor current IL to return to zero. Zero-current detection comparator 140 is used to perceive zero inductor current IL. When SLEEP comparator 110 again determines that output voltage VOUT is greater than the SLEEP threshold, the SLEEP comparator outputs a logic LOW, returning the power converter to SLEEP mode. Alternatively, voltage converter 80 may be configured to recharge output capacitor 84 by fixed frequency pulse width modulation or by maintaining P-MOSFET 940N and N-MOSFET 96 OFF during the entire wake-up period.
When hysteretic BURST comparator 124 determines that the average output current, and thus the load current demand, is greater than the mode transition level programmed by programming resistor 120, BURST comparator 124 transitions voltage regulator 80 out of BURST mode into NORMAL operation. Like the converter circuits of
Accordingly, the power converter of
Also as discussed in greater detail with respect to
To provide faster response to sudden increases in load current demand when the voltage regulator is operating in automatic or forced BURST mode, under-voltage comparator 132 outputs a signal to logic gates 126 that commands an immediate transition from BURST mode to NORMAL operating mode when output voltage VOUT decreases below an under-voltage mode transition threshold, e.g., 3–4% below regulation level. To prevent premature transition back to BURST mode, e.g., due to a slight overshoot, in output voltage VOUT, voltage regulator 80 may include internal pull-up circuit 134 that quickly recharges filtering capacitor 122 above the programmed mode transition threshold in a manner similar to that described with respect to
In addition to transitioning voltage converter 80 into and out of BURST mode responsive to BURST comparator 124, voltage regulator 80 may be configured to transition between modes responsive to additional conditions. For example, as illustrated in
Likewise, to transition voltage regulator 80 into SLEEP mode, the regulator also may be configured to respond to additional conditions. For example, as depicted in
Pursuant to another aspect of the present invention, voltage regulator 80 may be configured to activate only one of the four phases, e.g., Phase A, when the regulator is in BURST mode to increase regulator efficiency.
In an optional embodiment, when power converter 80 is commanded to transition back to NORMAL mode, power blocks 81B–D may be brought out of SLEEP mode after a delay by a predetermined finite amount of time to permit the voltage regulator to become “smart” as discussed hereinabove.
Each power block 81A–D also has a multiplicity of output lines, including I_ZERO output 146 that dispatches the output signal of zero-current detection comparator 140 (see
Examples of modifications that may be made to switching regulator 80 include but are not limited to:
Referring now to
Current mirror 148 also may comprise additional embodiments of current mirrors well-known to those of ordinary skill in the art, e.g., BJT current mirrors, cascode configuration mirrors, Wilson configuration mirrors, modified Wilson configuration mirrors, resistors, etc.
Current mirror 148 also may be employed to monitor current flowing through N-MOSFET 96 of
Referring now to
With the exception of programming resistor 170 and filtering capacitor 172, both of which may be selected by the user and coupled to BURST pin 174 external to IC 160, any remaining components 176 of the automatic BURST mode control circuit described with respect to
If monolithic IC 160 is a constant output voltage regulator, voltage divider 186A/186B may be integrated within IC 160. However, if monolithic IC 160 is a programmable output voltage regulator, voltage divider 186A/186B may be coupled to monolithic IC 160 externally via FB pin 188.
As used herein, the term “monitor” and derivatives thereof refer to the action of detecting or measuring the instantaneous value of a current or voltage signal or a fraction thereof. In contrast, the term “sense” and derivatives thereof broadly refer to the action of obtaining some indication, either directly or indirectly, of a current or voltage signal. Furthermore, the term “an output voltage” does not necessarily mean that the voltage at the output of the power converter is a constant value. Rather, as is understood in the art, the power converter's output voltage may vary to some extent.
Although illustrative embodiments of the present invention are described above, it will be apparent to one skilled in the art that various changes and modifications may be made without departing from the invention. For example, while the above-described figures depict a resistive current shunt and transistor-based current mirror to monitor output current IOUT, additional embodiments of current monitors also may be employed, such as current transformers, Hall effect devices, or optical current sensors.
In addition, while the above-described embodiments depict the use of synchronous switches, each having two active switching elements that are driven out of phase to supply current at an output voltage to a load, one of ordinary skill in the relevant art would appreciate that either of the two MOSFETs may be replaced with a passive switch element, e.g., a switching diode. The present invention also may be integrated with voltage regulators employing other types of switches having, e.g., a pair of N-MOSFETS, a pair of P-MOSFETS, or bipolar junction transistors.
It will be apparent to one of ordinary skill in the art that the switching regulators of the present invention could be taken out of SLEEP mode a predetermined time period after going into SLEEP mode, rather than transitioning out of SLEEP mode after load current demand increases as described hereinabove. All reference voltages defining the thresholds may comprise the same threshold levels or one or more different levels, and may be constant or variable in nature.
Furthermore, while the above-described embodiments incorporate current-mode regulation of the converter's duty cycle, it should be obvious to one of ordinary skill in the art that the BURST mode control circuit of the present invention also may be integrated with power converters having voltage-mode regulation. Furthermore, the BURST mode control circuit of the present invention also may be integrated with current regulators in a manner similar to that described above.
It is intended in the appended claims to cover all such changes and modifications that fall within the true spirit and scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
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|Cooperative Classification||H02M3/158, Y02B70/16, H02M2001/0032|
|Mar 19, 2004||AS||Assignment|
Owner name: LINEAR TECHNOLOGY CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SALERNO, DAVID C.;JORDAN, MARK G.;REEL/FRAME:015126/0021
Effective date: 20031222
|Sep 18, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Sep 25, 2013||FPAY||Fee payment|
Year of fee payment: 8