|Publication number||US7036032 B2|
|Application number||US 10/083,903|
|Publication date||Apr 25, 2006|
|Filing date||Feb 27, 2002|
|Priority date||Jan 4, 2002|
|Also published as||US20030131274|
|Publication number||083903, 10083903, US 7036032 B2, US 7036032B2, US-B2-7036032, US7036032 B2, US7036032B2|
|Inventors||Carl Mizuyabu, Ken Ka Kit Kwong, Milivoje Aleksic|
|Original Assignee||Ati Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (27), Non-Patent Citations (2), Referenced by (54), Classifications (31), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent application claims benefit under 35 U.S.C. 119(e) of the U.S. Provisional application No. 60/345,100 filed on Jan. 4, 2002, entitled: “SYSTEM FOR REDUCED POWER CONSUMPTION.
This application is related to U.S. patent application Ser. No. 10/083,875 entitled “SYSTEM FOR REDUCED POWER CONSUMPTION BY PHASE LOCKED LOOP AND METHOD THEREOF”, filed on Feb. 27, 2002, and U.S. patent application Ser. No. 10/083,917 entitled “SYSTEM FOR REDUCED POWER CONSUMPTION BY MONITORING VIDEO CONTENT AND METHOD THEREOF” filed on Feb. 27, 2002.
The present invention relates generally to reducing system power consumption and more specifically to bypassing system components to reduce power consumption.
Handheld devices, such as personal digital assistants (PDA) and mobile phones, are now being equipped with hardware and software to handle several different computing tasks. Handheld devices are being equipped with communications adapters to allow the handheld devices to access the Internet, other handheld devices, and other information handling systems. Handheld devices are also being used to process multimedia data, such as audio and video data. Many handheld devices are capable of playing video on an integrated screen. Handheld devices are being integrated with more components to handle the increased functionality. However, as more components are integrated with the handheld devices and as processing increases, the handheld devices draw more power.
Power is limited on most handheld devices. Most desktop computers take power from a power supply connected to an alternating current (AC) power outlet and generally don't need to worry about conserving power. Handheld devices generally take their power from standard power cells. Handheld devices are designed to be small and light to make them portable for consumers. The power cells are generally selected to be small and light to not hinder the handheld device. However, the increased processing performed to handle new functionality, such as communications or multimedia playback, takes more power from the handheld devices than general processing tasks the handheld devices were originally used for.
Current methods of reducing power consumption are not adequate. To conserve power, a handheld device may reduce the speed at which its central processing unit (CPU) is run. However, inhibiting the CPU reduces the performance of the handheld device in most or all of the functions of the handheld device. Alternatively, specific functions or hardware components within the handheld device may be completely disabled to conserve power. However, completely disabling functions within the handheld device reduces a stability expected by a user. Power-saving modes can be enabled through software by having a software application decide processing can be reduced. However, such applications are not generally aware of the effect of running in a reduced power mode on other components within the device. The application may not be aware of all the processes running within the device. From the above discussion, it is apparent that an improved method of conserving power within a system would be useful.
Specific embodiments of the present disclosure are shown and described in the drawings presented herein. Various objects, advantages, features and characteristics of the present disclosure, as well as methods, operations and functions of related elements of structure, and the combination of parts and economies of manufacture, will become apparent upon consideration of the following description and claims with reference to the accompanying drawings, all of which form apart of this specification, and wherein:
Referring now to
An oscillator 110 is coupled to clock driver 115 to generate a raw clock signal for specific operations within system 100. Oscillator 110 produces the raw clock signal at a fixed frequency. Higher frequencies operations may be desired than can be generated through oscillator 110. Accordingly, a phase locked loop (PLL) 130 is used to generate a stable, locked clock signal from the raw clock signal generated by oscillator 110. PLL 130 is generally used to generate multiplied clock signals based on the raw clock signal generated by oscillator 110. It should be appreciated that oscillator 110 may include various oscillators. For example, various resistor/capacitor (RC) circuits or crystal oscillators may be used in place of oscillator 110 without departing from the scope of the present disclosure.
Several components of PLL 130 are used to generate a signal locked to the phase of the raw clock signal. The PLL 130 works as a control loop, attempting to correct for erratic changes in phase or frequency between the raw clock signal generated through oscillator 110 and a signal generated internal to the PLL 130. In one embodiment, PLL 130 includes a phase comparator (not shown) to identify a difference in phase or frequency between the raw clock signal and the internal signal generated by PLL 130. The comparator can include components or flops to generate a difference signal between the internal signal and the raw clock signal. The difference signal is provided to a filter (not shown), which generates a voltage signal associated with the difference signal. The voltage signal is provided to a voltage controlled oscillator (VCO, not shown) that generates an oscillating signal associated with the voltage signal. The oscillating signal is used as the internal signal mixed with the input raw clock signal. Accordingly, the oscillating signal may be output from the PLL 130 as a locked clock signal.
In one embodiment, the locked clock signal is coupled to a set of dividers 140 and 145. In a normal operating mode, the set of dividers 140 and 145 generate clock signals based on the locked clock signal from PLL 130. In one embodiment, the first divider 140 provides a first divided clock signal to the first clock bus 150. The second divider 145 provides a second divided clock signal, with a lower frequency than the first divided clock signal, to the second clock bus 155. The clock busses 150 and 155 may then be used to provide clock signals for various processing performed by system 100. It should be appreciated that more or less clock busses can be used without departing from the scope of the present disclosure.
In one embodiment, a power module 300 initiates several power modes within system 100. The power module 300 first identifies a processing status of system 300. The status provides an indication of a level of activity, process or power consumption expected by system 100. For example, power module 300 may monitor a number of instructions being stored in random access memory (RAM) 160. Instructions to be processed are stored in an instruction buffer 162 of RAM 160. RAM 160 can include various forms of memory, such as static dynamic random access memory (SDRAM) or dynamic random access memory (DRAM), without departing from the scope of the present disclosure.
Instruction buffer 162 includes a set of memory addresses of RAM 160 in a linked configuration. Instruction buffer 162 includes a write buffer 164 to identify a memory address within instruction buffer 162 where a new instruction is to be stored. A read pointer 165 identifies a memory address within instruction buffer 162 where the next instruction to be processed is read. As more instructions are pending, the number of linked memory addresses between write buffer 164 and read buffer 165 increases. In one embodiment, a threshold 166 is used to identify when the number of instructions pending in instruction buffer 162 has increased or decreased past a limit. It should be noted that the number of linked addresses within instruction buffer 162 can be fixed or dynamic. If the number of linked addresses within the instruction buffer 162 is fixed, the instruction buffer includes a set maximum number of pending instructions that can be supported. Accordingly, pending instructions may need to be dropped if a current number of pending instructions reached the maximum number of pending instructions. If the number of linked addresses within the instruction buffer is dynamic, memory addresses are dynamically allocated to instruction buffer 162 to meet a particular demand. While the size of the instruction buffer can increase as more instructions are received, there may not be enough time to adequately process all the instructions if the number of pending instructions is too high.
Furthermore, the types of instructions stored in instruction buffer 162 may be altered without departing from the scope of the present disclosure. In one embodiment, the types of instructions stored in instruction buffer 162 include display instructions for presenting video or graphics through display 195. It should be appreciated that the instructions may include other instructions, such as multimedia processing instructions, such as video and/or audio processing commands. While instruction buffer 162 is shown as a part of RAM 160 and system 100, it should be noted that instruction buffer 162 can be stored external to system 100.
By monitoring the number of instructions in instruction buffer 162, power module 300 may determine that an increased level of processing will be needed to process the number of pending instructions within a particular amount of time. For example, if a number of pending instructions is greater than a threshold 166, or an increasing rate of the number of pending instructions is greater than a particular value, power module 300 initiates a normal, or high reliability, power mode, in which all or most power is available to system 100. The normal power mode insures the instructions are processed using all available resources of system 100. Alternatively, if read pointer 165 falls below threshold 166, power module 300 may initiate a power conservation mode. Since the number of instructions to be processed is lower than normal, power module 300 can conserve excess power without overflowing the instruction buffer 162.
In one embodiment, power module 300 monitors a rate of change of the number of instructions in instruction buffer 162. If the number of instructions is increasing at a specific rate, power module 300 may switch from a power conservation mode to a normal power mode to anticipate an upcoming high demand for processing. Furthermore, power module 300 can be used to monitor the types of instructions stored in instruction buffer 162. For example, instruction buffer 162 may store a number of instructions lower than threshold 166; however, the number of instructions can include process intensive instructions. Alternatively, the number of instructions may include simple instructions that can be processed quickly. Accordingly, power module 300 can initiate power conservation modes based on an amount of processing needed by the type of instructions stored in instruction buffer 162.
Power module 300 can activate measures to respond to an identified power mode. When a normal power mode is initiated, power module 300 can provide power to all components of system 100. For example, power module 300 can provide the raw clock signal generated by oscillator 110 to the input of PLL 130. When a power conservation mode is initiated, power module 300 bypasses the locked clock signal output by PLL 130. For example, in one embodiment, the locked clock signal output from the PLL 130 and the raw clock signal from the oscillator 110 are provided to a set of multiplexors 121 and 122. In a normal mode of operation, multiplexers 121 and 122 provide the locked clock signal to clock busses 150 and 155, respectively. When the power conservation mode is initiated, the power module 300 sets multiplexors 121 and 122 to only use the raw clock signal output by the oscillator 110. Accordingly, during power conservation modes, the raw clock signal can be used as a clock source for dividers 140 and 145.
The clock signal output by dividers 140 and 145 are provided to clock busses 150 and 155, respectively, and used for processes within system 100. While the raw clock signal generated by oscillator 110 may not be as fast or as stable as the locked clock signal generated through PLL 130, the raw clock signal may be an adequate source for the second divider 145, running at a slower speed than the first divider 140.
To conserve power, power module 300 can also set the PLL 130 into a power down mode during the power conservation mode. In one embodiment PLL 130 is powered down by disabling clock signals input into the PLL 130. A switch (not shown) can be provided to disable input of the raw clock signal generated through oscillator 110 to the PLL 130. Alternatively, PLL 130 can be shut off by cutting power to the PLL 130. However, it should be noted that as the PLL 130 may be a complementary metal oxide semiconductor (CMOS) device, it may be preferable to disable a clock signal provided to PLL 130 in place of disabling power provided to PLL 130.
In one embodiment, power module 300 is capable of setting multiplexors 121 and 122 independently of each other. Accordingly, multiplexor 121 can be set to use the locked clock signal while multiplexor 122 is set to use the raw clock signal. Alternatively, a single multiplexor can be used in place of multiplexors 121 and 122 to provide either the locked clock signal or the raw clock signal to first divider 140 and/or second divider 145.
In one embodiment, power module 300 monitors display content. For example, power module 300 monitors received display data, or compares a new set of display data to an old set of display data, to determine if the display content has changed. If the display content has not changed recently, power module 300 initiates a power conservation mode. If the display content has changed, the power module 300 may switch to, or remain in, the normal mode.
In one embodiment, when in a power conservation mode, power module 300 sends signals to enable power saving features through a display module 170. In one embodiment, display module 170 controls a number of bits used to represent display data sent through display port 180. To conserve power, display module 170 may be directed to use fewer bits to represent some or all bits of the display data. In on embodiment, a number of bits used to represent color is reduced. For example, the color depth of the display data can be reduced from 32-bit color to 16- or 8-bit color The display data is provided to a display device 195, through display interface 190. Display port 180 and display interface 190 use a set number of interface lines to transfer display data to display device 195. In one embodiment, when fewer bits are used to represent the display data, less communications lines may need to be powered. Accordingly, less power is needed to transfer the display data from display port 180 to display device 195, through display interface 190.
The display interface 190 includes various interface adapters for transporting the display data to the display device 195, such as a digital to analog converter (DAC), a transition minimized differential signaling (TMDS) transceiver, or a low voltage differential signaling (LVDS) transceiver, without departing from the scope of the present disclosure. While interface input lines can be disabled to reduce power, it should be appreciated that simply transmitting less data can conserve a substantial amount of power. Accordingly, a frame rate or a refresh rate associated with the display data being sent to display device 195 can be reduced to conserve power. As display content may not be changing, display module 170 can reduce the number of frames per second being displayed on display device 195 without drastically affecting the appearance of content displayed on the display device 195. A bit depth used to represent other forms of multimedia data may also be reduced to lower power consumption. For example, a number of bits used to represent audio data may also be reduced to simplify multimedia processing and conserve power. Accordingly, power consumption can be reduced by having less data being transferred from display port 180 per unit time. In one embodiment, slower clock signals can be used to process multimedia data represented with a lower bit depth than multimedia data with a higher or normal bit-depth. In one embodiment, display device 195 includes a display device associated with a PDA, such as a liquid crystal display screen.
Power module 300 can initiate other forms of power conservation modes. In one embodiment, power module 300 initiates a suspend mode. Power module 300 can determine when system 100 has not been used for an extended period of time. If a lack of video data has been sent to system 100 or an information handling system interfaced with system 100 has not been active for a particular period of time, power module 300 initiates a suspend mode. Furthermore, if no instructions are provided to system 100, power module 300 can initiate the suspend mode. In one embodiment, power module disables oscillator 110 as part of the suspend mode. Power module 300 may provide a signal to switch 125 to disable a signal provided from clock driver 115 to oscillator 110. Alternatively, power module 300 may disable power to the clock driver 115 to disable oscillator 110 and the raw clock signal. Furthermore, power module 300 may provide a signal to display module 170 to disable display data output through display port 180.
In one embodiment, power module 300 controls an amount of power provided to system 100. Power module 300 may reduce a total amount of power provided to system 100 to match less power needed in power conservation modes, in comparison to a normal or nominal power mode. It should be appreciated that other forms of power conservation may also be incorporated without departing from the scope of the present disclosure.
Referring now to
In step 205, the power module sets the subsystem to a normal operating mode. In step 210, in accordance with the normal operating mode, the power module enables an external oscillator, such as oscillator 100 (
In step 220, the power module monitors the status of components of the subsystem to identify a level of activity and an appropriate power mode. In one embodiment, the power module monitors a number of pending instructions to determine the power mode. For example, if the number of pending instructions has increased greater than a threshold, the power module may determine a normal, or high-reliability, power mode is necessary to ensure all the instructions are processed in time. Alternatively, if the number of pending instructions is less than the threshold, the power module may determine the subsystem may operate in a reduced operation mode, wherein power can be conserved. Furthermore, if no instructions are pending, the power module may determine that processing within the subsystem may be suspended by hardware components of the subsystem.
The power module may also monitor display content to determine a mode of operation or a power mode to employ. The power module may monitor the display content to determine if new content is to be displayed. If new display content is identified, the power module may determine a normal power mode is needed. If new display content is not different from old display content, the power module may determine the subsystem should be in a reduced operation mode to conserve power.
If a normal mode is to be used, the power module initiates a normal power mode in the device, such as previously discussed in reference to step 210. Alternatively, if a reduced operation mode is to be used, the power module initiates a power conservation mode. Accordingly, in step 230, the power module ensures the external oscillator is enabled. In step 240, the PLL is bypassed. In one embodiment, the power module sets a switch or multiplexor to route a clock signal associated with the external oscillator to a clock divider coupled to the output of the PLL in the normal mode. The PLL can also be placed in a power down mode to conserve power while the PLL is bypassed and not being used. In one embodiment, the power module sets a PLL indicator to notify other portions of the subsystem that the PLL is disabled. A delay may need to be provided to allow particular portions of the subsystem time to switch to using the external oscillator for a clock source. Clock signals in the reduced operation mode may be divided to run processes slower than in the normal mode to account for a lack of stability associated with the clock signal generated by the external oscillator in comparison to a PLL output signal. Other forms of power conservation may also be employed in the reduced operation mode. For example, the power module may set the subsystem to represent display data with a reduced number of bits. Accordingly, a number of active interface input lines used to transmit display data to a display device, such as a PDA screen, may be reduced. A frame rate used to update video on a display device can also be reduced to conserve power.
If a suspend mode is to be used, the power module initiates a suspend mode in which several operations within the subsystem are disabled. Accordingly, in step 250, the external oscillator is disabled. In one embodiment, a connection between the external oscillator and a clock driver is broken to disable the external oscillator. Furthermore, a driver signal generally provided to the external oscillator may be replaced with a ground signal. In one embodiment, steps are taken to place the subsystem into the reduced operation mode before initiating the suspend mode. The power module may provide a signal or set an indicator to notify other portions of the subsystem that a suspend mode will be initiated. It should be noted that hardware components may be necessary to transition out of a suspend mode. In one embodiment, the power module uses hardware components to monitor system properties to re-enabling subsystem functions when returning from the suspend mode. The hardware components may monitor user interface buttons. When a user has pressed a user interface button, the hardware components return from the suspend mode to a normal power mode. It should be appreciated that other modes of operation and other forms of conserving power can be employed without departing from the scope of the present invention.
Referring now to
Several components of power module 300 may be used to identify levels of activity within the subsystem. For example, an instruction-monitoring module 400 monitors a number of pending instructions. In one embodiment, instruction-monitoring module 400 compares the number of pending instructions to a threshold value. If the number of pending instructions is less than the threshold, power module 300 initiates a reduced operation, or reduced power, mode. Instruction-monitoring module 400 can also be used to monitor a rate of change in the number of pending instructions, as will be subsequently discussed in reference to
A display-monitoring module 500 may be used to monitor operating characteristics associated with content to be displayed. Display-monitoring module 500 may notify power module 300 when display content has or has not changed. If the display content has not changed, the power module 300 may initiate a power conservation mode to make use of the lack of new display content.
Several controls within power module 300 can be used to initiate power conservation modes. For example, a clock control 340 can be used to apply controls to clocks used within the subsystem. For example, clock control 340 may be used to disable a PLL in a reduced operation mode. Clock registers of registers 310 may be set to indicate to other components of the subsystems that the PLL has been disabled. Clock control 340 may control a switch or multiplexor to route a clock signal generated by an external oscillator to dividers coupled with the disabled PLL. Clock control 340 may also notify other components to switch to the clock signal generated by the external oscillator in place of the clock signal output by the PLL in a normal mode. Furthermore, clock control 340 may be used to disable the external oscillator in a suspend mode in which most or all clocked operations in the subsystem are disabled.
A display control 350 can be used to reduce power associated with display elements in a reduced operation mode. In one embodiment, display control 350 is used to reduce a number of bits used to represent display data. For example, a color depth used to represent pixel elements may be changed. By reducing the number of bits used to represent display data, a number of communications or control lines activated to transfer video data from the subsystem to an interfaced display device or display screen can be reduced. By reducing the number of active interface lines, an amount of power needed to transfer the display data to the display device may be reduced. It should be appreciated that simply providing less data to the display device or display screen can substantially reduce power consumption. For example, a refresh rate associated with the display device or display screen can be reduced to conserve power. Furthermore, display data may be processed within the subsystem more quickly. A lower clock speed may be used to process the display data with the reduced number of bits. Accordingly, the display data may be reliably processed in a reduced operation/power mode.
A power control 320 can be used to control an amount of power provided to the subsystem. As a power conservation mode may be initiated, less power is needed by the subsystem. Power conservation techniques employed by the power module 300, such as disabling the PLL or reducing the number of bits used to represent display data, reduce the total amount of power consumed by the subsystem. Accordingly, power control 320 may be used to reduce the total power provided to the subsystem. Power module 320 may reduce or disable power provided to particular components, such as the clock driver, in response to particular power conservation modes in place.
Registers 310 may be used to enable or disable particular power conservation modes or techniques. Registers 310 can also be used to indicate to other system components that a particular power mode is being implemented. Registers 310 also allow for several properties concerning transitions between power modes to be controlled. Table 1 provides a list of possible registers of registers 310 which may be used, according to one embodiment of the present disclosure.
ENABLES POWER MANAGEMENT
WITHIN THE POWER MODULE
CURRENT POWER MODE
STORED AN IDENTIFIER FOR THE
CURRENT POWER CONSERVATION
POWER MODE REQUEST
SOFTWARE TRANSITION BETWEEN
POWER CONSERVATION MODES
IF DIFFERENT FROM
ENABLES HARDWARE CONTROL
FOR TRANSITIONING FROM A
NORMAL MODE AND A POWER
FOR HARDWARE TO TRANSITION
FROM A NORMAL MODE TO
ENABLES HARDWARE CONTROL
FOR TRANSITIONING FROM A
REDUCED OPERATIONS MODE
TO A NORMAL
DEFINES CONDITIONS FOR
TRANSITIONING FROM A
REDUCED OPERATIONS MODE
TO A NORMAL MODE
DEFINES CONDITIONS HARDWARE
USES FOR WAKING FROM
A SUSPEND MODE
Registers of register 310 can be used by components external to power module 300 to enable particular power conservation modes. A power management enable register can be used to enable or disable operation of the power module 300. If power module 300 is disabled, the system may be set to run in only the normal power mode. Accordingly, user preferences may be linked to disable power conservation modes through the power management enable register. Registers 310 can also include a current power mode register that defines the current or active mode. A power mode request register can be used to force the power module 300 into a new power mode. Conditions for transitioning between power modes may also be set through registers 310. For example, a wakeup condition register may be used to indicate different triggers to monitor for returning from a suspended operation mode. For example, the wakeup condition register may indicate the power module 300 should only leave a suspend mode when a power button or switch is activated by the user.
Referring now to
A fullness monitor 410 tracks a fullness of an instruction buffer, such as instruction buffer 162 (
Alternatively, the number of pending instructions may be equal to or less than the threshold 415. The fullness monitor 410 provides an indicator through output registers 430 that the level of activity is low. The power module can use the reported level of activity to initiate a reduced operation mode in which power to some components is disabled. Furthermore, slower clocks signals can be used to conserve power.
A rate of change monitor 420 is used to monitor a rate of change in the number of pending instructions in the instruction buffer. The rate of change monitor 420 may calculate the rate of change in the number of pending instructions tracked through fullness monitor 410. If the number of pending instructions increases at a high rate, the rate of change monitor 420 may provide a warning of increased activity to the power module, through output registers 430. The power module may use the warning to switch from a reduced operations mode to a normal mode. Accordingly, the rate of change monitor 420 allows the power module to anticipate and react to the changes in the level of activity. In one embodiment, the fullness monitor 410 and rate of change monitor 420 include discrete components for monitoring the instruction buffer. For example, fullness monitor may include logic circuitry to toggle a flag on output registers 430 to indicate a particular power mode when a memory address being written to matches threshold 415. In one embodiment, instruction-monitoring module 400 forms a part of a hardware subsystem to process display instructions associated with a PDA.
Instruction-monitoring module 400 can also include a content monitor 425. Content monitor 425 monitors the types of instructions stored in the instruction buffer to anticipate an amount of processing that may be needed to process the instructions. Content monitor 425 can provide set an indicator through output registers 430 based on a level of processing intensity associated with the instructions stored in the instruction buffer. A first indicator can be used to indicate at least a majority of the instructions in the instruction buffer require minor processing and a second indicator can be used to indicate intensive processing is needed to process the instructions in the instruction bugger. Furthermore, the content monitor 425 can provide a number of instructions of a first type, requiring minor processing, and a number of instructions of a second type, requiring intensive processing. Accordingly, the power module can determine whether or not to enter a power conservation mode based on the types of instructions to be processed.
Referring now to
In one embodiment, to determine when changes in display content have occurred, display-monitoring module 500 analyzes different sets of display content. A first set of display content 510 may include a set of display data currently being displayed. A second set of display content 520 may include a set of display data that will be displayed. A content analyzer 530 compares the display data of the two sets of display content 510 and 520. If the sets of display content 510 and 520 are substantially different, content analyzer can set a flag of output registers 530 indicating the display content is changing. Alternatively, if the two sets of display content 510 and 520 are substantially the same, the content analyzer 530 may apply a value to a register of output registers 530 indicating the display content is not changing. The sets of display content 510 and 520 may include portions of the total display content, allowing content analyzer 530 to determine how much of the display content is actually changing. If only a few portions of the total display content change, the content analyzer may not consider the sets of display content 510 and 520 substantially different. In one embodiment, the sets of display content 510 and 520 are stored in memory, such as in video memory or a frame buffer.
In one embodiment, the power module monitors output registers 530 to determine display activity. If the display content appears to be changing, the power module may initiate a normal power mode to ensure the new display data is processed in time. Alternatively, if the display content is not substantially changing, the power module may initiate power conservation modes. In one embodiment, the power module reduces the number of bits used to represent display data. Using the reduced number of bits, the display data may be processed at slower speeds and less active communications lines are needed to provide the display data to a display device or screen. Furthermore, a frame rate used to output display data can also be reduced. Accordingly, by reducing an amount of data output through a display port, power consumption associated with display data processing and display can be reduced. In one embodiment, the display-monitoring module 500 is part of a set of hardware components used to process display content for output through a display device. While display content is discussed in reference to display-monitoring module 500, it should be appreciated that other forms of content may also be monitored without departing from the scope of the present invention. For example, audio content to be output may be monitored to determine a power mode to be initiated.
The systems described herein may be part of an information handling system. The term “information handling system” refers to any system that is capable of processing information or transferring information from one source to another. An information handling system may be a single device, such as a computer, a personal digital assistant (PDA), a hand held computing device, a cable set-top box, an Internet capable device, such as a cellular phone, and the like. Alternatively, an information handling system may refer to a collection of such devices. It should be appreciated that the system described herein has the advantage of dynamically reducing power consumption in response to system activity.
In the preceding detailed description of the embodiments, reference has been made to the accompanying drawings which form a part thereof, and in which is shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosure, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit or scope of the disclosure. To avoid detail not necessary to enable those skilled in the art to practice the disclosure, the description may omit certain information known to those skilled in the art. Furthermore, many other varied embodiments that incorporate the teachings of the disclosure may be easily constructed by those skilled in the art. Accordingly, the present disclosure is not intended to be limited to the specific form set forth herein, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents, as can be reasonably included within the spirit and scope of the disclosure. The preceding detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4521918 *||Nov 10, 1980||Jun 4, 1985||General Electric Company||Battery saving frequency synthesizer arrangement|
|US4955075 *||Oct 17, 1988||Sep 4, 1990||Motorola, Inc.||Battery saver circuit for a frequency synthesizer|
|US5095280 *||Nov 26, 1990||Mar 10, 1992||Integrated Circuit Systems, Inc.||Dual dot clock signal generator|
|US5142247 *||Aug 6, 1991||Aug 25, 1992||Compaq Computer Corporation||Multiple frequency phase-locked loop clock generator with stable transitions between frequencies|
|US5576738 *||May 3, 1994||Nov 19, 1996||International Business Machines Corporation||Display apparatus with means for detecting changes in input video|
|US5623234 *||Mar 4, 1996||Apr 22, 1997||Motorola||Clock system|
|US5805907 *||Oct 4, 1996||Sep 8, 1998||International Business Machines Corporation||System and method for reducing power consumption in an electronic circuit|
|US5815693 *||Dec 15, 1995||Sep 29, 1998||National Semiconductor Corporation||Processor having a frequency modulated core clock based on the criticality of program activity|
|US5872823 *||Apr 2, 1997||Feb 16, 1999||Sutton; Todd R.||Reliable switching between data sources in a synchronous communication system|
|US5877656 *||May 29, 1997||Mar 2, 1999||Cypress Semiconductor Corp.||Programmable clock generator|
|US5963068 *||Jul 28, 1997||Oct 5, 1999||Motorola Inc.||Fast start-up processor clock generation method and system|
|US6021449 *||Aug 1, 1997||Feb 1, 2000||International Business Machines Corporation||Video FIFO overflow control method that blocks video encoder data when overflow is imminent and resumes flow when frames sizes have returned to nominal size|
|US6219723 *||Mar 23, 1999||Apr 17, 2001||Sun Microsystems, Inc.||Method and apparatus for moderating current demand in an integrated circuit processor|
|US6243820 *||Jun 23, 1995||Jun 5, 2001||Michael H. Davis||Process and apparatus for reducing power usage in microprocessor devices according to the type of activity performed by the microprocessor|
|US6529083 *||Mar 30, 2000||Mar 4, 2003||Fujitsu Limited||Clock control circuit|
|US6654898 *||May 8, 2000||Nov 25, 2003||Apple Computer, Inc.||Stable clock generation internal to a functional integrated circuit chip|
|US6658508 *||Jan 31, 2000||Dec 2, 2003||Koninklijke Philips Electronics N.V.||Expansion module with external bus for personal digital assistant and design method therefor|
|US6687322 *||Oct 6, 2000||Feb 3, 2004||Adaptec, Inc.||Dual mode clock alignment and distribution device|
|US6691215 *||Sep 26, 2000||Feb 10, 2004||Sun Microsystems, Inc.||Method and apparatus for reducing power consumption|
|US6704892 *||May 31, 2000||Mar 9, 2004||Intel Corporation||Automated clock alignment for testing processors in a bypass mode|
|US6704908 *||Nov 6, 2000||Mar 9, 2004||Amadala Limited||Method and apparatus for automatically generating a phase lock loop (PLL)|
|US6775787 *||Jan 2, 2002||Aug 10, 2004||Intel Corporation||Instruction scheduling based on power estimation|
|US6785826 *||Jul 17, 1996||Aug 31, 2004||International Business Machines Corporation||Self power audit and control circuitry for microprocessor functional units|
|US6859399 *||Jul 20, 2000||Feb 22, 2005||Marvell International, Ltd.||Memory architecture and system and multiport interface protocol|
|US20030003876 *||May 22, 2002||Jan 2, 2003||Rumsey Daniel L.||Multimedia PDA attachment unit|
|US20050015634 *||Jun 2, 2004||Jan 20, 2005||Rosch Winn L.||Process and apparatus for reducing power usage in microprocessor devices according to the type of activity performed by the microprocessor|
|JPH1168881A *||Title not available|
|1||U.S. Appl. No. 10/083,875, Mizuyabu, et al., Pending.|
|2||U.S. Appl. No. 10/083,917, Mizuyabu, et al., Pending.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7146513 *||Feb 6, 2004||Dec 5, 2006||Hitachi, Ltd.||System for adjusting a clock frequency based on comparing a required process times and a worst case execution times and adjusting a voltage and clock frequency based on a number of ready state application tasks|
|US7284138||Dec 2, 2004||Oct 16, 2007||International Business Machines Corporation||Deep power saving by disabling clock distribution without separate clock distribution for power management logic|
|US7443221 *||May 23, 2005||Oct 28, 2008||Broadcom Corporation||System and method for fully digital clock divider with non-integer divisor support|
|US7570259 *||Jun 1, 2004||Aug 4, 2009||Intel Corporation||System to manage display power consumption|
|US7656237 *||Feb 2, 2010||International Business Machines Corporation||Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic|
|US7667517||Oct 28, 2008||Feb 23, 2010||Broadcom Corporation||System and method for fully digital clock divider with non-integer divisor support|
|US7783905 *||Jun 13, 2006||Aug 24, 2010||Via Technologies Inc.||Method for reducing power consumption of a computer system in the working state|
|US7800621||Sep 21, 2010||Ati Technologies Inc.||Apparatus and methods for control of a memory controller|
|US7827424||Nov 2, 2010||Ati Technologies Ulc||Dynamic clock control circuit and method|
|US7849339||Dec 7, 2010||Silicon Image, Inc.||Power-saving clocking technique|
|US7925907 *||Apr 12, 2011||Nvidia Corporation||Using non-lossless compression to save power|
|US7940139 *||Jul 19, 2007||May 10, 2011||Nec Corporation||Voltage-controlled oscillator, frequency synthesizer, and oscillation frequency control method|
|US8059209 *||Nov 15, 2011||Funai Electric Co., Ltd.||Broadcast signal receiving device and method|
|US8094147 *||Jan 10, 2012||Anapass Inc.||Display device and method for transmitting clock signal during blank period|
|US8111799 *||Jan 3, 2008||Feb 7, 2012||Dell Products L.P.||Method, system and apparatus for reducing power consumption at low to midrange resolution settings|
|US8335941||Dec 18, 2012||Via Technologies, Inc.||Method for reducing power consumption of a computer system in the working state|
|US8510487||Feb 11, 2010||Aug 13, 2013||Silicon Image, Inc.||Hybrid interface for serial and parallel communication|
|US8555091||Oct 27, 2010||Oct 8, 2013||Intel Corporation||Dynamic power state determination of a graphics processing unit|
|US8593470 *||Feb 24, 2005||Nov 26, 2013||Ati Technologies Ulc||Dynamic memory clock switching circuit and method for adjusting power consumption|
|US8661284 *||Jan 15, 2013||Feb 25, 2014||Intel Corporation||Method and system to improve the operations of a registered memory module|
|US8738945||Mar 23, 2011||May 27, 2014||Nvidia Corporation||Using non-lossless compression to save power|
|US8751709||Jul 2, 2013||Jun 10, 2014||Silicon Image, Inc.||Hybrid interface for serial and parallel communication|
|US8760188||Jun 30, 2011||Jun 24, 2014||Silicon Image, Inc.||Configurable multi-dimensional driver and receiver|
|US8799685||Aug 25, 2010||Aug 5, 2014||Advanced Micro Devices, Inc.||Circuits and methods for providing adjustable power consumption|
|US8832412 *||Sep 20, 2011||Sep 9, 2014||Broadcom Corporation||Scalable processing unit|
|US8885435||Sep 18, 2012||Nov 11, 2014||Silicon Image, Inc.||Interfacing between integrated circuits with asymmetric voltage swing|
|US9071243||Jun 30, 2011||Jun 30, 2015||Silicon Image, Inc.||Single ended configurable multi-mode driver|
|US9240784||May 20, 2015||Jan 19, 2016||Lattice Semiconductor Corporation||Single-ended configurable multi-mode driver|
|US9281969||Jun 9, 2014||Mar 8, 2016||Silicon Image, Inc.||Configurable multi-dimensional driver and receiver|
|US9306563||Feb 19, 2013||Apr 5, 2016||Lattice Semiconductor Corporation||Configurable single-ended driver|
|US9348403 *||Mar 31, 2015||May 24, 2016||Renesas Electronics Corporation||Semiconductor device and automobile control system|
|US9386521||Dec 20, 2012||Jul 5, 2016||Qualcomm Incorporated||Clock structure for reducing power consumption on wireless mobile devices|
|US20050138452 *||Feb 6, 2004||Jun 23, 2005||Hitachi, Ltd.||Information processing system and operating system|
|US20050289360 *||Jun 1, 2004||Dec 29, 2005||Rajesh Banginwar||System to manage display power consumption|
|US20060017486 *||May 23, 2005||Jan 26, 2006||John Iler||System and method for fully digital clock divider with non-integer divisor support|
|US20060026450 *||Jul 29, 2004||Feb 2, 2006||Ati Technologies, Inc.||Dynamic clock control circuit and method|
|US20060119445 *||Dec 2, 2004||Jun 8, 2006||International Business Machines Corporation||Method to gate off PLLS in a deep power saving state without separate clock distribution for power management logic|
|US20060123261 *||Dec 2, 2004||Jun 8, 2006||International Business Machines Corporation||Deep power saving by disabling clock distribution without separate clock distribution for power management logic|
|US20060187226 *||Feb 24, 2005||Aug 24, 2006||Ati Technologies Inc.||Dynamic memory clock switching circuit and method for adjusting power consumption|
|US20060259804 *||May 16, 2005||Nov 16, 2006||Ati Technologies, Inc.||Apparatus and methods for control of a memory controller|
|US20070288782 *||Jun 13, 2006||Dec 13, 2007||Via Technologies, Inc.||Method for reducing power consumption of a computer system in the working state|
|US20080235526 *||Mar 23, 2007||Sep 25, 2008||Silicon Image, Inc.||Power-saving clocking technique|
|US20090051400 *||Oct 28, 2008||Feb 26, 2009||Broadcom Advanced Compression Group||System and method for fully digital clock divider with non-integer divisor support|
|US20090175397 *||Jan 3, 2008||Jul 9, 2009||Dell Products L.P.||Method, System and Apparatus for Reducing Power Consumption at Low to Midrange Resolution Settings|
|US20090237395 *||Mar 20, 2009||Sep 24, 2009||Yong-Jae Lee||Display device and method for transmitting clock signal during blank period|
|US20100176888 *||Jul 19, 2007||Jul 15, 2010||Nec Corporation||Voltage-controlled oscillator, frequency synthesizer, and oscillation frequency control method|
|US20100191988 *||Apr 1, 2010||Jul 29, 2010||Via Technologies, Inc.||Method for reducing power consumption of a computer system in the working state|
|US20110154069 *||Jun 23, 2011||Edward Costales||Dynamic power state determination|
|US20110173476 *||Jul 14, 2011||Nvidia Corporation||Using non-lossless compression to save power|
|US20110196997 *||Aug 11, 2011||Ruberg Alan T||Hybrid interface for serial and parallel communication|
|US20130024652 *||Sep 20, 2011||Jan 24, 2013||Broadcom Corporation||Scalable Processing Unit|
|US20150121110 *||Oct 8, 2014||Apr 30, 2015||Em Microelectronic-Marin Sa||Electronic circuit with a sleep mode|
|US20150268715 *||Mar 31, 2015||Sep 24, 2015||Renesas Electronics Corporation||Semiconductor device and automobile control system|
|WO2008118821A1 *||Mar 21, 2008||Oct 2, 2008||Silicon Image, Inc.||Power-saving clocking technique|
|U.S. Classification||713/323, 713/324, 713/300, 331/49, 375/376, 365/227, 331/60, 345/214, 345/211, 345/204, 713/322, 331/74, 713/330, 713/320|
|International Classification||G06F1/32, G06F1/10|
|Cooperative Classification||Y02B60/1242, G06F1/3203, G06F1/3265, Y02B60/1221, G06F1/10, G09G2330/021, G06F1/3218, G06F1/3225, G06F1/3237|
|European Classification||G06F1/32P1C6, G06F1/32P5P5, G06F1/32P5C, G06F1/32P1C2, G06F1/32P, G06F1/10|
|Feb 27, 2002||AS||Assignment|
Owner name: ATI TECHNOLOGIES, INC., CANADA
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