US 7042377 B2 Abstract An analog-to-digital sigma-delta modulator for converting analog input signals to digital output signals comprises a feedback path (
1, 101, 201) for producing analog feedback signals that are a function of the digital output signals (y, Y), an N-stage (N=2) integrator path (9 to 14, 109 to 114) for integrating analog difference signals that are a difference function of the input signal and the analog feedback signals, and a quantizer (3, 103) responsive to the signals integrated by the integrator means (9 to 14, 109 to 114) for producing the digital output signals (y, Y) at clock intervals. The feedback path includes N feedback stages (15 to 17, 115 to 117) for respective integrator stages (9 to 14, 109 to 114).Each of the N feedback stages (
15 to 17, 115 to 117) comprises finite impulse response (FIR) filters (15 to 19, 115 to 117), each of the FIR filters being of the same order M, where M is at least two; at least the filter (15, 115) of the feedback stage that feeds back to the first integrator stage is a low pass filter.The integrator stages may be discrete-time integrators; the FIR filters reduce their sensitivity to feedback voltage step changes that would cause non-linearities due to slew-rate limitations. Alternatively, the integrator stages may be continuous-time integrators; the FIR filters reduce their sensitivity to clock pulse jitters. In the embodiment shown in FIG.
11, the first integrator stage (109, 110) is a continuous-time integrator stage, and the remainder of the integrator stages (11 to 14) are discrete-time integrator stages.Claims(8) 1. An analog-to-digital sigma-delta modulator for converting analog input signals to digital output signals comprising feedback path means for producing analog feedback signals that are a function of said digital output signals, integrator means for integrating analog difference signals that are a difference function of said input signal and said analog feedback signals, and a quantizer responsive to the signals integrated by said integrator means for producing said digital output signals at clock intervals, said integrator means including N integrator stages, where N is at least two, said input signal being applied to a first one of said integrator stages, said feedback path means including N feedback stages for feeding back said feedback signals at respective integrator stages of said integrator means, and said feedback path means including finite impulse response filter means, each of said N feedback stages comprising finite impulse response filter means, each of said finite impulse response filter means being of order M, where M is at least two, and at least the filter of the feedback stage that feeds back to said first integrator stage being a low pass filter.
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Description This invention relates to analog-to-digital sigma-delta modulators. Sigma-delta modulators are now widely used for conversion between analog and digital signals, especially with advances in very large-scale integrated circuit technology (VLSI). An article by P. M. Aziz, H. V. Sorensen and J. van der Spiegel in IEEE Signal Processing magazine, January 1996 gives an overview of analog-to-digital sigma-delta modulators as used in analog-to-digital converters for example. An article by P. F. Ferguson, Jr. A. Ganesan and R. W. Adams, One Bit Higher-Order Sigma-Delta A/D Converters, IEEE International Symposium on Circuits and Systems, pp. 890893, 1990 gives a presentation of the general form of higher-order signal-delta modulators including filters in both feed-forward and feedback paths. Two basic kinds of sigma-delta modulators exist: discrete-time and continuous-time. In general terms, an analog-to-digital sigma-delta modulator receives analog input signals X (that is to say whose amplitude represents data) and converts them at clock intervals to encoded digital output signals Y (that is to say pulses whose amplitude is constant and whose repetition rate represents the data). The modulator comprises a feedback path An article by D. K. Su and B. A. Wooley, A CMOS Oversampling D/A Converter with a Current-Mode Semidigital Reconstruction Fllter, IEEE Journal of Solid-State Circuits, Vol. 28, No. 12, December 1993, pp. 12241233 gives a description of a digital-to-analog modulator including a finite impulse response (FIR) filter, in particular a semi-digital FIR filter in the output path. The technique proposed is not applicable to an analog-to-digital modulator. In U.S. Pat. No. 5,357,252, assigned to the assignee of the present invention, first-order FIR filtering in the feedback path of the first stage of an analog-to-digital modulator is proposed to combat the pattern noise. This method changes the noise transfer function of the modulator and its extension to higher-order filtering is not practicable. An article by T. Okamoto, Y. Maruyama and A. Yukawa, A Stable High-Order-Delta-Sigma Modulator with an FIR Spectrum Distributor, IEEE Journal of Solid-State Circuits, Vol. 28, No. 7, pp. 730735, July 1993, describes a noise-shaper circuit including an FIR spectrum distributor, used to improve the stability of higher-order modulators. The order of FIR filtering is limited to twice the modulator order. The orders of the successive FIR filters are not the same but are stepped from one up to the modulator order along the feedback path. No improvement in terms of power or distortion is apparent in this architecture. It is noted that the article describes a digital-to-analog modulator whose feedback path includes a plurality of feedback stages including finite impulse response filters of differing orders. Concerns that arise in the design of analog-to-digital sigma-delta modulators include their sensitivity to the effects of feedback voltage step changes and clock pulse instabilities. The present invention provides novel analog-to-digital sigma-delta modulators that address these concerns, among others. The present invention provides an analog-to-digital sigma-delta modulator as described in the accompanying claims. The design of a sigma-delta modulator must take account of many different criteria and achieve a suitable compromise between sometimes conflicting requirements. Thus, power consumption in a sigma-delta modulator is a direct function of its sampling frequency and dynamic range. Sampling capacitors such as During the integration phase, the output of an SC-integrator In the prior art discrete-time sigma-delta modulator structure shown in In such a prior art sigma-delta modulator, the feedback path is responsible for the abruptness of the voltage variations. The embodiments of the present invention shown in Referring now to In calculating the coefficients for the FIR filters, it is convenient to calculate the function F k The transfer function A(z) and B(z) of the FIR filters
If for the sake of simplicity,D(z) is required to remain a second order polynomial, it follows that:
The coefficients of A(z) can be obtained as:
and the coefficients of B(z) can then be calculated. In a practical implementation, calculation of an ideal filter from quadratic programming offers the optimum noise suppression for a given filter length. In practical integrated circuit design, it is convenient to implement all coefficients using capacitors that are integer multiples of a unit capacitor and, in a particular embodiment of the present invention, a comb filter is used as the FIR filter
The corresponding optimum values for the second integrator stage FIR filter can be shown to be:
Examples of the FIR filter coefficients for M=0 (corresponding to a modulator as shown in
The last column of the table shows the sum of coefficients of b(z), which represents the factor by which the feedback capacitor of the second integrator increases. The FIR filters used in the embodiments of the present invention shown in Each stage of each FIR filter comprises a voltage reference switch If the size of the integrator capacitor It will be appreciated that the description given above with reference to In addition, feed forward, interpolation and resonance paths may be added. The choice of the order of the FIR filters, which are identical for each integrator stage, may be a compromise. A higher order decreases the voltage steps applied to the integrator first stage, enables the speed of the first stage to be reduced and hence enables a reduction in the parasitic capacitance and power consumption of the first integrator stage. On the other hand, a lower order FIR filter reduces the complexity of the clock routing connections. A suitable compromise for a two-stage discrete-time integrator may be a fourth or fifth order for the FIR filters. The discrete-time sigma-delta modulator embodiments of the present invention described above with reference to The present invention is also applicable to continuous-time (CT) sigma-delta modulators. In continuous-time modulators the amplifier bandwidth can be quite close to the sampling frequency and thermal noise is not aliased. In addition, the structure inherently presents an anti-aliasing pre-filtering with regard to the input signal. However, a prior art CT-modulator such as shown in The operation of a typical basic second-order continuous-time sigma-delta modulator is illustrated schematically in The analog feedback signal is a rectangular pulse of duration τ and with a delay t
- where σ
_{τ}^{2 }is the variance of the effect of the clock jitter on the pulse width τ,
α=−2+τ/(2T) and -
- T is the clock period.
The result of pulse duration jitters in the output spectrum is both a white noise component and a first order shaped noise, the latter being of substantially reduced importance, due to the output filters. The effect of clock jitters on the pulse delay, on the other hand, give rise to a first order shaped noise spectrum:
The white noise component can be represented by an error ε Choice of the coefficients of the transfer function of the first FIR filter for the first integrator stage A satisfactory solution when the input signal is unknown or when the optimum spread of filter coefficients is troublesome for analog implementation is again the use of a comb filter, as described above for the discrete-time modulator. A preferred embodiment of the nth stage of an FIR filter is shown in In both CT and DT modulators, the first stage is the most critical. In fact, the circuit imperfections are dominated by those generated by the first stage. These imperfections are essentially thermal noise, harmonic distortion and jitter-induced noise. For this reason the first stage is the most power and area consuming block. Yet another embodiment of the present invention, shown in In a practical implementation of the mixed-time sigma-delta modulator of the kind shown in In a practical second order modulator of this kind, with gain of each of the integrator stages for the first stage FIR filter
for the second stage FIR filter 16
In calculating the improvement obtained with this type of circuit compared to the modulators of
It can be shown that the white noise spectrum that results at the output from clock pulse width jitters at the first stage is:
where _{y }is the output auto-correlation function of the modulator. The improvement in the result at the modulator output of clock pulse width jitters at the first integrator stage compared to the modulator of
To a first approximation, the modulator output spectrum due to clock pulse width jitters at the first stage is less than:
where A is the amplitude of the input signal applied to the modulator and Θ is a factor related to N, the number of integrator stages, and M, the order of the FIR filters. Calculation shows that the worst case for the effect of clock jitters on the modulator output is when the input signal frequency is in the pass band of the low pass FIR comb filter
The calculated values of S Ignoring quantization noise, the output signal-to-noise ratio of the modulator is given by:
where σ A major advantage of this embodiment of the invention appears especially for small signals, which significantly extends the modulator dynamic range. The dynamic range represents the capability of the system in capturing weak signals and in many applications it is more critical than SNR In addition to reducing the effect of clock jitters at the first, continuous-time integrator stage, the low pass FIR filters have a smoothing effect that reduces voltage variations at the output of the first integrator Once again, it will be appreciated that the description given above with reference to Patent Citations
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