|Publication number||US7045390 B2|
|Application number||US 10/413,320|
|Publication date||May 16, 2006|
|Filing date||Apr 15, 2003|
|Priority date||Dec 11, 2000|
|Also published as||EP1350270A1, EP1350270B1, US6670217, US6696318, US20020121693, US20020123172, US20020127837, US20030180987, WO2002049109A1, WO2002049109B1|
|Publication number||10413320, 413320, US 7045390 B2, US 7045390B2, US-B2-7045390, US7045390 B2, US7045390B2|
|Inventors||Juan G. Milla, Robert L. Hubbard|
|Original Assignee||Medtronic, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (27), Non-Patent Citations (1), Referenced by (4), Classifications (30), Legal Events (2)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of application Ser. No. 09/734,073, filed Dec. 11, 2000, now abandoned.
The present invention relates generally to implantable medical devices (IMDs) incorporating stacked die packages. Specifically, the invention pertains to stacked die configurations adapted for use in IMDs.
As implantable medical devices become smaller and smaller, and as more and more components are added to such devices, the real estate available for components is shrinking. Components too are shrinking in size, but the need for improving the use of available volume and space continues.
In implantable medical devices, the footprints of dice and stacked dice packages typically exceed the bottom die size. For example, when wire bonding is used to electrically connect a die to rigid or flexible interposers, the package size is much larger than the bottom die size, and is therefore very size inefficient.
One stacked die package in the industry uses a structure having a number of chips glued to one side of a substrate, and a connection array also laid out on the same side of the substrate. The chips are stacked by repeated hand-folding and adhering. This structure requires that perforations be placed along bend lines of the substrate to allow bending along precisely the correct lines. Further, each individual stacked package is cut individually once the substrate is folded.
In one embodiment, a method for making a stacked die package includes mounting at least two chips on a first side of a flexible substrate, forming solder balls on a second side of the substrate, and interconnecting the chips and the solder balls through the substrate. Once the chips are interconnected with the solder balls, the chips are stacked, and the stacked device is surface mounted.
In another embodiment, a method for forming a stacked die package includes stiffening a flexible substrate with a stiffener frame, forming an array of mounting elements on a first side of the flexible substrate, positioning the substrate mounting elements down on a reflow boat or foundation, and mounting and reflowing a number of chips on a second side of the flexible substrate in a predetermined pattern. Once the chips are mounted, they are stacked, and the substrate stiffener is removed.
In yet another embodiment, a stacked die array includes a stacked array of chips adhered together on a flexible substrate folded to accommodate mounting, a surface mount element on a side of the substrate opposite the chips, and through-substrate routing electrically connecting the chips and the surface mount element.
In still another embodiment, an IMD includes a device body and a stacked chip array mounted by conventional surface mount techniques to a printed circuit board.
Other embodiments are described and claimed as described hereinbelow.
In the following detailed description of the embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention.
In one embodiment, the flexible substrate is stiffened with a stiffener in block 101. When the substrate is stiffened, the method becomes more reproducible due to the added rigidity and ability to work on the product. In one embodiment, the substrate is stiffened with a printed wiring board (PWB) stiffener. Other stiffeners include by way of example only and not by way of limitation, metal, screens, and the like. One requisite for a stiffener is that it be amenable to bending when the chips mounted to the substrate are to be stacked.
To mount chips as in block 102, in one embodiment the substrate and any attached stiffener are inverted after applying the solder ball array. Once inverted, the substrate is placed on a reflow boat, and chips are mounted according to a predetermined pattern on the substrate and reflowed. In one embodiment, the predetermined pattern is laid out on the substrate in a sub panel format which has been determined for folding patterns. The layout of sub panel patterns for efficient folding to stack chips is known to those of skill in the field, and will not be described further herein. Provided that the sub panel layout is sufficient for folding and stacking the chips, the layout is consistent with the embodiments of the present invention.
The stiffener allows the substrate to be maintained in a rigid form without the need for a specialized frame to hold the substrate during process flow. Since the stiffener is connected to the substrate, the stiffener is present wherever the substrate is, thus providing rigidity without sacrificing portability during process flow.
In one embodiment, once the chips have been stacked by folding and adhering and curing, and before mounting the stacked die package, the stiffener is removed in block 109. In one embodiment, the stiffener is saw cut away, separating the stiffener and the stacked die package, leaving a stacked die package ready for surface mounting. The arrangement and layout of the substrate and the stiffener allow the stiffener to be fully cut away in a single saw cut, leaving multiple stacked die packages ready for mounting. The sub panel layout allows such a single saw cut to be feasible. In optional process flow, the chips are underfilled.
Stacking the chips in accordance with method 150 shown in
In another embodiment, method 200 for forming a stacked die package is shown in
An embodiment 300 of a stiffened substrate is shown in
While a stiffener such as stiffener 304 is described herein, other means or components for maintaining rigidity and workability of the substrate are contemplated, and are within the scope of the invention. For example, in one embodiment, a spacer is used instead of the stiffener.
Once the substrate 302 is stiffened with stiffener 304, it undergoes in one embodiment the processes described above. These processes are shown in greater detail on
In one embodiment, the flexible substrate 506 has formed therein a sub panel layout for the layout of chips such as chips 502 so that folding of the substrate 506 aligns or abuts the chips 502 top to top. Multiple individual designs are laid out on the substrate 506 in one embodiment. The substrate folds along predetermined patterns to align the chips together as desired.
In another embodiment shown in
Recently, high voltage flip chip designs have been implemented in implantable medical devices. Such a high voltage flip chip design is not described herein, but the methods and devices of the present invention are also amenable and applicable to use in high voltage flip chip stacked die packages.
In another embodiment, the substrates of the present invention are laid out in a format wherein the components to be stacked are not the same size. With proper arrangement and chip layout, chips or components of different sizes are stacked in the same manner as that described above.
Most electronic devices can afford the extra volume of previous larger footprint designs. However, decreased volume and space are a market driver for implantable medical devices, specifically, and other medical devices. Stacking dice significantly reduces the area required on hybrid modules and therefore decreases the necessary volume of the module. The stacked die packages of the present invention embodiments have smaller footprints, but typically have increased vertical height over traditional packages due to the stacking of chips. The increase in vertical height due to the use of stacked die packages is not a critically limiting factor due to the use of other high profile components in such devices.
It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
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|U.S. Classification||438/109, 257/E21.705, 257/E23.177, 257/E25.013|
|International Classification||H01L21/68, H01L23/538, H01L21/44, H05K3/34, H01L21/98, H01L25/065|
|Cooperative Classification||H01L2924/1305, H01L2924/1301, H01L2924/13091, H05K3/3478, H01L23/5387, H01L2225/06586, H01L2225/06579, H01L2225/06593, H01L25/50, H01L2225/06517, H01L25/0657, H01L21/6835, H01L2924/3025, H01L2224/16225, H01L2224/73253, H01L2224/32145|
|European Classification||H01L21/683T, H01L25/50, H01L25/065S, H01L23/538J|
|Sep 28, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Nov 18, 2013||FPAY||Fee payment|
Year of fee payment: 8