|Publication number||US7051229 B2|
|Application number||US 10/308,026|
|Publication date||May 23, 2006|
|Filing date||Dec 3, 2002|
|Priority date||Dec 3, 2002|
|Also published as||DE60311060D1, DE60311060T2, EP1434139A2, EP1434139A3, EP1434139B1, US20040117512|
|Publication number||10308026, 308026, US 7051229 B2, US 7051229B2, US-B2-7051229, US7051229 B2, US7051229B2|
|Inventors||Steven Douglas Margerm, Darwin Noel Hawes|
|Original Assignee||Alcatel Canada Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (3), Classifications (10), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to increasing the data rate of a system bus in a switch/router, particularly while supporting legacy cards of a lower data rate.
Patent Prior Art:
This patent discloses an output driver circuit that drives first and second portions of data onto a bus on rising and falling edge transitions of an external clock signal, respectively. A clock circuit is required to derive low skew internal clock and inverted clock signals from the external clock signal (see column 4, lines 30–33). The internal clock and inverted block signals define odd and even cycles to which all slave devices (e.g. DRAMs) connected to the bus must be able to respond (see column 8, lines 15–40). This capability requires that new circuitry be added to such prior art slave devices (see column 4, lines 24–29). In effect, the bus rate is simply doubled by using both edges of the bus clock.
The problem of the bus architecture of
Problems With Prior Art Patents:
In general, the known prior art teaches techniques of increasing the data rate of a bus using TDM approaches that require modification of existing (legacy) devices connected to the bus, in order to make these devices compatible with the modified bus.
The object of the present invention is to provide a system and method for increasing the data rate of a system bus without making modifications to existing (legacy) devices connected to the bus. According to the invention, a logical bus is overlaid onto one or more existing physical buses in a TDM manner. The overlaying is done by transmitting data into the one or more of the existing buses during a previously unused phase of the bus clock, thereby having no effect on existing devices connected to the buses. The additional devices that are capable of latching data on either phase of the bus clock are provided to interwork with the overlaid bus.
Thus, there is provided a method and apparatus of increasing the data rate of the bus of an electronic system having a bus clock with rising and falling edges and a first device coupled to the bus that is operable to latch data from the bus responsive to one edge of the bus clock comprising coupling to the bus, a bus driver that is operable to drive data onto the bus responsive to the other edge of the bus clock and coupling to the bus a second device operable to latch data from the bus responsive to the other edge of the bus clock. A further device operable to latch data from the bus that selectively responds to either edge of the bus clock may be provided. The invention contemplates configuring a third device to latch data from the bus responsive to a particular one of the two edges of the bus clock. Moreover, a further feature of the invention is that there are a plurality of devices of the same type as the first device, replacing one device of the plurality of the device of the same type as the second type device. The invention further features a bus driver operable to drive data onto a bus responsive to both edges of the bus clock and a further feature comprises decoupling from the bus an existing bus driver that is operable to drive data under the bus only in response to one edge of the bus clock.
The above and other objects, advantages and features of the invention will become more apparent when considered with the accompanying drawings wherein:
According to the invention, in order to increase the data rate of a system bus without making modifications to existing devices connected to the bus, a new logical bus is overlaid onto one or more existing physical system buses. Data is driven onto the new logical bus on the clock edge that is opposite to the clock edge currently being used for the buses. That is, where the buses are driven from the rising edge of the system clock, the new overlaid logical bus is driven onto the buses on the falling edge of the system clock. Consequently, the logical bus is overlaid on the group of existing physical buses by interleaving the data of the logical bus in a TDM manner. In this way, slower legacy devices are still supported because they latch data on only one edge of the system clock, while new devices are supported because they can latch data on either edge of the clock. The new devices can be configured to latch data from the bus on the clock edge opposite to that of the legacy devices. Furthermore, since the logical bus is overlaid on all existing physical buses, a new device (e.g. linecard) can replace a legacy device at any location (e.g. card slot) in the system.
As noted earlier, the invention encompasses further UCS devices (linecards) which are configureable to latch data from the bus responsive to either edge of the bus clock, and/or configuring the UCS device to be able to latch data from the bus responsive to a particular one of the two edges of the bus clock. There may be a plurality of UCS devices of the same type as the first device replacing one of a plurality of the devices the same type as the second, third or fourth device. The bus drivers are operable to drive data into the bus responsive to both edges of the bus clock, and coupling further comprises decoupling, from the bus an existing bus driver that is operable to drive the data into the bus only in and in response to the one edge of the bus clock.
Advantages of the Invention Over the Closest Prior Art Solution:
Thus, the invention provides a method and apparatus overlaying a logical bus onto one or more existing physical buses in a TDM manner. The overlaying is done by transmitting data into one or more of the existing buses on a previously unused phase of the bus clock, thereby having no effect on existing devices connected to the buses. Bus devices that are capable of latching data on either phase of the bus clock are provided to interwork with the overlaid bus. Thus, the system provides a method of upgrading a system bus to increase the data rate as well as an electronic system having an overlaid bus applied thereto.
While the invention has been described in relation to preferred embodiments of the invention, it will be appreciated that other embodiments, adaptations and modifications of the invention will be apparent to those skilled in the art.
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|U.S. Classification||713/600, 713/500|
|International Classification||G06F13/40, G06F13/42, G06F1/04, G06F3/00|
|Cooperative Classification||G06F13/423, G06F13/4072|
|European Classification||G06F13/42C2S, G06F13/40E2B|
|Dec 3, 2002||AS||Assignment|
Owner name: ALCATEL CANADA INC., CANADA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MARGERM, STEVEN DOUGLAS;HAWES, DARWIN NOEL;REEL/FRAME:013564/0031
Effective date: 20021126
|Nov 19, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Jan 30, 2013||AS||Assignment|
Effective date: 20130130
Owner name: CREDIT SUISSE AG, NEW YORK
Free format text: SECURITY INTEREST;ASSIGNOR:ALCATEL-LUCENT CANADA INC.;REEL/FRAME:029826/0927
|Nov 15, 2013||FPAY||Fee payment|
Year of fee payment: 8
|Sep 4, 2014||AS||Assignment|
Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:CREDIT SUISSE AG;REEL/FRAME:033686/0798
Effective date: 20140819
Owner name: ALCATEL-LUCENT CANADA INC., CANADA