|Publication number||US7062734 B2|
|Application number||US 10/319,018|
|Publication date||Jun 13, 2006|
|Filing date||Dec 12, 2002|
|Priority date||Apr 5, 2002|
|Also published as||US20030192020|
|Publication number||10319018, 319018, US 7062734 B2, US 7062734B2, US-B2-7062734, US7062734 B2, US7062734B2|
|Inventors||Truman Wesley Collins, Jr.|
|Original Assignee||Collins Jr Truman Wesley|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Non-Patent Citations (1), Referenced by (3), Classifications (4), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent application claims priority to U.S. Provisional Patent Application No. 60/370,805, filed on Apr. 5, 2002, and entitled “SLACK TIME ANALYSIS ON A CIRCUIT DESIGN”, which is incorporated herein by reference.
The invention relates to methods of deriving timing information for circuits, and more particularly to deriving slack times in circuits comprising latches.
Flip-flops and latches are common elements of circuits. A flip-flop receives a data signal on an input data terminal. The input data terminal is typically denoted by the symbol D. Upon receiving a clock signal on a clock terminal, the flip-flop stores (latches) the data signal and provides the data signal on an output data terminal. The clock terminal is typically denoted by the symbol CK, and the output data terminal is typically denoted by the symbol Q. The data signal is latched upon the occurrence of an edge of the clock signal. Herein, the terms “terminal” and “pin” may be considered interchangeable.
A latch operates in a manner similar to a flip-flop, except that the latch is “open” during substantially the entire interval while the clock signal is asserted. In other words, for a latch, the signal propagates from D through the latch to Q during substantially the entire time while the clock signal is asserted. When the clock signal is no longer asserted, the latch “closes”, e.g. the signal from D is no longer propagated to Q. The Q terminal retains the value of the signal at D when the latch closed.
After the clock signal arrives at CK, the data signal must remain stable for the hold time in order for the data signal to be properly latched. This is true for both flip-flops and latches. Another consideration is the period of time during which the data signal must be stable before the clock signal arrives at CK. This is referred to as the setup time. The data signal must arrive at D and be stable there for a period of time equal to or exceeding the setup time in order for the data signal to be properly latched. Both flip-flops and latches are characterized by setup times.
For a flip-flop, the triggering edge of the clock signal is the clock signal edge that causes the flip-flop to latch the data signal. The triggering edge may be either the rising or falling edge of the clock signal. For a latch, the edge of the clock signal that causes the latch to open is referred to as the opening edge of the latch. The edge of the clock signal that causes the latch to close is referred to as the closing edge of the latch. The rising edge of the clock signal may serve as either the opening or closing edge of a latch. Likewise, the falling edge of the clock signal may serve as either the opening or closing edge of a latch.
Flip-flops and latches are clocked devices typically employed as sequential circuit elements. The timing of their operation is controlled by the timing of the clock signal. Non-clocked devices are also typically found in circuits. Such devices operate independently of a clock signal, and may be referred to collectively as “combinational” circuit elements. Examples of combinational elements include logic gates (AND, OR, inverter, NOR, NAND, etc. gates). Both clocked and combinational circuit elements have an associated propagation delay. The propagation delay of flip-flops and latches is the time that it takes the data signal to propagate from D to Q, once the clock signal is received at CK. The propagation delay of combinational elements, and collections thereof, is the time it takes for changes in the data signal(s) to the combinational elements to be reflected at the output(s) of the combinational elements.
A circuit element may be characterized by different propagation delays for high-low (falling) and low-high (rising) signal transitions. For example, an AND gate in a circuit may be characterized by a first input-to-output propagation delay for rising input signals, and second input-to-output propagation delay for falling input signals.
The propagation delay of a flip-flop is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal after the clock signal arrives at the CK terminal. This propagation delay may be referred to as the CK-Q delay of the flip-flop.
One propagation delay of a latch is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal after the opening clock edge arrives at the CK terminal. This propagation delay may be referred to as the CK-Q delay of the latch. The CK-Q delay of the latch may be employed in situations where the data signal arrives at the D terminal of a closed latch. Another propagation delay of a latch is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal when the data signal arrives at the D terminal of an open latch. This propagation delay may be referred to as the D-Q delay of the latch.
An important consideration for circuit designers is the tolerance for signal delays inherent in a circuit design. For example, in a circuit including a latch, it may be important for the circuit designer to know that the data signal arrives at D of the latch within the setup time of the latch, with five nanoseconds to spare. This spare time may be referred to as the “slack time” of the latch in the circuit in question. Among other things, the slack time for an element tells the designer whether the circuit design can tolerate additional delays in the data signal prior to the element. Where the slack time for an element is substantial, it may be possible for the circuit designer to insert additional or slower combinational logic before (“upstream” from) the element, or to rearrange the circuit design so that the slack time of the element is reduced by shifting the benefit of the slack time to parts of the design that come after (“downstream” from) the element. Herein, the term “upstream”, in relation to a circuit element, refers to points in a circuit that a signal of interest reaches before it reaches the element. “Downstream” refers to points in the circuit that the signal reaches after it reaches the element.
A slack time may be positive, indicating that there is some spare time built into the timing. A slack time may also be negative, indicating that signals do not propagate in sufficient time to meet the timing requirements of the circuit.
Existing approaches to determining the slack time for latches have involved attempts to balance the slack time of the latch with the slack time of the next clocked element downstream from the latch. These approaches have proven problematic and have led to complex implementation code, misleading or unexpected slack times at points in the circuit, and confusing slack time reports.
Slack times at an input of a latch in a circuit design are determined by determining a set of required times at the input of the latch, where the set of required times includes a required time entry for each different relationship between a signal comprising a downstream reference event and a clock signal for the latch. A set of arrival time entries at the input of the latch is also determined, each arrival time entry having a corresponding required time entry. The required times are propagated upstream from a final event of interest to a source event of interest. The arrival times are propagated downstream from the source event of interest to the final event of interest.
Slack path analysis on the circuit design is performed by organizing starting points of paths through the circuit design into a queue. Slack times are determined at the points, and the queue is ordered according to the slack times. A path having a lowest slack time is removed from the top of the queue. When the path is not complete, it is extended and a slack time is determined at a new end point of the path. The path is replaced at a location in the queue such that the queue remains ordered.
With reference to the circuit embodiment 100 of
With respect to signal S, the first flip-flop 102 is upstream from the second flip-flop 108. The first flip-flop 102 may be referred to as the “source” flip-flop, and the second flip-flop 108 may be referred to as the “destination” flip-flop. With reference to
Signal S then propagates from C to D, arriving at D after the propagation delay P2 of logic 104. Upon reaching point D, the signal S propagates to F after incurring the propagation delay P3 of the latch 107. The delay P3 to apply is either the CK-Q delay of the latch 107 (if the signal S arrives at D before the occurrence of clock signal C2 at E, e.g. when the latch 107 is closed), or else the delay is the D-Q delay if the signal S arrives at D after the clock signal C2, e.g. after the latch 107 opens. Signal S then propagates from F to G, arriving at G after the propagation delay P4 of the logic 106.
The propagation delays P1, P2, P3, and P4 may all vary according to whether or not the propagating event is a rising or falling edge of the signal S.
Consider the situation where P1=0, P2=2 nanoseconds, P3=0, and P4=3 nanoseconds. Assume that the timing of the circuit requires that occurrence of edge C1 corresponds with the occurrence of edge C3. That is, a signal S that is propagated from point A (the input of the source flip-flop 102) upon the occurrence of edge C1 at time t=0 and must arrive at point G (the input of the destination flip-flop 108) prior to the occurrence of the edge C3 at time t=14. For purposes of simplifying the present discussion, the setup times for the latch 107 and the flip-flop 108 are ignored. At the occurrence of edge C1 (t=0), S begins to propagate downstream from A. Signal S can arrive at point D at any time prior or during the open interval of the latch 107 at t=5 and t=15 and still make it to point G before the occurrence of edge C3. Between times t=5 and t=15, the latch 107 is open and the signal S propagates through the latch 107. In the present example, signal S arrives at point D at t=2 and hits a red light until the occurrence of edge C2 at time t=5. At the occurrence of edge C2, the signal S propagates through the latch and arrives at point G at time t=8. The slack time at point G is the difference between when S actually arrives at point G, and the latest time S could have arrived at point G and still met the timing of the circuit. Thus the slack time at point G is:
Working backwards it is possible to determine the slack times at other points in the circuit. The slack time at F is
The slack time at the clock terminal E of the latch 107 is
(14−3)−5=6 nanoseconds (the CK-Q delay of the latch is assumed to be 0).
The slack time at the input terminal D of the latch 107 is
15−2=13, for reasons set forth in the following description.
A “path” is a set of related events at different points in a circuit. The points in a path are related by a common signal that passes through them without stopping. If a signal gets to a latch when it is closed, that path stops there. A new path starts at the enable pin when the latch opens. The slack time of a path is the slack time at the end of the path (the slack time as determined for the path at the final point in the path). Paths provide useful information about circuit timing behavior, including slack times at points in the circuit. To determine the slack times at points along a path, an event of interest is selected at the end point of the path. This event is referred to herein as the “final event of interest”. In the preceding example, the final event of interest is the occurrence of the edge C3 at the flip-flop 108. At the start of the path, an event of interest is determined corresponding to the final event of interest. This corresponding event of interest is referred to herein as the “starting event of interest”. In the preceding example, the starting event of interest is the occurrence of edge C1. For a specific path, the slack time will be the same at all the points.
Typically, the interval of time between the starting event of interest and the final event of interest bears upon the slack times at points along the path connecting the events. Thus, for events based upon periodic signals, it is important to examine all possible timing relationships between events comprised by the signals. In one embodiment, two periodic signals comprising the events of interest are “walked” in time to identify all possible relationships between the edges of the signals. For example, if the starting event of interest is a rising edge of a first clock signal, the first clock signal is traversed in time and each rising edge is examined against the corresponding (following most closely in time) rising edge of the second clock signal comprising the final event of interest. Each different timing relationship between the edges is recorded for purposes of determining slack times along the path between the events, when latches are involved. In a path without latches, only the timing relationship with the shortest time in between events is recorded, because that represents the worst slack time.
Consider the pair of signal embodiments represented in
A more complicated situation arises when, as in the circuit embodiment 100 of
Consider the situation where the final event of interest is a rising (trigger) edge of Clock3, the clock signal to the destination flip-flop 108. The signal Clock3 is periodic. The rising edge selected as the final event of interest has a required time. During back propagation of this required time, the latch 107 is encountered between points D and F in the path. Recall that the latch 107 propagates the signal S from point D to point F during the interval when the latch clock signal, e.g. Clock2, is high. The required time for the signal S to reach point D (the D input terminal of the latch 107) occurs some time before the falling (closing) edge of Clock2 corresponding to the rising (trigger) edge of Clock3 that was selected as the final event of interest. A process known as “ping-pong” may be employed to identify an edge to reference this required time to.
This process is illustrated in flow chart form in
When there are multiple relationships between the edges of Clock2 and Clock3, the two signals are walked using the process described previously in conjunction with
With reference to
The required time at C is recorded as TRC1, e.g. the required time for signal S at point C in the circuit. In practical applications, the setup time of the flip-flop FF2 is factored into TRC1, so that for example if the flip-flop FF2 has a 1 nanosecond setup time, TRC1 is −1, e.g. 1 nanosecond sooner than the arrival of C4. Working backward along the path, latch L2 is encountered. Latch L2 is clocked by signal Clock3.
Referring to the signals Clock3 and Clock4, edge E9 of Clock3 corresponds to (is the closest preceding edge in time) edge E13 of Clock4. In other words, if edge E13 is used to clock the flip-flop FF2, then edge E9 is presumed to be the edge that will open the preceding latch L2. Edge E10 of Clock3 corresponds to edge E14 of Clock4. The other edges of Clock3 and Clock4 have the same relationship (e.g. the same relative timing) as edges E9/E13 and E10/E14. Thus, the signals Clock3 and Clock4 have two possible relationships. The “virtual period” of the two clock signals Clock4 and Clock3 is determined as the least common multiple of the clock periods of the two signals. In this case, the virtual period is 60.
Referring back to
A second required time entry TRB2 is recorded for point B. Using the ping-pong approach, a reference event, in this case E14, is associated with this required time relative to E14. The interval <E10, E14> is also associated with the required time and like the required time is made relative to the reference event. The interval, as one will recall from
The set of reference edges at a point in a path may be referred to as a “virtual clock edge list” at the point in the path.
As the preceding example illustrates, in one embodiment of a method to determine slack times of a circuit, the reference event for required times at a point preceding a latch is a closing edge of the latch clock signal when the latch closes prior to the occurrence of the corresponding downstream event.
Next, required times are determined for point A, based upon the required times determined for point B. The latch L1 is clocked by signal Clock2. The edges of Clock2 have four possible relationships with the set of reference signals determined at point B. The required times associated with the reference edges E5′, E6′, E7′, and E8′ are the ones that would have been originally from edges E13, E14, E15, and E16 respectively. The virtual period of the signals comprising the reference edges at point B is 60. The required time TRB1 at point B is referenced to the edge E9′ of signal Clock3. A required time TRA1 at point A, corresponding to the required time TRB1 at point B, is determined by adjusting the required time TRB1 to be relative to the reference edge at point A. Edge E5′ is chosen as the reference edge at point A using the ping-pong approach. Thus if the required time TRB1 at E9′ is 1, the required time TRA1 at E5′ is 3, because E9′ occurs at 24, two nanoseconds later than E5′ at 22. An interval <E9,E5′> is associated with TRA1, representing the composite (overlap) of the latch open intervals <E9,E9′> and <E5,E5′>. (e.g. the overlap of the open intervals of all latches downstream from point A along the path). Actual delays in the circuit are taken into account in adjusting the latch open interval <E9,E9′> before finding the overlap with interval <E5,E5′>(this simplified example ignores the delays). Also, both of the intervals are made relative to the new reference edge E5′ before determining the overlap. The purpose of the composite open interval will be covered more fully in the determination of slack times.
Likewise, a required time TRA2 is recorded at point A, corresponding to the required time TRB1 plus one virtual period of the signals comprising the reference edges at point B. One virtual period (60) was added to the reference edge E9′ to determine the corresponding reference edge E11′ from the next virtual period of Clock3. Using the ping-pong approach, the reference event is set to E7′. A composite open interval <E11,E7′> is associated with TRA2, representing the overlap of the latch open intervals <E11,E11′> and <E7,E7′>. Adjustments for circuit delay are made in the manner described above. The intervals are made relative to the same reference edge, as described above.
The required time TRA3 at point A represents a third relationship between the edges of Clock2 and Clock3. Applying the ping-pong approach to the reference edge E14 for TRB2, the reference event for TRA3 is set to E6′. There is no interval of time during which the open intervals <E10,E10′> and <E6,E6′> overlap (assume for the purpose of this description that this is true, even after adjusting for circuit delay and making the intervals relative to E6′). Thus the composite open interval is set to undefined (!).
A fourth required time TRA4 is recorded at point A, corresponding to the required time TRB3 plus one virtual period of the signals comprising the reference events at point B. Applying the ping-pong approach to edge E16 (E14 plus one virtual period), the reference event for TRA4 is determined to be E8′. A composite open interval <E12,E8′> is associated with TRA4, representing the overlap of the latch open intervals <E12,E12′> and <E8,E8′>. Again, circuit delays are ignored, and the intervals are made relative to E8′ in determining the overlap.
Eventually, the source flip-flop FF1 or other origination point of the path is reached. The signal Clock1 is the clock signal for flip-flop FF1. For each required time at point A, a corresponding arrival time is determined at point X, where Clock1 is received. Where the edges of the signal Clock1 have multiple relationships with the virtual clock edge list, a particular required time entry at point A may give rise to multiple arrival time entries at point X. Edges of Clock1 are chosen that immediately precede each of the required times. In this manner, each back propagated required time and event of interest is associated with a source event of interest at the starting point of the path. Each required time is associated with one or more starting events of interest. If the number of starting events of interest is greater than one, then the relationship of one or more virtual periods is different with respect to the source clock.
The source events of interest identified in this fashion may then be propagated downstream along the path. Any uncertainty in the arrival time of a source event at point X is accounted for as an interval (T1, T2) of potential arrival times for the source event, where T1 is the earliest possible arrival time for the event, and T2 is the latest possible arrival time for the event.
Arrival times for the source events of interest at various points downstream are determined by adding propagation delays of the elements encountered by the events as they propagate downstream. Each element can have a minimum and maximum propagation delay. The arrival ranges are “widened” according to the maximum propagation delay of the elements encountered. To widen a range, T1 is increased by the minimum propagation delay of the element, and T2 is increased by the maximum propagation delay of the element.
When a latch is encountered during propagation of arrival times downstream, entries may be merged to determine the arrival time entries at the next downstream point after the latch. Referring to
The interval (T1 AB1, T2 AB1) is widened according to the minimum and maximum propagation delays of the latch L1. The interval (T1 AB1, T2 AB1) is “clipped” according to the relevant open interval of the latch L1. Clipping involves finding the overlap of the two intervals. When the reference event is edge E9′, the corresponding open interval of latch L1 is <E5,E5′>. When the reference event is edge E14, the corresponding open interval of latch L1 is <E6,E6′>.
Likewise, the two arrival time entries (T1 AA3, T2 AA3, E6′) and (T1 AA4, T2 AA4, E8′) at point A are merged and adjusted to create the arrival time entry at point B, (T1 AB2, T2 AB2, E14).
A situation may arise where the arrival interval and the open interval of the latch do not overlap. If the arrival interval ends before the open interval begins, the signal S always hits a red light at the latch. In this case, the path from point X is ended at point A, and a new path is started from point Y. The source events of interest for this new path are the edges of the clock signal Clock2.
If the arrival interval begins before the open interval begins, but ends during or after the open interval, the signal S may hit a red light at the latch. In this case, the path from point X is ended at point A, and an identical path from point X is continued on through the latch (using the CK-Q propagation delay of the latch). Another path is started from point Y. The source events of interest for this new path are the edges of the clock signal Clock2. Slack times for the path ending at A are determined relative to the closing edge of the latch clock, providing a slack value that is relevant for the path up to that latch but not beyond.
In one embodiment, arrival entries will be recorded at X only for those edges of Clock2 resulting in red-light conditions at point A. For example, if there are 6 different clock relationships between the latch clock and the clocks comprising the reference events at a latch, if only on the fifth relationship involves a red-light situation, then an arrival entry and a path from the latch clock terminal to the latch output terminal will be produced only for that fifth relationship. In other words, for each reference event at the data terminal of a latch, a decision is made as to whether or not to begin a new path at the clock terminal of the latch. If an arrival entry gives rise to a red light situation, paths are started from the clock terminal of the latch and proceeding downstream through the design for each arrival at the latch clock terminal that gives rise to a red light situation. Other arrivals at the clock terminal do not give rise to new paths.
A “period offset” may be included with the arrival entries. The period offset associated with an arrival entry indicates which period of the virtual clock for the reference event comprised by the arrival entry had the earliest arrival time. When arrival entries are merged into a parent entry upon crossing a latch, the period offset indicates from which virtual period of the reference event the red-light situation arose. The period offset is increased appropriately when merging arrival entries. When a path is started at a latch clock terminal, the period offsets there are set based on the period offsets of the arrival entries at the latch data terminal that gave rise to the red light condition. The period offset is used when a path is started at the clock pin of a latch to begin the path an appropriate number of iterations of the virtual period out to correspond with the red light arrival.
When the arrival interval falls completely within the open interval of the latch, the path from point X is ended at point A, and an identical path from point X is continued on through the latch (using the D-Q propagation delay of the latch).
If the arrival interval begins after the open interval ends, the signal S never gets through the latch on time to meet the timing requirements of the circuit. In this case, the path from point X is ended at point A, and the timing failure is recorded.
In this case a new path may be started at the output terminal of the latch. The circuit designer may examine this path to ascertain what would be the worst case slack from the latch output terminal to the final event of interest.
In one embodiment, each arrival entry may also comprise a minimum late value and a maximum early value. These values may be applied to ascertain when to start a path at the latch clock terminal or the latch output terminal in situations where multiple signals merge coming to the input terminal of the latch.
Returning to the example of
Another situation that can occur is where two or more paths merge at a circuit element. Referring to
Once required and arrival times are determined for all paths through the circuit, a list of paths having the worst-case slack times for a given point may be reported.
At 1204 slack times are determined at each starting point according to the required time and arrival time entries. When a path is started, an arrival time for each possible clock relationship is carried from the source clock all the way through the pipeline of latches. Each of these arrivals is updated appropriately as the path is extended. Each arrival can be compared with a required time at the current end point of the path by an appropriate adjustment. By examining each arrival as it passes through a latch, it can be determined whether or not the late value will pass through the latch. If so, the path continues. If not, the path is left undefined. The worst-case of the slack times determined in this fashion is the slack time of the path.
Once slack times for all points are determined, the queue is ordered at 1206 according to slack time. Alternatively, the queue could be “self-ordering”, so that as paths are added, the queue reorders itself so that it is always ordered according to the slack time of its constituent paths. The path with the lowest (worst-case) slack time is placed at the head of the queue. The slack time of paths increases from the head of the path queue to the tail of the path queue.
At 1208 the path at the head of the path queue (the path having the worst slack time) is removed from the path queue. A check is made to determine if this path is a complete path, e.g. if it has been extended to its ending point. If so, the path is “reported” by moving it to the report queue at 1210. This report queue is provided to the circuit designer and is self-ordering; that is, the first path moved to the report queue has the worst slack, the next path moved to the report queue has the second worst slack, and so on. Processing may stop once a number of worst case slack paths, as specified by the circuit designer, are reported.
If, at 1214, extending a path would result in “fan out”, the path is cloned at 1216 to create one or more new paths proportional to the amount of fan-out.
As paths are extended, the arrival ranges are adjusted according to the actual slew times of the signals. At the data terminal of a latch, each arrival range is examined to determine if the latest arrival time for the range falls within the open interval of the latch. If it does, the path is extended though the latch. Otherwise, the path is left undefined.
Referring again to
With reference to
With reference to
The apparatus 1500 may comprise additional storage (removable 1506 and/or non-removable 1507) such as magnetic or optical disks or tape. The apparatus 1500 may further comprise input devices 1510 such as a keyboard, pointing device, microphone, etc., and/or output devices 1512 such as display, speaker, and printer. The apparatus 1500 may also typically include network connections 1520 (such as a network adapter) for coupling to other devices, computers, networks, servers, etc. using either wired or wireless signaling media.
The components of the device may be embodied in a distributed computing system. For example, a terminal device may incorporate input and output devices to present only the user interface, whereas processing component of the system are resident elsewhere. Likewise, processing functionality may be distributed across a plurality of processors.
The apparatus may generate and receive machine readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. This can include both digital, analog, and optical signals. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Communications media, including combinations of any of the above, should be understood as within the scope of machine readable media.
Particular embodiments of a method and apparatus to perform slack analysis on a circuit design have been described herein. Many alternative embodiments will now become apparent to those skilled in the art. It should be recognized that the described embodiments are illustrative only and should not be taken as limiting in scope. Rather, the present invention encompasses all such embodiments as may come within the scope and spirit of the following claims and equivalents thereto.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4763289 *||Dec 31, 1985||Aug 9, 1988||International Business Machines Corporation||Method for the modeling and fault simulation of complementary metal oxide semiconductor circuits|
|US5218551 *||Apr 30, 1990||Jun 8, 1993||International Business Machines Corporation||Timing driven placement|
|US5365463 *||Dec 21, 1990||Nov 15, 1994||International Business Machines Corporation||Method for evaluating the timing of digital machines with statistical variability in their delays|
|US5404360 *||Mar 6, 1992||Apr 4, 1995||Mitsubishi Denki Kabushiki Kaisha||Simulator for simulating circuit operation|
|US5740347 *||May 1, 1995||Apr 14, 1998||Synopsys, Inc.||Circuit analyzer of black, gray and transparent elements|
|US5790830 *||Dec 29, 1995||Aug 4, 1998||Synopsys, Incorporated||Extracting accurate and efficient timing models of latch-based designs|
|US5864487 *||Nov 19, 1996||Jan 26, 1999||Unisys Corporation||Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool|
|US5894419 *||Apr 21, 1997||Apr 13, 1999||International Business Machines Corporation||System and method for robust clocking schemes for logic circuits|
|US6158022 *||Apr 13, 1998||Dec 5, 2000||Synopsys, Inc.||Circuit analyzer of black, gray and transparent elements|
|US6185723 *||Nov 27, 1996||Feb 6, 2001||International Business Machines Corporation||Method for performing timing analysis of a clock-shaping circuit|
|US6401231||Apr 25, 1997||Jun 4, 2002||Cadence Design Systems, Inc.||Method and apparatus for performing both negative and positive slack time budgeting and for determining a definite required constraint during integrated circuit design|
|US6438731 *||Sep 13, 1999||Aug 20, 2002||Synopsys, Inc.||Integrated circuit models having associated timing exception information therewith for use in circuit design optimizations|
|US6442739 *||Dec 17, 1998||Aug 27, 2002||Cadence Design Systems, Inc.||System and method for timing abstraction of digital logic circuits|
|US6496972 *||Sep 13, 1999||Dec 17, 2002||Synopsys, Inc.||Method and system for circuit design top level and block optimization|
|US6604227 *||Aug 10, 2001||Aug 5, 2003||Hewlett-Packard Development Company, L.P.||Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools|
|US6611948 *||Aug 10, 2001||Aug 26, 2003||Hewlett-Packard Development Company, L.P.||Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model|
|US6678644 *||Sep 13, 1999||Jan 13, 2004||Synopsys, Inc.||Integrated circuit models having associated timing exception information therewith for use with electronic design automation|
|1||IBM(R) website, www.http://houns54.clearlake.ibm.com, "EinsTimer: Timing Analysis", 2003.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7239996||May 28, 2003||Jul 3, 2007||Boland Arthur J||Causality based event driven timing analysis engine|
|US7873953 *||Mar 20, 2006||Jan 18, 2011||Altera Corporation||High-level language code sequence optimization for implementing programmable chip designs|
|US8578356||Dec 13, 2010||Nov 5, 2013||Altera Corporation||High-level language code sequence optimization for implementing programmable chip designs|
|Dec 12, 2002||AS||Assignment|
Owner name: MENTOR GRAPHICS CORPORATION, OREGON
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:COLLINS, TRUMAN WESLEY JR.;REEL/FRAME:013585/0464
Effective date: 20021127
|Nov 20, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Nov 13, 2012||CC||Certificate of correction|
|Nov 26, 2013||FPAY||Fee payment|
Year of fee payment: 8