US 7062734 B2 Abstract Slack times at an input of a latch in a circuit design are determined by determining a set of required times at the input of the latch, where the set of required times includes a required time entry for each different relationship between a signal comprising a downstream event and a clock signal for the latch. A set of arrival time entries at the input of the latch is also determined, each arrival time entry having a corresponding required time entry.
Claims(30) 1. A method for determining a slack time for a node in a circuit design comprising:
determining a starting point and an ending point for a path going through at least one latch;
determining a set of required times for each node in the path by working upstream from the ending point,
determining a respective set of arrival times for the one or more nodes in the path by working downstream from the starting point; and
calculating the slack time for the one or more nodes in the path from the respective set of required times and the respective set of arrival times at each respective node,
wherein the required times in the respective set of required times and the arrival times in the respective set of arrival times are associated with different clock relationships between the respective node and a downstream node, the different clock relationships resulting from the respective node and the downstream node being driven by different respective clock signals, at least one of the respective clock signals having a varying pulse width.
2. The method of
3. The method of
4. The method of
taking the difference between a required time and an arrival time for each pair of arrival and required times at a node to create a slack time for each pair, where the required time and the arrival time have a common clock reference;
finding a worst slack time for the node by finding the worst of the slack times for all of the pairs of arrival and required times for the node; and
using the worst slack time of the node as the slack time for the node.
5. The method of
6. The method of
7. The method of
8. The method of
9. The method of
determining a required time for each reference clock edge in the set of reference edges to create the respective set of required times.
10. The method of
11. The method of
12. The method of
13. The method of
14. The method of
15. The method of
16. The method of
17. The method of
18. A method for determining a slack time for a node in a circuit design comprising:
determining on a first computer, a starting point and an ending point for a path going through at least one latch;
transmitting the circuit design, the starting point, and the ending point to a second computer;
on the second computer,
determining a respective set of required times for one or more nodes in the path by working upstream from the ending point, each required time in the respective set of required times being associated with a different clock relationship between the respective node and a downstream node, the different clock relationship resulting from the respective node and the downstream node being driven by different clock signals, at least one of which has a varying pulse width,
determining a respective set of arrival times for the one or more nodes in the path by working downstream from the starting point, each arrival time in the respective set of arrival times being associated with a corresponding one of the different clock relationships, and
calculating the slack time for each node in the path from the respective set of required times and the respective set of arrival times at each node; and transmitting the slack time for each node from the second computer to the first computer.
19. A method for determining a slack time for a node in a circuit design comprising:
determining a starting point and an ending point for a path going through at least one latch and including the node;
calculating all of the different clock relationships from the node to the ending point, wherein the different clock relationships arise from at least two different clock signals, and wherein at least two of the different clock signals have different periods;
determining a reference clock edge for each clock relationship, where the reference clock edge is any edge of the clock at the ending point if the node is the first latch upstream of the ending point, or, if not, the reference clock edge is a specific clock edge relative to a preceding latch in the path;
determining a required time, which is the last possible time a signal can arrive at the node and still make the timing requirements of the circuit, for each reference clock edge and constructing a set of required times corresponding to the set of reference clock edges;
calculating for each node between the node and the ending point an open interval, which is a window of time where, if a signal arrives at the node during the interval, the signal will travel from the node to the ending point without hitting a closed latch;
calculating an arrival interval, which is a time window stretching from the earliest to the latest possible time that a signal can arrive at a given point, at each node, for each clock relationship, along the path from the starting point to the ending point;
calculating the slack time at each node by taking the difference between a required time and an arrival time for each pair of arrival and required times at a respective node to create a slack time for each pair, where the required time and the arrival time have a common clock reference, and
finding a worst slack time for the node by finding the worst of the slack times for all of the pairs of arrival and required times for the node, and using the worst slack time of the node as the slack time for the node.
20. The method of
21. The method of
22. The method of
23. The method of
calculating a period offset, which is an index into a virtual clock indicating which period of the virtual clock the earliest arrival time of the set of arrival times occurs, at each node along the path from the starting point to the ending point, including the node where the slack time will be calculated, taking into consideration the effects of combinational logic along the path.
24. The method of
determining a maximum early arrival time, which is the latest early arrival time from a set of arrival intervals, for each arrival interval set.
25. The method of
determining a minimum late arrival time, which is the earliest late arrival time from a set of arrival intervals, for each arrival interval set.
26. The method of
folding and clipping arrival times as they move through latches.
27. The method of
updating the period offset value when the arrival times are folded.
28. The method of
generating one or more paths at a starting point;
extending the paths downstream; and
reporting the paths that go through latches.
29. The method of
determining whether or not a first path arrives at a latch during the open interval of the latch;
extending the first path to the (Q) pin of the latch if the first path arrived at the (D) pin of the latch during the open interval of the latch; and
generating a second path relative to a specific clock edge starting at the enable pin of the latch if the first path arrives at the (D) pin of the latch before the latch opens.
30. The method of
Description This patent application claims priority to U.S. Provisional Patent Application No. 60/370,805, filed on Apr. 5, 2002, and entitled “SLACK TIME ANALYSIS ON A CIRCUIT DESIGN”, which is incorporated herein by reference. The invention relates to methods of deriving timing information for circuits, and more particularly to deriving slack times in circuits comprising latches. Flip-flops and latches are common elements of circuits. A flip-flop receives a data signal on an input data terminal. The input data terminal is typically denoted by the symbol D. Upon receiving a clock signal on a clock terminal, the flip-flop stores (latches) the data signal and provides the data signal on an output data terminal. The clock terminal is typically denoted by the symbol CK, and the output data terminal is typically denoted by the symbol Q. The data signal is latched upon the occurrence of an edge of the clock signal. Herein, the terms “terminal” and “pin” may be considered interchangeable. A latch operates in a manner similar to a flip-flop, except that the latch is “open” during substantially the entire interval while the clock signal is asserted. In other words, for a latch, the signal propagates from D through the latch to Q during substantially the entire time while the clock signal is asserted. When the clock signal is no longer asserted, the latch “closes”, e.g. the signal from D is no longer propagated to Q. The Q terminal retains the value of the signal at D when the latch closed. After the clock signal arrives at CK, the data signal must remain stable for the hold time in order for the data signal to be properly latched. This is true for both flip-flops and latches. Another consideration is the period of time during which the data signal must be stable before the clock signal arrives at CK. This is referred to as the setup time. The data signal must arrive at D and be stable there for a period of time equal to or exceeding the setup time in order for the data signal to be properly latched. Both flip-flops and latches are characterized by setup times. For a flip-flop, the triggering edge of the clock signal is the clock signal edge that causes the flip-flop to latch the data signal. The triggering edge may be either the rising or falling edge of the clock signal. For a latch, the edge of the clock signal that causes the latch to open is referred to as the opening edge of the latch. The edge of the clock signal that causes the latch to close is referred to as the closing edge of the latch. The rising edge of the clock signal may serve as either the opening or closing edge of a latch. Likewise, the falling edge of the clock signal may serve as either the opening or closing edge of a latch. Flip-flops and latches are clocked devices typically employed as sequential circuit elements. The timing of their operation is controlled by the timing of the clock signal. Non-clocked devices are also typically found in circuits. Such devices operate independently of a clock signal, and may be referred to collectively as “combinational” circuit elements. Examples of combinational elements include logic gates (AND, OR, inverter, NOR, NAND, etc. gates). Both clocked and combinational circuit elements have an associated propagation delay. The propagation delay of flip-flops and latches is the time that it takes the data signal to propagate from D to Q, once the clock signal is received at CK. The propagation delay of combinational elements, and collections thereof, is the time it takes for changes in the data signal(s) to the combinational elements to be reflected at the output(s) of the combinational elements. A circuit element may be characterized by different propagation delays for high-low (falling) and low-high (rising) signal transitions. For example, an AND gate in a circuit may be characterized by a first input-to-output propagation delay for rising input signals, and second input-to-output propagation delay for falling input signals. The propagation delay of a flip-flop is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal after the clock signal arrives at the CK terminal. This propagation delay may be referred to as the CK-Q delay of the flip-flop. One propagation delay of a latch is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal after the opening clock edge arrives at the CK terminal. This propagation delay may be referred to as the CK-Q delay of the latch. The CK-Q delay of the latch may be employed in situations where the data signal arrives at the D terminal of a closed latch. Another propagation delay of a latch is typically specified in terms of the time it takes a data signal at the D terminal to reach the Q terminal when the data signal arrives at the D terminal of an open latch. This propagation delay may be referred to as the D-Q delay of the latch. An important consideration for circuit designers is the tolerance for signal delays inherent in a circuit design. For example, in a circuit including a latch, it may be important for the circuit designer to know that the data signal arrives at D of the latch within the setup time of the latch, with five nanoseconds to spare. This spare time may be referred to as the “slack time” of the latch in the circuit in question. Among other things, the slack time for an element tells the designer whether the circuit design can tolerate additional delays in the data signal prior to the element. Where the slack time for an element is substantial, it may be possible for the circuit designer to insert additional or slower combinational logic before (“upstream” from) the element, or to rearrange the circuit design so that the slack time of the element is reduced by shifting the benefit of the slack time to parts of the design that come after (“downstream” from) the element. Herein, the term “upstream”, in relation to a circuit element, refers to points in a circuit that a signal of interest reaches before it reaches the element. “Downstream” refers to points in the circuit that the signal reaches after it reaches the element. A slack time may be positive, indicating that there is some spare time built into the timing. A slack time may also be negative, indicating that signals do not propagate in sufficient time to meet the timing requirements of the circuit. Existing approaches to determining the slack time for latches have involved attempts to balance the slack time of the latch with the slack time of the next clocked element downstream from the latch. These approaches have proven problematic and have led to complex implementation code, misleading or unexpected slack times at points in the circuit, and confusing slack time reports. Slack times at an input of a latch in a circuit design are determined by determining a set of required times at the input of the latch, where the set of required times includes a required time entry for each different relationship between a signal comprising a downstream reference event and a clock signal for the latch. A set of arrival time entries at the input of the latch is also determined, each arrival time entry having a corresponding required time entry. The required times are propagated upstream from a final event of interest to a source event of interest. The arrival times are propagated downstream from the source event of interest to the final event of interest. Slack path analysis on the circuit design is performed by organizing starting points of paths through the circuit design into a queue. Slack times are determined at the points, and the queue is ordered according to the slack times. A path having a lowest slack time is removed from the top of the queue. When the path is not complete, it is extended and a slack time is determined at a new end point of the path. The path is replaced at a location in the queue such that the queue remains ordered. With reference to the circuit embodiment With respect to signal S, the first flip-flop Signal S then propagates from C to D, arriving at D after the propagation delay P The propagation delays P Consider the situation where P Working backwards it is possible to determine the slack times at other points in the circuit. The slack time at F is
The slack time at the clock terminal E of the latch A “path” is a set of related events at different points in a circuit. The points in a path are related by a common signal that passes through them without stopping. If a signal gets to a latch when it is closed, that path stops there. A new path starts at the enable pin when the latch opens. The slack time of a path is the slack time at the end of the path (the slack time as determined for the path at the final point in the path). Paths provide useful information about circuit timing behavior, including slack times at points in the circuit. To determine the slack times at points along a path, an event of interest is selected at the end point of the path. This event is referred to herein as the “final event of interest”. In the preceding example, the final event of interest is the occurrence of the edge C Typically, the interval of time between the starting event of interest and the final event of interest bears upon the slack times at points along the path connecting the events. Thus, for events based upon periodic signals, it is important to examine all possible timing relationships between events comprised by the signals. In one embodiment, two periodic signals comprising the events of interest are “walked” in time to identify all possible relationships between the edges of the signals. For example, if the starting event of interest is a rising edge of a first clock signal, the first clock signal is traversed in time and each rising edge is examined against the corresponding (following most closely in time) rising edge of the second clock signal comprising the final event of interest. Each different timing relationship between the edges is recorded for purposes of determining slack times along the path between the events, when latches are involved. In a path without latches, only the timing relationship with the shortest time in between events is recorded, because that represents the worst slack time. Consider the pair of signal embodiments represented in A more complicated situation arises when, as in the circuit embodiment 100 of Consider the situation where the final event of interest is a rising (trigger) edge of Clock This process is illustrated in flow chart form in When there are multiple relationships between the edges of Clock With reference to The required time at C is recorded as T Referring to the signals Clock Referring back to A second required time entry T The set of reference edges at a point in a path may be referred to as a “virtual clock edge list” at the point in the path. As the preceding example illustrates, in one embodiment of a method to determine slack times of a circuit, the reference event for required times at a point preceding a latch is a closing edge of the latch clock signal when the latch closes prior to the occurrence of the corresponding downstream event. Next, required times are determined for point A, based upon the required times determined for point B. The latch L Likewise, a required time T The required time T A fourth required time T Eventually, the source flip-flop FF The source events of interest identified in this fashion may then be propagated downstream along the path. Any uncertainty in the arrival time of a source event at point X is accounted for as an interval (T Arrival times for the source events of interest at various points downstream are determined by adding propagation delays of the elements encountered by the events as they propagate downstream. Each element can have a minimum and maximum propagation delay. The arrival ranges are “widened” according to the maximum propagation delay of the elements encountered. To widen a range, T When a latch is encountered during propagation of arrival times downstream, entries may be merged to determine the arrival time entries at the next downstream point after the latch. Referring to The interval (T Likewise, the two arrival time entries (T A situation may arise where the arrival interval and the open interval of the latch do not overlap. If the arrival interval ends before the open interval begins, the signal S always hits a red light at the latch. In this case, the path from point X is ended at point A, and a new path is started from point Y. The source events of interest for this new path are the edges of the clock signal Clock If the arrival interval begins before the open interval begins, but ends during or after the open interval, the signal S may hit a red light at the latch. In this case, the path from point X is ended at point A, and an identical path from point X is continued on through the latch (using the CK-Q propagation delay of the latch). Another path is started from point Y. The source events of interest for this new path are the edges of the clock signal Clock In one embodiment, arrival entries will be recorded at X only for those edges of Clock A “period offset” may be included with the arrival entries. The period offset associated with an arrival entry indicates which period of the virtual clock for the reference event comprised by the arrival entry had the earliest arrival time. When arrival entries are merged into a parent entry upon crossing a latch, the period offset indicates from which virtual period of the reference event the red-light situation arose. The period offset is increased appropriately when merging arrival entries. When a path is started at a latch clock terminal, the period offsets there are set based on the period offsets of the arrival entries at the latch data terminal that gave rise to the red light condition. The period offset is used when a path is started at the clock pin of a latch to begin the path an appropriate number of iterations of the virtual period out to correspond with the red light arrival. When the arrival interval falls completely within the open interval of the latch, the path from point X is ended at point A, and an identical path from point X is continued on through the latch (using the D-Q propagation delay of the latch). If the arrival interval begins after the open interval ends, the signal S never gets through the latch on time to meet the timing requirements of the circuit. In this case, the path from point X is ended at point A, and the timing failure is recorded. In this case a new path may be started at the output terminal of the latch. The circuit designer may examine this path to ascertain what would be the worst case slack from the latch output terminal to the final event of interest. In one embodiment, each arrival entry may also comprise a minimum late value and a maximum early value. These values may be applied to ascertain when to start a path at the latch clock terminal or the latch output terminal in situations where multiple signals merge coming to the input terminal of the latch. Returning to the example of Another situation that can occur is where two or more paths merge at a circuit element. Referring to Referring to Once required and arrival times are determined for all paths through the circuit, a list of paths having the worst-case slack times for a given point may be reported. At Once slack times for all points are determined, the queue is ordered at At If, at As paths are extended, the arrival ranges are adjusted according to the actual slew times of the signals. At the data terminal of a latch, each arrival range is examined to determine if the latest arrival time for the range falls within the open interval of the latch. If it does, the path is extended though the latch. Otherwise, the path is left undefined. Referring again to With reference to With reference to The apparatus The components of the device may be embodied in a distributed computing system. For example, a terminal device may incorporate input and output devices to present only the user interface, whereas processing component of the system are resident elsewhere. Likewise, processing functionality may be distributed across a plurality of processors. The apparatus may generate and receive machine readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism. The term “modulated data signal” means a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. This can include both digital, analog, and optical signals. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Communications media, including combinations of any of the above, should be understood as within the scope of machine readable media. Particular embodiments of a method and apparatus to perform slack analysis on a circuit design have been described herein. Many alternative embodiments will now become apparent to those skilled in the art. It should be recognized that the described embodiments are illustrative only and should not be taken as limiting in scope. Rather, the present invention encompasses all such embodiments as may come within the scope and spirit of the following claims and equivalents thereto. Patent Citations
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