|Publication number||US7064970 B2|
|Application number||US 10/699,652|
|Publication date||Jun 20, 2006|
|Filing date||Nov 4, 2003|
|Priority date||Nov 4, 2003|
|Also published as||US7149100, US20050105327, US20060126378|
|Publication number||10699652, 699652, US 7064970 B2, US 7064970B2, US-B2-7064970, US7064970 B2, US7064970B2|
|Inventors||Hagop A. Nazarian|
|Original Assignee||Micron Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Non-Patent Citations (4), Referenced by (14), Classifications (27), Legal Events (7)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The invention relates to memory structures utilizing variable resistance states for data storage and to an architecture for such structures incorporating a serial configuration.
Integrated circuit designers have always sought the ideal semiconductor memory: a device that is randomly accessible, can be written or read very quickly, is non-volatile, but indefinitely alterable, and consumes little power. Emerging variable resistance memories increasingly offer these advantages. Programmable Conductance Random Access Memory (PCRAM) is one example of such a memory. Additionally, Magnetoresistive Random Access Memory (MRAM) technology has been increasingly viewed as offering all these advantages. Other types of variable resistance memories include polymer-based memory and chalcogenide-based memory.
A PCRAM element has a structure including a chalcogenide-based glass region incorporating a metal (or metal ions) and electrodes on either side of the glass region. Information can be stored as a digital “1” or “0” as stable resistance states. A typical chalcogenide glass used in PCRAM devices is GexSe100−x. The chalcogenide glass can also be used in conjunction with layers of Ag and/or Ag2Se. An example of a PCRAM device is described in U.S. Pat. No. 6,348,365 to Moore and Gilton. The glass region of a PCRAM element can be made less resistive upon application of a threshold voltage. This less resistive state is maintained in a non- or semi-volatile manner and is reversible by applying a reversed voltage. The resistance state of a PCRAM element can be sensed by the application of a sub-threshold voltage through the cell element.
A magnetic memory element has a structure which includes ferromagnetic layers separated by a non-magnetic barrier layer that forms a tunnel junction. An example of an MRAM device is described in U.S. Pat. No. 6,358,756 to Sandhu et al. Information can be stored as a digital “1” or a “0” as directions of magnetization vectors in these ferromagnetic layers. Magnetic vectors in one ferromagnetic layer are magnetically fixed or pinned, while the magnetic vectors of the other ferromagnetic layer are not fixed so that the magnetization direction is free to switch between “parallel” and “antiparallel” states relative to the pinned layer. In response to parallel and antiparallel states, the magnetic memory element represents two different stable resistance states, which are read by the memory circuit as either a “1” or a “0.” Passing a current through the MRAM cell enables detection of the resistance states.
As mentioned above, polymer memory, another type of variable resistance memory, utilizes a polymer-based layer having ions dispersed therein or, alternatively, the ions may be in an adjacent layer. The polymer memory element is based on polar conductive polymer molecules. The polymer layer and ions are between two electrodes such that upon application of a voltage or electric field the ions migrate toward the negative electrode, thereby changing the resistivity of the memory cell. This altered resistivity can be sensed as a memory state.
Chalcogenide memory, another type of variable resistance memory, switches resitivity states by undergoing a phase change in response to resistive heating. The two phases corresponding to the two stable resistivity states include a polycrystalline state and an amorphous state. The amorphous state is a higher resistive state, which can be read as stored data.
A problem encountered in variable resistance memory array architectures, particularly MRAM, is the generation of sneak paths. Sneak paths during read operations are most prevalent in cross-point array architectures, but exist wherever memory cells are in direct electrical contact with one another through the array. A sneak path is a parasitic path or logic flow within a system which, under certain conditions, can initiate an undesired function or inhibit a desired function. Typically, in variable resistance memory circuits the problem is exhibited when reading data from a desired cell. Other cells in electrical contact with the addressed cell provide alternate routes for current, causing a sneak path and lowering the memory circuit's resistance to potentially unreadable levels.
A typical prior art variable resistance memory array 10, here discussed as an MRAM array, is shown in
The sneak path effect on the addressed MRAM cell 12 of
R sneak =R/m−1 (1)
where R is the combined resistance of memory cells (e.g., 12 a) and m is the total number of wordlines 18 or rows.
It would be advantageous to have a memory array architecture suitable for a variable resistance memory array that could provide similar integration characteristics as a cross-point array architecture, but which would also mitigate the detriments of sneak path occurrence.
The invention relates to an architecture suitable for variable resistance memory that addresses the above-discussed problems of the prior art. The invention mitigates sneak path and associated problems in memory array architectures by limiting the number of memory cells associated with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells connected thereto into one-half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where there may or may not be an equal number of cells (n) on either side of the transistor. The memory array has memory cells, which, for example, may be grouped into 1T-2nCell blocks. “1T-2nCell” indicates that there is an even number (2n) of memory cells per transistor for each block, where n memory cells are on each side of the transistor. The resistance of the sneak path(s) can be calculated and factored into the read operation. The memory array architecture provides a higher resistance sneak path as well as producing less noise and enabling a reasonably high level of integration, which may include multiple memory array layers.
These and other advantages and features of the present invention will be more apparent from the following detailed description and drawings which illustrate various embodiments of the invention.
In the following detailed description, reference is made to various specific embodiments in which the invention may be practiced. These embodiments are described with sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be employed, and that structural and electrical changes may be made without departing from the spirit or scope of the present invention.
This invention relates to a novel array architecture for memory technology, particularly variable resistance memory with low volatility (termed “non-volatile” in the art), requiring little or no refreshing, such as MRAM, PCRAM, polymer memory, and chalcogenide-based memory. It is also possible that the memory array architecture of the invention can be used with other types of memory as well, so long as such memory may benefit from the mitigation of sneak path. Typical memory cell types with which the invention can be utilized are two terminal structures; however, more than two terminals can be used also.
The invention mitigates problems associated with memory array architecture sneak path by limiting the number of memory cells associated (by potential electrical connection) with an addressed cell to a known number having a sneak path resistance that can be calculated and taken into consideration when sensing the addressed memory cell. Blocks of memory cells are associated with access transistors, which separate the memory cells associated with the transistor into one-half (½) sections of cell blocks. The access transistors can be associated with n memory cells, where n is at least 2. The one-half sections need not necessarily be symmetrical or consist of equal numbers of memory cells.
Now referring to the drawings, where like reference numbers designate like components of the invention,
Memory cells 32 of the invention can be MRAM, PCRAM, polymer-based, phase-changing chalcogenide-based, and other non-volatile type memory cells. Such memory cells 32 can be fabricated as is known in the art. Interconnect lines such as wordlines and bit lines can be of materials and can be fabricated as is known in the art. Likewise, transistors used in the invention can be fabricated by processes and with materials as is known in the art.
Now referring to
The addressing and reading operation is also shown in
Now referring to
R sneak =[R/(n−1)]+[R/(m(n−1))] (2)
This formula can be factored into a read operation. As shown by formula 2, the resistance of the sneak path of the array architecture of the invention can be exponentially greater than that of a comparable cross-point array architecture as exemplified by formula (1) above.
The memory controller 902 is also coupled to one or more memory buses 907. Each memory bus 907 accepts memory components 908 which include at least one memory device 100 of the present invention. The memory components 908 may be a memory card or a memory module. Examples of memory modules include single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). The memory components 908 may include one or more additional devices 909. For example, in a SIMM or DIMM, the additional device 909 might be a configuration memory, such as a serial presence detect (SPD) memory. The memory controller 902 may also be coupled to a cache memory 905. The cache memory 905 may be the only cache memory in the processing system. Alternatively, other devices, for example, processors 901 may also include cache memories, which may form a cache hierarchy with cache memory 905. If the processing system 900 includes peripherals or controllers which are bus masters or which support direct memory access (DMA), the memory controller 902 may implement a cache coherency protocol. If the memory controller 902 is coupled to a plurality of memory buses 907, each memory bus 907 may be operated in parallel, or different address ranges may be mapped to different memory buses 907.
The primary bus bridge 903 is coupled to at least one peripheral bus 910. Various devices, such as peripherals or additional bus bridges may be coupled to the peripheral bus 910. These devices may include a storage controller 911, a miscellaneous I/O device 914, a secondary bus bridge 915, a multimedia processor 918, and a legacy device interface 920. The primary bus bridge 903 may also coupled to one or more special purpose high speed ports 922. In a personal computer, for example, the special purpose port might be the Accelerated Graphics Port (AGP), used to couple a high performance video card to the processing system 900.
The storage controller 911 couples one or more storage devices 913, via a storage bus 912, to the peripheral bus 910. For example, the storage controller 911 may be a SCSI controller and storage devices 913 may be SCSI discs. The I/O device 914 may be any sort of peripheral. For example, the I/O device 914 may be a local area network interface, such as an Ethernet card. The secondary bus bridge 915 may be used to interface additional devices via another bus to the processing system. For example, the secondary bus bridge 915 may be an universal serial port (USB) controller used to couple USB devices 917 via to the processing system 900. The multimedia processor 918 may be a sound card, a video capture card, or any other type of media interface, which may also be coupled to one additional devices such as speakers 919. The legacy device interface 920 is used to couple legacy devices, for example, older styled keyboards and mice, to the processing system 900.
The processing system 900 illustrated in
The processes and devices described above are merely illustrative of but a few of the preferred methods and typical devices that could be used and produced in accordance with the invention. The above description and drawings illustrate embodiments, which achieve the objects, features, and advantages of the present invention. However, it is not intended that the present invention be strictly limited to the above-described and illustrated embodiments. Any modifications of the present invention that come within the spirit and scope of the following claims should be considered part of the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6348365||Mar 2, 2001||Feb 19, 2002||Micron Technology, Inc.||PCRAM cell manufacturing|
|US6356477||Jan 29, 2001||Mar 12, 2002||Hewlett Packard Company||Cross point memory array including shared devices for blocking sneak path currents|
|US6358756||Feb 7, 2001||Mar 19, 2002||Micron Technology, Inc.||Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme|
|US6445612 *||Aug 27, 2001||Sep 3, 2002||Motorola, Inc.||MRAM with midpoint generator reference and method for readout|
|US6757189 *||Apr 24, 2003||Jun 29, 2004||Industrial Technology Research Institute||Magnetic random access memory with memory cells of different resistances connected in series and parallel|
|US20010012228||Dec 19, 2000||Aug 9, 2001||Perner Frederick A.||Differential sense amplifiers for resistive cross point memory cell arrays|
|US20020039308||Aug 23, 2001||Apr 4, 2002||Dietmar Gogl||MRAM configuration|
|US20020159317||Apr 30, 2002||Oct 31, 2002||Stefan Lammers||MRAM semiconductor memory configuration with redundant cell arrays|
|US20020176272||May 23, 2001||Nov 28, 2002||International Business Machines Corporation||Select line architecture for magnetic random access memories|
|US20020196647||Jun 22, 2001||Dec 26, 2002||Nickel Janice H.||Resistive cross point array of short-tolerant memory cells|
|US20030058685||Sep 25, 2001||Mar 27, 2003||Tran Lung T.||Read methods for magneto-resistive device having soft reference layer|
|US20040100835 *||Nov 7, 2003||May 27, 2004||Nec Corporation||Magnetic memory cell and magnetic random access memory using the same|
|EP1426966A2 *||Dec 4, 2003||Jun 9, 2004||Sharp Kabushiki Kaisha||Nonvolatile memory cell and nonvolatile semiconductor memory device|
|1||James Daughton, Magnetoresistive Random Access Memory (MRAM), Feb. 24, 2000 (contact Arthur at firstname.lastname@example.org).|
|2||M. Durlam, et al., "A Low Power 1Mbit MRAM based on 1T1MTJ Bit Cell Integrated With Copper Interconnects", 2002 Symposium on VLSI Circuits Digest of Technical Papers; Mar. 2, 2002.|
|3||R. Butner, "Computing Unplugged", http://www.research.ibm.com/thinkresearch/pages/2001/20010202<SUB>-</SUB>mram.shtml; visited Apr. 7, 2003.|
|4||R. Desikan, et al., "On-Chip MRAM as a High-Bandwidth, Low-Latency Replacement for DRAM Physical Memories", Department of Computer Sciences, Tech Report TR-02-47, University of Texas at Austin, Sep. 27, 2002.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7149100 *||Dec 22, 2005||Dec 12, 2006||Micron Technology, Inc.||Serial transistor-cell array architecture|
|US7206216 *||Feb 15, 2005||Apr 17, 2007||Renesas Technology Corp.||Semiconductor device with a non-erasable memory and/or a nonvolatile memory|
|US7269044 *||Apr 22, 2005||Sep 11, 2007||Micron Technology, Inc.||Method and apparatus for accessing a memory array|
|US7385838||Mar 9, 2007||Jun 10, 2008||Renesas Technology Corp.||Semiconductor device with a non-erasable memory and/or a nonvolatile memory|
|US7718533||May 8, 2007||May 18, 2010||Micron Technology, Inc.||Inverted variable resistance memory cell and method of making the same|
|US8208294 *||Jan 22, 2010||Jun 26, 2012||Qimonda Ag||Resistive memory cell accessed using two bit lines|
|US8263962||Sep 11, 2012||Micron Technology, Inc.||Inverted variable resistance memory cell and method of making the same|
|US20050185445 *||Feb 15, 2005||Aug 25, 2005||Renesas Technology Corp.||Semiconductor device|
|US20060126378 *||Dec 22, 2005||Jun 15, 2006||Nazarian Hagop A||Serial transistor-cell array architecture|
|US20060239058 *||Apr 22, 2005||Oct 26, 2006||Micron Technology, Inc.||Method and apparatus for accessing a memory array|
|US20070159871 *||Mar 9, 2007||Jul 12, 2007||Renesas Technology Corp.||Semiconductor device with a non-erasable memory and/or a nonvolatile memory|
|US20080277641 *||May 8, 2007||Nov 13, 2008||William Arthur Stanton||Inverted variable resistance memory cell and method of making the same|
|US20100193765 *||Apr 9, 2010||Aug 5, 2010||William Arthur Stanton||Inverted variable resistance memory cell and method of making the same|
|US20100290277 *||Nov 18, 2010||Thomas Happ||Resistive memory cell accessed using two bit lines|
|U.S. Classification||365/46, 365/148|
|International Classification||G11C11/16, G11C27/00, G11C16/02, G11C11/00, G11C13/00, G11C16/26, G11C13/02|
|Cooperative Classification||G11C11/16, G11C13/003, B82Y10/00, G11C13/0014, G11C13/0016, G11C2213/78, G11C2213/79, G11C13/004, G11C13/0004, G11C13/0011|
|European Classification||G11C13/00R1, G11C13/00R25C, B82Y10/00, G11C13/00R25R, G11C13/00R5C, G11C13/00R5C2, G11C13/00R5B, G11C11/16|
|Nov 4, 2003||AS||Assignment|
Owner name: MICRON TECHNOLOGIES, INC., IDAHO
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:NAZARIAN, HAGOP A.;REEL/FRAME:014670/0862
Effective date: 20031030
|Jun 8, 2004||AS||Assignment|
Owner name: MICRON TECHNOLOGY, INC., IDAHO
Free format text: CORRECTIVE TO CORRECT THE ASSIGNEE S NAME PREVIOUSLY RECORDED AT REEL 014670 FRAME 0862. (ASSIGNMENT OF ASSIGNOR S INTEREST);ASSIGNOR:NAZARIAN, HAGOP A.;REEL/FRAME:015437/0045
Effective date: 20031030
|Nov 7, 2006||CC||Certificate of correction|
|Nov 18, 2009||FPAY||Fee payment|
Year of fee payment: 4
|Nov 20, 2013||FPAY||Fee payment|
Year of fee payment: 8
|May 12, 2016||AS||Assignment|
Owner name: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGEN
Free format text: SECURITY INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038669/0001
Effective date: 20160426
|Jun 2, 2016||AS||Assignment|
Owner name: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL
Free format text: PATENT SECURITY AGREEMENT;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:038954/0001
Effective date: 20160426