|Publication number||US7065606 B2|
|Application number||US 10/655,191|
|Publication date||Jun 20, 2006|
|Filing date||Sep 4, 2003|
|Priority date||Sep 4, 2003|
|Also published as||US20050055527|
|Publication number||10655191, 655191, US 7065606 B2, US 7065606B2, US-B2-7065606, US7065606 B2, US7065606B2|
|Inventors||Alexander E. Andreev, Igor A. Vikhliantsev, Ranko Scepanovic|
|Original Assignee||Lsi Logic Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (2), Classifications (7), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention generally relates to integrated circuits, and particularly to an apparatus and method for synthesizing a controller that automatically maps a customer's logic memories to given physical memories.
Integrated circuit (IC) design on a chip, e.g., LSI Logic Corporation's RapidSlice™, and the like, usually contains physical memories with fixed capacities and fixed data widths. However, a customer's IC design may contain logic memories with different capacities and data widths. Conventionally, mapping customer's logic memories to given physical memories is done manually, which is a very tedious and time-consuming process. Therefore, it would be advantageous to provide a controller for automatically mapping a customer's arbitrary logic memory into physical memories on a chip.
Accordingly, the present invention is directed to an apparatus and method for synthesizing a controller that automatically maps customer's logic memories to given physical memories. In an exemplary aspect of the present invention, a method for mapping a customer memory onto a plurality of physical memories may include the following steps: (a) dividing input of a customer memory into k input blocks, where k is an integer; (b) converting k input blocks into m input blocks, where m is an integer; and (c) combining m input blocks into input to a plurality of physical memories, each physical memory having a data width of m blocks.
In an additional exemplary aspect of the present invention, an apparatus for mapping a customer memory onto a plurality of physical memories may include: (a) a plurality of physical memories onto which a customer memory may be mapped, each of physical memories having a data width of m blocks, the customer memory having a data width of k blocks, and k and m being integers; (b) an address controller, communicatively coupled to a plurality of physical memories, for receiving first address information of the customer memory, for outputting second address information to a plurality of physical memories, and for outputting index information; (c) a data input controller, communicatively coupled to the address controller and a plurality of physical memories, for receiving data of the customer memory and the index information, and for outputting data with a data width of m blocks to a plurality of physical memories; and (d) a data output controller, communicatively coupled to a plurality of physical memories and to the address controller though a delay unit, for receiving the index information, for receiving output, with a width of said m blocks, of a plurality of physical memories, and for outputting the customer memory with a width of said k blocks.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed. The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention and together with the general description, serve to explain the principles of the invention.
The numerous advantages of the present invention may be better understood by those skilled in the art by reference to the accompanying figures in which:
Reference will now be made in detail to the presently preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings.
Referring generally now to
I. “Snake” Algorithm for Memory Packing
Suppose there is a customer's logic memory with a capacity cap and data width w, and two physical memories, each with a capacity tcap and data width tw, where
i.e., customer's logic memory data and physical memory data may be divided into blocks of the width block_width, where k and m are both integers, then the following may be assumed:
for some t.
From (1), the following may be obtained:
According to (4), if m=4, then k=3; if m=8, then k=5 or k=7.
For k=6, block_width may be increased to twice wide, and m and k may be decreased to half according to formulas (2-1) and (2-2). Thus, for the case k=6, m=4 and k=3 may still be obtained.
The algorithm of the present invention goes through data blocks (cells) of an original logic memory like a snake and packs the data to a wider memory consecutively. After all the data of the original logic memory are packed into the wider memory, the wider memory may be divided into two physical memories in the following way: all the cells with even addresses of the wider memory may be consecutively put into the first memory named Memory-1, and all the cells with odd addresses of the wider memory may be consecutively put into the second memory named Memory-2.
As shown in
Similarly, for k=5 and m=8, an exemplary snake algorithm in accordance with an exemplary embodiment of the present invention is shown in
where A, A1, and A2 are all integers.
Take into account formula (3), the following may be obtained:
where the symbol “>>” represents a Bitwise Right-Shift. Operation a>>b means a right shift of all digits of integer a by b times, and returns the value of a divided by 2 to the power of b, i.e., (a/2^b). For example, suppose a=25=(00011001) and b=3, then a>>b=3=(00000011). If a=(a0, a1, . . . , ak), then a>>b=(0, . . . , 0, a0, a1, . . . ,a(k-b)).
II. Circuit for Snake Algorithm Realization
The process of packing is periodic with a period (2*m) because k is odd. For a cell of the original logic memory with address A=(i+2m), the packing actions may be repeated as for the cell with address A=i. For a cell with address A=(i+m), the packing actions may be repeated as for the cell with address A=i, with one change (the memories are permuted because k is odd).
For example, in
The index of the address in the period may be denoted by index. Obviously,
and from formula (3) the following may be obtained:
Thus, when A<2*m, index=A.
The address controller 402 may receive an address A of an original logic memory as input. The address controller 402 may then output an address A1 of the physical Memory-1 408 based on formula (5a-1), an address A2 of the physical Memory-2 410 based on formula (5a-2), and an index based on formula (6a).
The data input controller 404 may receive DI (Data In) and the index as input. The DI may be a customer's arbitrary memory with a width of k block_width. The data input controller 404 may output DI1 and DI2, both with a width of m block_width. Thus, the data input controller 404 converts the customer's memory with a width of k block_width into memories with a width of m block_width. The data input controller 404 will be described in detail below.
The physical Memory-1 408 and the physical Memory-2 410 may receive DI1 and DI2 as input and output DO1 and DO2, respectively. Both DO1 and DO2 have a width of m block_width.
The data output controller 412 may receive a delayed index (Dindex obtained through the delay unit 414), DO1 and DO2 as input and may output DO, which has a width of k block_width. Thus, the data output controller 412 converts memories with a width of m block_width back into a memory with a width of k block_width. The data output controller 412 will be described in detail below.
The write-enable controller 406 is the same as the data input controller 404 except wires WE, WE1 and WE2 are used instead of DI, DI1 and DI2, respectively.
Thus, the circuit 400 automatically maps a customer's logic memory with a data width of k block_width to a plurality of physical memories, each with a data width of m block_width. From the customer's perspective, however, the customer may only see DI and DO, both have a data width of k block_width. The customer may not realize that the logic memory has been mapped to physical memories with a different data width.
(2) Data Input Controller
The i-th block of the input data (i.e., DI in
The content of i-th block of the Memory-1 for index=j may be denoted by mem1_data[i][j], and the content of i-th block of the Memory-2 for index=j may be denoted by mem2_data[i][j], where 0≦j<2*m and 0≦i<m.
For the semi-period m, the following may be obtained:
When 0≦j<m, because the snake subsequence is periodic the memories may be permuted.
For the full period 2*m, the following may be obtained
For example, for m=4 and k=3, the following may be obtained:
mem2_data[i]=0 for any i,
because all blocks with the address 0 belongs to Memory-1 (see, e.g.,
In addition, for m=4 and k=3, the following may be obtained:
As shown in
The content of i-th input block for Memory-1 may be denoted by x[i], and the content of i-th input block for Memory-2 may be denoted by y[i], where 0≦i<m. Thus,
x[i]=((mem1_data[i] & ind)
Note, based on the above two formulas, a tree of disjunctions with a minimal depth to realize x[i] and y[i] may be constructed. For example,
Referring back to
(3) Data Output Controller
As described previously, the i-th block of the original input data (i.e., DI in
where mem1_block[i] represents the i-th block from the Memory-1 106 and mem2_block[i] represents the i-th block from the Memory-2 108.
z[i]=(memdata[i] & ind)
The output z in
The process 800 shown in
It is to be noted that the above described embodiments according to the present invention may be conveniently implemented using conventional general purpose digital computers programmed according to the teachings of the present specification, as will be apparent to those skilled in the computer art. Appropriate software coding may readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software art.
It is to be understood that the present invention may be conveniently implemented in forms of software package. Such a software package may be a computer program product which employs a storage medium including stored computer code which is used to program a computer to perform the disclosed function and process of the present invention. The storage medium may include, but is not limited to, any type of conventional floppy disks, optical disks, CD-ROMs, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or any other suitable media for storing electronic instructions.
It is understood that the specific order or hierarchy of steps in the processes disclosed is an example of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the processes may be rearranged while remaining within the scope of the present invention. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
It is believed that the present invention and many of its attendant advantages will be understood by the foregoing description. It is also believed that it will be apparent that various changes may be made in the form, construction and arrangement of the components thereof without departing from the scope and spirit of the invention or without sacrificing all of its material advantages. The form herein before described being merely an explanatory embodiment thereof, it is the intention of the following claims to encompass and include such changes.
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|U.S. Classification||711/102, 711/170, 711/202|
|International Classification||G06F12/00, G06F12/04|
|Sep 4, 2003||AS||Assignment|
Owner name: LSI LOGIC CORPORATION, CALIFORNIA
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