US 7065698 B2 Abstract A method and an apparatus for encoding/decoding RS (Reed-Solomon) code using a binary equivalence method of bit level. The apparatus includes a binary conversion unit for converting non-binary symbols outputted from a source information inputting unit into binary symbols and getting bit level RS code using a binary equivalence of the RS code, an encoding unit for generating row and column vectors using the bit level RS code as a component code, and a decoding unit for decoding the row and column vectors using the binary equivalence of the RS code for the bit level RS sequence.
Claims(12) 1. An encoding method of an RS (Reed-Solomon) code in bit level, the method being performed in an encoding apparatus and comprising:
generating a binary equivalence matrix of the RS code by multiplying a non-binary systematic generator matrix and a binary information sequence of the RS code such that the generated binary equivalence matrix includes row and columns which are m times rows and columns of the non-binary matrix, where symbols of the non-binary matrix have a GF(2
^{m}) dimension; andgenerating row and column vectors using the binary equivalence matrix of the RS code as a component code.
2. A decoding method of an RS (Reed-Solomon) code in bit level, the method being performed in a decoding apparatus and comprising:
generating a binary trellis using a binary parity check matrix corresponding to a binary generator matrix of the RS code from a received signal; and
performing repeatedly processes of decoding row and column vectors using the binary trellis and of getting extrinsic information of bit level and inputting the extrinsic information of bit level as a new decoding information,
wherein the binary generator matrix of the RS code is converted from a non-binary matrix originally representing the RS code and includes rows and columns which are m times rows and columns of the non-binary matrix, where symbols of the non-binary matrix have a GF(2
^{m}) dimension.3. An encoding apparatus of an RS (Reed-Solomon) code in bit level comprising:
a source information inputting unit configured to receive source information for encoding;
a binary conversion unit configured to convert non-binary symbols outputted from the source information inputting unit into binary symbols;
an encoding unit configured to encode the binary symbols to check and correct errors which may be generated by the binary symbols on a communication channel; and
a modulating unit configured to modulate the binary symbols encoded in the encoding unit so as to transmit the symbols through the communication channel,
wherein the binary conversion unit generates a binary equivalence of the RS code by multiplying a binary information sequence and a non-binary systematic generator matrix such that the generated binary equivalence matrix includes row and columns which are m times rows and columns of the non-binary matrix, xvhere symbols of the non-binary matrix have a GF(2
^{m}) dimension, and then generates a bit level RS code using the binary equivalence matrix.4. The apparatus of
5. A decoding apparatus of an RS (Reed-Solomon) code in bit level comprising:
a demodulating unit configured to demodulate binary symbols of the RS code transmitted from a communication channel;
a decoding unit configured to repeatedly decode row and column vectors of the binary symbols using a binary equivalence matrix of the RS code; and
a source information outputting unit configured to output the decoded binary symbols as a data stream,
wherein the binary equivalence matrix of the RS code is converted from a non-binary matrix originally representing the RS code and includes rows and columns which are m times rows and columns of the non-binary matrix, where symbols of the non-binary matrix have a GF(2
^{m}) dimension.6. The apparatus of
a column vector decoder configured to generate a column vector by calculating the sequence of the bit level RS code and nexv decoding information transmitted from the demodulating unit; and
a row vector decoder configured to generate a row vector by being inputted the column vector transmitted from the column vector decoder, and to feedback new decoding information to the column vector decoder.
7. A storage medium with computer programming instructions contained therein, the instructions when executed causing a processing device to perform
a first computer code transforming a non-binary matrix representation of a Reed-Solomon (RS) code including non-binary symbols into a binary equivalence matrix including only binary symbols; and
a second computer code generating row and column vectors using the binary equivalence matrix,
wherein each non-binary symbol is transformed into an m×m matrix, where symbols of the non-binary matrix have GF(2
^{m}) dimension, andwherein the binary equivalence matrix includes row and columns which are m times row and columns of the non-binary matrix.
8. The computer program product of
a third computer code configured to encode the binary symbols to check and correct errors which may be generated by the binary symbols on a communication channel; and
a fourth computer code configured to modulate the encoded binary symbols so as to transmit the symbols through the communication channel.
9. The computer program product of
a fifth computer code configured to demodulate the binary symbols of the RS code transmitted from the communication channel;
a sixth computer code configured to repeatedly decode row and column vectors of the binary symbols using the binary equivalence matrix of the RS code; and
a seventh computer code configured to output the decoded binary symbols as a data stream.
10. An apparatus for processing a Reed-Solomon (RS) code, comprising:
a converting unit configured to transform a non-binary matrix representation of the RS code including non-binary symbols into a binary equivalence matrix including only binary symbols; and
an encoding unit configured to encode row and column vectors using the binary equivalence matrix,
wherein the converting unit transforms each non-binary symbol into an m×m matrix, where symbols of the non-binary matrix have a GF(2
^{m}) dimension, andwherein the binary equivalence matrix includes row and columns which are m times row and columns of the non-binary matrix.
11. The apparatus of
the encoding unit configured to encode the binary symbols to check and correct errors which may be generated by the binary symbols on a communication channel; and
a modulating unit configured to modulate the encoded binary symbols so as to transmit the symbols through the communication channel.
12. The apparatus of
a demodulating unit configured to demodulate binary symbols of the RS code transmitted from the communication channel;
a decoding unit configured to repeatedly decode row and column vectors of the binary symbols using the binary equivalence matrix of the RS code; and an outputting unit configured to output the decoded binary symbols as a data stream.
Description 1. Field of the Invention The present invention relates to an error correction code in a digital communication system, and particularly, to a method and an apparatus for encoding/decoding Reed-Solomon(hereinafter referred to RS) code made by non-binary symbols in bit level. 2. Description of the Background Art Generally, a product code is a form of a serial concatenation block turbo code, and shows a high trade-off in a performance and in a complexity compared to a turbo code based on a convolution code. Especially, the product code is less complex and has a higher performance than the turbo code based on the convolution code in a high rate system having a high band-width efficiency and in a short block frame for communication devices. Also, the performance of the product code is decided by the component code, and therefore the RS code having a good characteristics is used for the component code of the product code. The source information inputting unit The encoding unit The modulating unit The communication channel is made by radio or wire. The demodulating unit The decoding unit In the RS product code, respective row and column vectors are (N, K) codewords, and a respective symbol has a GF(2 The SISO decoding method for the RS product code can be divided into two methods. A first method is a chase algorithm. However, thin algorithm has a problem that the decoder becomes very complex because the number of test patterns which is to be produced is very large for the RS code having a large dimension. A second method is a SISO decoding method based on a trellis using the MAP (Maximum A posteriori) algorithm, Max-log, SOVA (Soft-Output Viterbi Algorithm) on a trellis of block code. However, in the above algorithms, the RS code has non-binary characteristics, and the number of branches of a respective trellis node is non-binary. Therefore, the decoding processes of the algorithms in the respective node are more complex than that in the binary branches. Also, the size of the interleaver is small according to the symbol dimension comparing to the size of the block which performs the decoding. Therefore, it is inefficient to use an iterative decoder in which the performance of the algorithms depends on the size of the interlearver. Therefore, an object of the present invention is to provide a decoding algorithm by which branch complexity is reduced comparing to a case of using non-binary symbol, also the size of interleaver is greatly extended in bit level by performing encoding/decoding process by generating trellis of bit level using binary equivalence of RS code. To achieve the object of the present invention, as embodied and broadly described herein, there is provided a RS code encoding method in a bit level according to the present invention comprising the steps of: generating binary equivalence of RS code by multiplying systematic generator matrix by binary information sequence of the RS code; and generating row and column vector using the binary equivalence of the RS code as a component code. Also, there is provided a decoding method of the RS code in bit level according to the present invention comprising the steps of: generating binary trellis from a receive signal using binary parity check matrix corresponded to the binary generator matrix of the RS code; and decoding row vector and column vector using the binary trellis, searching extrinsic information of the bit level, and inputting the extrinsic information of the bit level as new decoding information. In addition, there is provided a encoding apparatus the RS code in the bit level according to the present invention comprising: a source information inputting unit in which source information for encoding is inputted; a binary conversion unit for being inputted non-binary symbols outputted from the source information inputting unit and changing the symbols into binary symbols; a encoding unit for encoding the binary symbols in order to check and correct errors which may be generated by the conversed binary symbols on the communication channels; and a modulating unit modulating the binary symbols encoded in the encoding unit so as to be transmitted through the communication channel. Also, there is provided a decoding apparatus for RS code on bit level according to the present invention comprising: a demodulating unit for demodulating the binary symbols of the RS code transmitted through the communication channel; a decoding unit for decoding row vectors and column vectors of the demodulated binary symbols repeatedly using the binary equivalence of the RS code; and a source information outputting unit for outputting the decoded binary symbols as data stream. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. The source information inputting unit The binary conversion unit The encoding unit The modulating unit The demodulating unit The decoding unit The encoding processes of the RS code will be described as follows with reference to A generator matrix G for (N, K) RS code of code length N and of information length K having a symbol α
Therefore, multiple of any symbols A and B is expressed as follows.
The linear combination of Equation (2) can be expressed as following matrix.
Respective column vectors in the right matrix of Equation (3) are made such that the symbol vectors having symbol B are multiplied by α At that time, the generated binary codeword has the same code characteristics in the original RS code and in symbol weight distribution even if the encoding processes are made at bit level. Therefore, through Equations (1), (2), and (3), the number of rows is increased as many as the number of multiplying original row numbers by m, and the binary generator matrix is made by expressing respective symbols constituting the matrix on a polynomial basis. In the binary matrix, the components are 0 or 1 unlike in the original matrix, and the original non-binary matrix is converted into the binary matrix having rows and columns which are m times of the original rows and columns. In addition, the bit level RS code is generated by using the binary matrix (step S At that time, the generated binary codeword has the same code characteristics in the original RS code and in symbol weight distribution even if the encoding processes are made at bit level. Also, as shown in Therefore, the size of interleaver is m Therefore, SISO decoding in a bit level trellis structure can reduce the complexity of branches, and is useful in a decoder in which branches of a trellis is more complex than the depth of the trellis. The column vector decoder That is, the decoding unit Also, the decoding unit The decoding processes of the row and column vectors use conventional method using parity check matrix as a trellis generation method for the block code. In the structure above, the RS code having high decoding rate and systematic form is able to get the parity check matrix from the generator matrix, and the number of trellis states is smaller than in low decoding rate. The above processes are similar to the conventional art, however the trellis of binary level is applied to the row and column vectors of binary level and the decoder of binary level is used, whereby the extrinsic information of binary level is generated according to the present invention. As described above, the encoding/decoding process is performed by generating the trellis of bit level using the binary equivalence according to the present invention, whereby the branch complexity is reduced than in case of using the non-binary symbols. Also, the size of the interleaver which is an important part of repeated code is greatly enlarged in bit level. Also, the present invention has higher performance than the RS product code of non-binary in case that the present invention is applied to the communication system having a short block. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalence of such meets and bounds are therefore intended to be embraced by the appended claims. Patent Citations
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