|Publication number||US7078794 B2|
|Application number||US 10/250,289|
|Publication date||Jul 18, 2006|
|Filing date||Jun 20, 2003|
|Priority date||Feb 25, 2003|
|Also published as||US20040164389|
|Publication number||10250289, 250289, US 7078794 B2, US 7078794B2, US-B2-7078794, US7078794 B2, US7078794B2|
|Inventors||I Tseng Lee|
|Original Assignee||Via Technologies, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (2), Referenced by (25), Classifications (71), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the priority benefit of Taiwan application serial no.92103870, filed on Feb. 25, 2003.
1. Field of Invention
The present invention relates to a chip package and process for forming the same. More particularly, the present invention relates to a technique for forming a chip package that combines wire-bond and flip-chip processes together.
2. Description of Related Art
In the semiconductor industry, layout diagrams of well-designed integrated circuits are submitted to a wafer plant for circuit fabrication. Patterned circuits are formed on wafers after performing a series of operations including, for example, doping, metal deposition, photolithography and etching processes and dielectric depositions. Thereafter, the wafers are sent to a packaging plant where the wafers are diced up into chips and assembled into individual packages. The chip and the substrate are electrically connected by using wires or bumps. After the packaging process, the chip and the electrical connection between the chip and the substrate are well protected.
In the aforementioned chip package 100, the average length of each piece of conductive wire 140 is rather long (mostly greater than 130 mil) and its diameter is rather small (mostly smaller than 1.2 mil). Hence, an impedance mismatch between the conductive wires 140 and the circuits inside the chip 110 or substrate 130 is quite common and often results in rapid signal decay. Ultimately, the access signals frequently contain errors. In addition, parasitic inductance/capacitance effect is especially serious when the chip performs a high frequency operation. In the presence of parasitic inductance/capacitance effect, signal reflections inside the chip package will be pervasive.
As shown in
As shown in
Accordingly, one object of the present invention is to provide a chip package and a method of forming the same for improving the electrical performance of the substrate and the electrical performance of the chip after forming a complete package.
A second object of this invention is to provide a chip package and a method of forming the same for reducing the production cost of the package by using a lamination technique to fabricate the substrate.
A third object of this invention is to provide a chip package and a method of forming the same for preventing the formation of voids when an insulating material is injected into the space between the chip and the substrate.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a chip package. The chip package has a structure comprising at least a substrate, a chip, a plurality of bumps, a plurality of conductive wires, an insulating material and a plurality of contacts. The substrate has a first surface and a corresponding second surface. The substrate has a slot passing through the first surface and the second surface. The substrate furthermore has a plurality of first substrate pads and a plurality of second substrate pads. The first substrate pads are formed on the first surface of the substrate close to and surrounding the slot. The second substrate pads are formed on the second surface of the substrate close to and surrounding the slot. The chip is attached to the first surface of the substrate at a location corresponding to the slot. The chip has an active surface with a plurality of first chip pads and a plurality of second chip pads thereon. The second chip pads are positioned in the central region of the active surface and the first chip pads are positioned in the peripheral region of the active surface. Each bump connects a first chip pad with a corresponding first substrate pad. Each conductive wire passes through the slot such that one end of the wire connects with a second chip pad while the other end of the wire connects with a corresponding second substrate pad. The insulating material occupies the slot and the space between the chip and the substrate such that the conductive wires and the bumps are also enclosed. The contacts are attached and electrically connected to the first surface of the substrate.
In addition, high frequency signals from the chip to the substrate or vice versa are transmitted through the first substrate pads and the first chip pads. Moreover, the substrate can be fabricated using a low-cost lamination technique.
The chip package according to this invention has a design that separates signal transmissions into a high frequency and a none high frequency category. The high frequency signals are transmitted from the chip through the bumps to the bottom surface of the substrate while the none high frequency signals (for example, power signals or ground signals) are transmitted via conductive wires passing through the slot to the top surface of the substrate. Hence, high frequency signals are directly routed to the contacts at the bottom surface of the substrate through a single patterned circuit layer rather than indirectly through the upper patterned circuit layers, the vias and the lower patterned circuit layers within the substrate to reach the contacts.
In brief, aside from shortening signal transmission paths, the chip package according to this invention is able to reduce the number of vias that need to be used for interconnecting circuit layers inside the substrate. In other Words, the overall area of the substrate can be reduced. In addition, both the first surface and the second surface of the substrate have substrate pads for connecting with the chip. With the substrate pads distributed on two separate surfaces of the substrate, circuits linking the substrate pads can be spread further apart. Consequently, the probability of cross talk or noise interference is greatly reduced. The decrease in circuit line density also permits the less costly lamination technique instead of the more costly layering build-up process to fabricate the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
In this embodiment, the substrate 300 has a four-layered structure. However, the substrate can comprise any number of patterned metallic layers. Moreover, the substrate 300 can be fabricated using a lamination or a built-up process. If the lamination technique is used for fabricating the substrate 300, the production cost will be lowered.
The chip 400 comprises a plurality of chip bump pads 412 and a plurality of chip wire pads 414. The chip wire pads 414 are formed in the central region on the active surface 410 of the chip 400. The chip bump pads 412 are formed in the peripheral region on the active surface 410 of the chip 400. The active surface 410 of the chip 400 has a surface area larger than the sectional area of the slot 350 in the substrate 300. Before the chip 400 and the substrate 300 are bonded together, a plurality of bumps 450 are attached to the respective chip bump pads 414 by performing a printing or a plating process.
As shown in
As shown in
As shown in
As shown in
As shown in
The chip package 600 in
Hence, the ultimate amount of parasitic capacitance that can be introduced between the patterned metallic layers 322 and 323 will be reduced considerably. Under such circumstances, the capacitance loss can be compensated by incorporating an external capacitance so that the impact resulting from a sudden surge of electric current is minimized.
Aside from the high density circuit layout within the patterned metallic layer 324 of the substrate 300, density of circuits within the patterned metallic layers 321, 322, 323 are relatively low. Thus, a low cost lamination method instead of a costly built-up process may be deployed to fabricate the substrate 300 of the chip package 600.
In the first embodiment, a two-step process is used to form the insulating layer 510 and the insulating layer 530 for protecting the bumps and the conductive wires. However, a single process can be used to form a single insulating material.
In the first embodiment, the chip and the contacts are positioned on the same side of the substrate. In other words, both the chip and the contacts are on the first surface of the substrate. In practice, the chip and the contacts can be positioned on each side of the substrate.
As shown in
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
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|U.S. Classification||257/687, 257/690, 257/E23.004, 257/E21.511, 257/738, 257/702, 257/703, 257/E23.062, 257/693, 257/793, 257/789|
|International Classification||H01L23/31, H01L23/13, H01L23/22, H01L21/60, H01L23/498, H01L23/24|
|Cooperative Classification||H01L2224/05571, H01L2224/05573, H01L2924/181, H01L2224/45015, H01L24/48, H01L2224/73204, H01L2224/92147, H01L2224/73265, H01L2224/81801, H01L2924/3025, H01L2224/48091, H01L24/17, H01L2924/15311, H01L2924/14, H01L2924/30105, H01L2924/16152, H01L2224/92, H01L24/81, H01L2224/83102, H01L2924/01078, H01L23/3128, H01L2224/49, H01L24/73, H01L2924/18301, H01L2924/1532, H01L2924/30107, H01L23/49822, H01L23/13, H01L2224/73207, H01L2924/3011, H01L2224/32225, H01L24/92, H01L2224/48227, H01L2224/13099, H01L2224/85, H01L2924/00014, H01L24/85, H01L2224/92125, H01L24/49, H01L2924/014, H01L2224/73253, H01L2224/16225, H01L2224/4824, H01L2924/01047, H01L2924/15151|
|European Classification||H01L24/49, H01L24/85, H01L24/92, H01L24/73, H01L24/17, H01L24/81, H01L23/13, H01L23/31H2B, H01L23/498D|
|Jun 20, 2003||AS||Assignment|
Owner name: VIA TECHNOLOGIES, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, I TSENG;REEL/FRAME:013744/0255
Effective date: 20030402
|Jan 19, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Dec 18, 2013||FPAY||Fee payment|
Year of fee payment: 8