|Publication number||US7080344 B2|
|Application number||US 10/604,071|
|Publication date||Jul 18, 2006|
|Filing date||Jun 25, 2003|
|Priority date||Jun 25, 2003|
|Also published as||US20040268288, US20060190908|
|Publication number||10604071, 604071, US 7080344 B2, US 7080344B2, US-B2-7080344, US7080344 B2, US7080344B2|
|Inventors||Stanislav Peter Bajuk, Jack Robert Smith, Sebastian Theodore Ventrone|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (7), Classifications (12), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Technical Field
The present invention relates in general to a field of logic design, and in particular to the partitioning and synthesis of field programmable gate array (FPGA) and standard cell logic. Still more particularly, the present invention relates to a method and system for dynamically shifting the boundary between FPGA and standard cell logic within a physically placeable block that can simultaneously hold both FPGA and standard cell elements
2. Description of the Related Art
Building computer logic takes many steps before the computer logic is physically manufactured. The logic designer typically uses synthesis tools, such as register transfer languages (RTL) such as Verilog® and VHDL (Very-high-speed-integrated-circuit Hardware Descriptor Language) to describe, design and document electronic circuits. A typical RTL file includes a description of the interfaces to the logic and its behavior.
Two types of devices that can implement logic are FPGA (Field Programmable Gate Arrays) and Standard Cell. FPGA's use a 2-dimensional array of logic cells that are programmable, such that the FPGA functions as a custom integrated circuit (IC) that is modified by program code. Thus, a same FPGA can be alternately programed to selectively perform the function of many different logic circuits. Typically, the programming of the FPGA is persistent until re-programmed at a later time. The persistent nature may be permanent (e.g, by blowing fuses in gates) or modifiable (by storing the programming code in a programmable memory). Standard cell, on the other hand, is hard-wired logic that is not modifiable after it is manufactured. Although it does not have the flexibility of a FPGA, standard cells is usually much faster than FPGA. Furthermore, FPGA's typically have many more gates and logic components than standard cells, since only a part of the FPGA circuit is typically used in any selected programmed configuration. Thus, FPGA's provide flexibility through their modifiable nature, but standard cell is faster and takes up less die space to implement a given logic function.
RTL synthesis takes an RTL file and maps it into a technology supplied by the semiconductor vendor. For example, standard cell synthesis takes a standard cell RTL file and maps out a selection of logic available from the vendor's library, which includes elements such as adders, exclusive OR's (XOR's), AND gates, etc Similarly, FPGA synthesis maps an FPGA file into an FPGA fabric, supplying program information required for a particular FPGA using configuration files supplied by the vendor.
In the prior art, FPGA and standard cell logic are created by synthesizing separate RTL files tbr the FPGA logic and other files for standard cell logic. In some situations, the logic designer may elect to move logic across the boundary, for example from FPGA to standard cell. However, the RTL descriptor files as used in the prior art require FPGA files and standard cell files to be in separate files, as shown in
The present invention is directed to a method and system for storing and modifying register transfer language (RTL) described logic types. Upon a declaration of a signal interconnect, a language extension of a register transfer language is defined for the signal interconnect based on the signal interconnect type. The language extensions allow different signal interconnect types, such as those targeted to field programmable gate arrays (FPGA) and standard cells, to be stored in a same RTL file. This storage facilitates changing logic types, thus ultimately resulting in an integrated circuit (IC) that is either smaller (using more standard cells) or more flexible (using more FPGA cells). Repartitioning of the RTL can be performed within the physical design cycle, in which wiring, timing and placement of components (information) is performed before masking out the final chip design.
A tile is a physically placeable block that contains some portion of FPGA (0% to 100%) and another portion of standard cell (0% to 100%). By having the technology vendor's library offer several variations of tiles, all of which have the same outline size but different portions of FPGA and standard cell, the designer can repetition logic with a tile and replace it during the physical design phase with an alternate tile that represents the new partition. In addition, the library preferably contains tiles of smaller and larger sizes that can be selected to implement the logic in the appropriate amount of area on the IC.
The above, as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.
The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, where:
With reference now to
With reference now to
Unlike prior art RTL files in which only a single wire type (“wire”) was defined without regard to whether the design was targeted to FPGA or standard cell technology, the present invention defines multiple wire types, as shown in
Extension 302 (Swire) describes/defines a standard cell fixed wire, which cannot be modified to become an FPGA wire. Extension 304 (Fwire) describes/defines an FPGA wire, which cannot be modified to become a standard cell wire. Extension 306 (sFwire) describes an intermediate wire type, which, as described in more detail below, is an FPGA wire that can later be modified to become a standard cell wire. Extension 308 (fSwire) describes another intermediate wire type, which, as described below, is a standard cell wire that can later be modified to become an FPGA wire. Extension 310 (Sfwire) describes a standard cell wire, which can be modified to become an FPGA wire. Extension 312 (Fswire) describes an FPGA wire, which can be modified to become a standard cell wire.
With reference now to
Sfwire 310 a is input into logic 2 a, which is a standard cell logic. Also input into logic 2 a is a control line (cntl3) identified and described as Sfwire 310 b. Analogous to an FPGA logic, a standard cell logic can take only standard cell inputs. Logic 2 a has an output at node2 identified and described as Fswire 312 f, which is one of the inputs to FPGA logic 4. The other input to FPGA logic 4 a is Fswire 312 g, coming from the node3 output of standard cell logic 1. The output from logic 4 is the outbus identified/described as Sfwire 310 c. Also shown in
As each of the wires shown in
The process shown in
Referring now to
The iterative process described above allows the logic designer to dynamically change the structure of the logic without manually having to delete wires and constructs from one RTL file (such as an FPGA file) and then re-building the deleted wires/constructs for the new logic in another RTL file (such as a standard cell file). The process described in
In a preferred embodiment, however, the size of each of the tiles shown in
It should be understood that at least some aspects of the present invention may alternatively be implemented in a program product. Programs defining functions on the present invention can be delivered to a data storage system or a computer system via a variety of signal-bearing media, which include, without limitation, non-writable storage media (e.g., CD-ROM), writable storage media (e.g., a floppy diskette, hard disk drive, read/write CD ROM, optical media), and communication media, such as computer and telephone networks including Ethernet. It should be understood, therefore in such single-bearing media when carrying or encoding computer readable instructions that direct method functions in the present invention, represent alternative embodiments of the present invention. Further, it is understood that the present invention may be implemented by a system having means in the form of hardware, software, or a combination of software and hardware as described herein or their equivalent.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
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|U.S. Classification||716/103, 717/136, 717/144, 717/141, 717/142, 717/143, 716/105|
|Cooperative Classification||G06F17/5068, G06F17/5045|
|European Classification||G06F17/50D, G06F17/50L|
|Jun 25, 2003||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BAJUK, STANISLAV PETER;SMITH, JACK ROBERT;VENTRONE, SEBASTIAN THEODORE;REEL/FRAME:013755/0059;SIGNING DATES FROM 20030620 TO 20030623
|Dec 5, 2006||CC||Certificate of correction|
|Jan 19, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Feb 28, 2014||REMI||Maintenance fee reminder mailed|
|Jul 18, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Sep 9, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140718
|Sep 3, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001
Effective date: 20150629
|Oct 5, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001
Effective date: 20150910