|Publication number||US7084479 B2|
|Application number||US 10/731,377|
|Publication date||Aug 1, 2006|
|Filing date||Dec 8, 2003|
|Priority date||Dec 8, 2003|
|Also published as||CN1630077A, CN100416820C, US20050127514, US20060264036|
|Publication number||10731377, 731377, US 7084479 B2, US 7084479B2, US-B2-7084479, US7084479 B2, US7084479B2|
|Inventors||Shyng-Tsong Chen, Stefanie Ruth Chiras, Matthew Earl Colburn, Timothy Joseph Dalton, Jeffrey Curtis Hedrick, Elbert Emin Huang, Kaushik Arun Kumar, Michael Wayne Lane, Kelly Malone, Chandrasekhar Narayan, Satyanarayana Venkata Nitta, Sampath Purushothaman, Robert Rosenburg, Christy Sensenich Tyberg, Roy RongQing Yu|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (27), Referenced by (16), Classifications (24), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates to high density multilevel microelectronic integrated circuit (IC) structures. In particular, the present invention relates to the reduction of dielectric constant between conductive lines in each line level by providing air dielectric. A porous permanent dielectric in via levels is provided in order to optimize further the performance of the structure in a functioning device.
An aggressive drive continues toward increasing the density of features in the IC structure and toward decreasing the size of individual features. At present, feature dimensions can be fabricated to be as small as about 0.5 microns or less, and may be separated by less than 5000 Angstroms. As the drive continues, materials and processes by which the IC structure is composed must be reexamined in order to deal with problems associated with increasing proximity. A major problem with increased density is the increased intralevel interaction in capacitive voltage coupling and cross-talk between conductive lines, the largest component of which is between adjacent conductive lines in a given line level. As a result of this increased interaction, the IC is at great risk for failure at line level, in the form of unacceptably slow signal propagation, i.e. Resistance-Capacitance (R-C) delay and increased energy consumption. Interlevel interaction, while a lesser component of delay, is advisedly reduced also in order for the effective dielectric constant of the IC structure to be minimized.
The typical IC is fabricated on a semiconductor wafer substrate. Besides single crystal silicon, other potential semiconductor substrates are gallium arsenide, silicon-on-sapphire, silicon germanium, silicon-on-insulator and diamond, etc. as set forth in U.S. Pat. No. 6,251,798 B1 to Soo et al. On and/or within the substrate may be included such features as transistors, bipolar devices and diodes. Above the substrate is fabricated an IC structure comprising electrically interconnected alternating layers of vias and layers of parallel wiring lines within an insulating dielectric medium.
There is substantial prior and current art which is focused on providing the material and means of reducing the dielectric constant (K) of the insulating medium from below the approximate value 3.9 of silicon dioxide to a value which is as close as possible to the ideal value of vacuum, 1.0000, or air, 1.0002. Various low dielectric materials including fluorinated silicon dioxide, various polymers, spin-on glasses and xerogels have been explored in the current art, as for example described in U.S. Pat. No. 6,297,125 B1 to Nag et al. and in U.S. Pat. No. 6,211,057 B1 to Lin. While these materials all have low K, the value is not as low as the ideal value of air and, as described in the Nag et al. patent, each may come with its own alternate limitations when left as the wiring level dielectric.
In efforts to reduce K, air has been incorporated by various means into a dielectric matrix in the form of hollow beads, bubbles, holes or porosities. Air has also been produced in wiring levels by removing, at least partially, a solid dielectric material using an etchant. As described in the Nag et al. patent, for one example, the temporary dielectric material described is the spin-on glass (SOG) hydrogen silsequioxane (HSQ), which is removed by HF after protection of the aluminum wiring lines. Air gaps may also be incorporated as a permanent dielectric only in particular areas of an IC structure, such as shown in U.S. Pat. No. 6,316,347 B1 and B2 to Chang et al.
Some additional art directed to air dielectric is reviewed in U.S. Pat. No. 6,596,624 B1 to Romankiw, which is assigned to the same assignee as is the present invention. The Romankiw patent describes also the provision of strategically placed nonconductive vias, including at the periphery of the IC structure, and simultaneous removal of dielectric from some or all levels after joining. Another processing scheme in the art includes Etch-back Gap Fill (EBGF), U.S. Pat. No. 6,346,484.
If air gaps are to be created by only partial removal of the solid dielectric, it remains important to incorporate a low K material into the structure, especially in the wiring levels. If removal is to be complete in a level, the sacrificial material in that level need not be a dielectric. No matter how extensive the replacement of sacrificial material will be, it must be removable by a process that will not contaminate, overheat, chemically attack, mechanically distort or otherwise compromise the integrity of the structure that will remain after processing. It would be desirable to employ means that will remove the sacrificial material cleanly and thoroughly in as environmentally friendly a way as possible, in a series of reliable, efficient manufacturable process steps, compatible with microelectronics processing, to produce a robust ultra-low-K IC structure.
Several patents describe carbon as the sacrificial material and oxygen plasma or oxygen ashing as the atmosphere in which CO2 is formed and then diffused away. Some examples are 6,492,256 B2 and U.S. Pat. No. 6,492,732 B2, both to Lee et al. In the Lee patents is described a dielectric liner to protect the wiring from the oxygen ashing or plasma etch. The presence of a liner on the wiring, however, risks raising the effective K. In U.S. Pat. No. 6,350,672 B1 to Sun there is no liner described. Some wiring, however, such as copper, would be attacked by oxygen ash or oxygen plasma etch.
In describing the structure and process of the present invention, the term “air dielectric” is intended to encompass vacuum, air, low-K inert gasses, forming gas and any mixtures thereof that can harmlessly replace a solid, temporary material to function as permanent dielectric.
The present invention provides a process and structure which results in a mechanically stable IC in a way that avoids processing problems experienced in the art. This result is accomplished by having air dielectric at line levels where the metallization is dense and a low-K dielectric environment is most required, in combination with low-K gas-permeable solid or porous permanent dielectric material at via levels to provide mechanical stability. The present invention does not include removal of sacrificial material by oxygen ashing or oxygen plasma etch or a reactive ambient lest the copper wiring lines be adversely affected. The present invention is directly compatible with the dual damascene process for the fabrication of copper wiring lines which is currently the state of the art.
The process of fabricating the structure of the invention includes the following exemplary steps, which take place on a semiconductor substrate on or in which there may be protected devices:
A permanent dielectric is deposited by means known in the art. A non-permeable etch stop is deposited on the surface of the solid permanent dielectric. A sacrificial material is deposited on the surface of the etch stop. A gas permeable single or dual level hard mask is deposited on the surface of the sacrificial material. After dual damascene processing and chemical metal polishing (CMP) to provide a conductive wiring level, which may be connected by via to any device below on the semiconductor level, a thin protective cap is selectively deposited on the conductive wiring.
After the via level permanent dielectric is applied on the wiring level which is selectively capped, heat is applied. The heat is applied either in vacuum atmosphere or in another controlled unreactive atmosphere at a temperature and for a time which concurrently decomposes and diffuses the sacrificial material out through the gas permeable via level dielectric, completes any necessary hard mask cure and via level permanent dielectric cure, and removes the bi-products of the heat process.
After heat treatment, a non-gas permeable etch stop is deposited on the via level and cured in order to protect the via and metallization levels from any contamination that might be generated in the sequential processing of additional layers. The process is repeated to fabricate additional via and line levels, as required. The IC of the present invention will provide Back End of Line (BEOL) interconnects with the lowest possible effective K in the line level where it has the biggest impact on RC delay, balanced with the most robust mechanical stability.
It should be noted that the permanent dielectric material selected should not be decomposable at a temperature near or below the temperature at which the sacrificial dielectric material is decomposed, unless air dielectric is desired for both via levels and line levels. However, if the permanent dielectric material is of a type that forms or maintains porosities while the sacrificial dielectric material is removed, the K value can be further reduced.
After dual Damascene processing is performed to provide conductive via 5 within permanent dielectric 1 and wiring 6 within sacrificial layer 3 as shown in
A blanket layer of permanent dielectric material 8 is then deposited on the wiring level as shown in
Starting with the process step underway in
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|U.S. Classification||257/522, 257/E21.573, 257/758, 257/E23.144, 257/E21.581, 257/E23.167, 257/E23.013|
|International Classification||H01L23/522, H01L23/48, H01L23/52, H01L21/768, H01L29/00, H01L23/532, H01L29/40|
|Cooperative Classification||H01L2924/0002, H01L23/5329, H01L23/53295, H01L23/5222, H01L21/7682, H01L21/76829|
|European Classification||H01L23/522C, H01L21/768B6, H01L23/532N4, H01L23/532N|
|Dec 8, 2003||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHEN, SHYING-TSONG;CHIRAS, STEFANIE RUTH;COBURN MATTHEW EARL;AND OTHERS;REEL/FRAME:014811/0688;SIGNING DATES FROM 20031201 TO 20031202
|Jan 21, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Mar 14, 2014||REMI||Maintenance fee reminder mailed|
|Aug 1, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Sep 23, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140801
|Sep 3, 2015||AS||Assignment|
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001
Effective date: 20150629