Publication number | US7085799 B2 |

Publication type | Grant |

Application number | US 10/203,004 |

PCT number | PCT/JP2001/010670 |

Publication date | Aug 1, 2006 |

Filing date | Dec 6, 2001 |

Priority date | Dec 7, 2000 |

Fee status | Lapsed |

Also published as | US20030014460 |

Publication number | 10203004, 203004, PCT/2001/10670, PCT/JP/1/010670, PCT/JP/1/10670, PCT/JP/2001/010670, PCT/JP/2001/10670, PCT/JP1/010670, PCT/JP1/10670, PCT/JP1010670, PCT/JP110670, PCT/JP2001/010670, PCT/JP2001/10670, PCT/JP2001010670, PCT/JP200110670, US 7085799 B2, US 7085799B2, US-B2-7085799, US7085799 B2, US7085799B2 |

Inventors | Yukio Koyanagi |

Original Assignee | Yasue Sakai |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (11), Classifications (9), Legal Events (5) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 7085799 B2

Abstract

An analog filter includes a first arithmetic operation section **2** _{-1 }having a plurality of sets of processing circuit being cascade connected, each processing circuit having an S/H circuit of plural stages for holding a ΔΣ-modulated signal and an analog adder for adding the input and output signals of the S/H circuit, in which the number of stages of the S/H circuits **11** _{-1} **, 14** _{-1} **, 17** _{-1 }and **20** _{-1 }decreases toward the end of cascade connection, and a second arithmetic operation section **2** _{-2 }configured in the same way, which are cascade connected. By using such an analog filter, over sampling and convolution of a ΔΣ-modulated signal are conducted so that the envelope of the filter output may be a quadratic curve of finite carrier that converges to zero at finite sampling points to prevent phase distortion of an LPF and a discretization error due to a conventional function. Compared with a conventional circuit for over-sampling and convolution, the number of stages of the S/H circuits and the number of adders are small.

Claims(4)

1. An analog filter comprising: a first arithmetic operation section for performing moving average operation or convolution operation on individual ΔΣ-modulated discrete data to perform interpolation so that the envelope of the output waveform may be a symmetrical trapezoidal wave; and a second arithmetic operation section for performing moving average operation or convolution operation on individual discrete data of said symmetrical trapezoidal wave obtained in said first arithmetic operation section to perform interpolation, so that the envelope of the output waveform may be a quadratic curve wave passing the sample values of individual ΔΣ-modulated discrete data; characterized in that each of said first arithmetic operation section and said second arithmetic operation section has a circuit composed of a sample hold circuit of plural stages for holding a signal, an adder for adding the input and output signals of the sample hold circuit of plural stages, and a ½ divider for dividing by two the output signal of said adder, as one set of processing circuit, a plurality of sets of processing circuit being cascade connected, and said sample hold circuit of plural stages provided for said plurality of sets of processing circuit has a different number of stages.

2. The analog filter according to claim 1 , characterized in that the number of stages of the sample hold circuit of plural stages provided for said plurality of sets of processing circuit decreases toward the end of said cascade connection in each of said first arithmetic operation section and said second arithmetic operation section.

3. The analog filter according to claim 1 , characterized by further comprising a preprocessing section for preprocessing individual ΔΣ-modulated discrete data according to a digital fundamental waveform that is the basis of a sampling function of finite carrier that converges to zero at finite sampling points to conduct the moving average operation or convolution operation on the output signal of said preprocessing section.

4. An analog filter, comprising:

a first arithmetic operation section having a circuit composed of a sample hold circuit of 2^{i }stages for holding a signal, an adder for adding the input and output signals of said sample hold circuit of 2^{i }stages, and a ½ divider for dividing by two the output signal of said adder, as one set of processing circuit, j sets of processing circuit being cascade connected, the number of stages of said sample hold circuit of 2i stages provided for said sets of processing circuit being i=j−1, j−2, . . . , 1, 0;

a second arithmetic operation section configured in the same way as said first arithmetic operation section, wherein said first arithmetic operation section and said second arithmetic operation section are cascade connected; and

a sample hold circuit of one stage for holding an output signal of said second arithmetic operation section, an adder for adding the input and output signals of said sample hold circuit of one stage, and a ½ divider for dividing by two the output signal of said adder.

Description

1. Field of the Invention

The present invention relates to an analog filter that is suitably used as a filter for smoothing a ΔΣ-modulated signal, for example.

2. Description of the Related Art

A ΔΣ-modulation is a method for encoding an analog signal with a variation in the data for the immediately preceding data at each sampling point sampled at each timing of a predetermined sampling frequency in converting an analog signal into a digital signal. That is, the ΔΣ-modulation represents an amplitude component of the analog signal in binary value (one bit) alone.

This ΔΣ-modulation is employed for encoding an audio signal, for example. The ΔΣ-modulation method has the merits that the overall constitution can be simplified as compared with the PCM method for the CD (Compact Disk) widely used at present, and the restorability from the digital signal to the original analog signal can be enhanced by controlling the distribution of quantization noise.

That is, in the PCM method, the analog signal is replaced with the digital signal by making an arithmetic operation based on the quantization characteristic at each timing of the sampling frequency, and the absolute amount of data are recorded at all the sampling points. On the contrary, in the ΔΣ-modulation method, a variation in the data for the immediately preceding data is only recorded, and no thinning or interpolation of information amount is made, unlike the PCM method, whereby the binary signal produced by quantization presents a characteristic quite close to analog characteristic.

Accordingly, in the case of reproducing the digital signal encoded on the basis of the ΔΣ-modulation method, the original analog signal can be reproduced by making a simple process of removing high frequency components of the digital signal through a low pass filter provided at the last stage, without need for a D/A converter, unlike the PCM method. In practice, in the conventional audio reproducing apparatus, the original analog signal was reproduced by passing the ΔΣ-modulated signal through the low pass filter.

However, when the low pass filter was used, there was a problem that the output waveform was distorted due to a phase distortion of the low pass filter. Another method is conceived in which an interpolation process with the sinc function is made by applying an over-sampling technique currently employed for the CD and so on. However, since this sinc function converges to zero toward ±∞, a discretization error occurs in the arithmetic operation and a distorted output waveform is produced. Also, there was another problem that the constitution was quite complex.

The present invention has been achieved to solve the above-mentioned problems, and it is an object of the invention to provide an analog filter optimal for the ΔΣ-modulated output. Specifically, the invention is aimed at providing an analog filter with less distortion in the output waveform and of a simple constitution.

The present invention provides an analog filter for performing over-sampling and moving average operation or convolution operation on individual ΔΣ-modulated discrete data to perform interpolation so that the envelope of the output waveform may be a quadratic curve passing the sample values of individual ΔΣ-modulated discrete data, wherein a plurality of sets of processing circuit are cascade connected, each set of processing circuit, comprising a sample hold circuit of plural stages for holding a signal, and an adder for adding the input and output signals of the sample hold circuit of plural stages and the number of stages of the sample hold circuit of plural stages for the plurality of sets of processing circuit being different.

In this analog filter, the number of stages of the sample hold circuit of plural stages provided for the plurality of sets of processing circuit decreases toward the end of the cascade connection.

This invention further provides an analog filter comprising a first arithmetic operation section for performing moving average operation or convolution operation on individual ΔΣ-modulated discrete data to perform interpolation so that the envelope of the output waveform may be a symmetrical trapezoidal wave, and a second arithmetic operation section for performing moving average operation or convolution operation on individual discrete data of the symmetrical trapezoidal wave obtained in the first arithmetic operation section to perform interpolation, so that the envelope of the output waveform may be a quadratic curve wave passing the sample values of individual ΔΣ-modulated discrete data, wherein each of the first arithmetic operation section and the second arithmetic operation section has a circuit composed of a sample hold circuit of plural stages for holding a signal, and an adder for adding the input and output signals of the sample hold circuit of plural stages as one set of processing circuit, a plurality of sets of processing circuit being cascade connected, and the number of stages of the sample hold circuit of plural stages provided for the plurality of sets of processing circuit being different.

This invention still further provides an analog filter comprising a first arithmetic operation section for performing moving average operation or convolution operation on individual ΔΣ-modulated discrete data to perform interpolation so that the envelope of the output waveform may be a symmetrical trapezoidal wave, and a second arithmetic operation section for performing moving average operation or convolution operation on individual discrete data of the symmetrical trapezoidal wave obtained in the first arithmetic operation section to perform interpolation so that the envelope of the output waveform may be a quadratic curve wave passing the sample values of individual ΔΣ-modulated discrete data, wherein each of the first arithmetic operation section and the second arithmetic operation section has a circuit composed of a sample hold circuit of plural stages for holding a signal, an adder for adding the input and output signals of the sample hold circuit of plural stages, and a ½ divider for dividing by two the output signal of the adder, as one set of processing circuit, a plurality of sets of processing circuit being cascade connected, and the number of stages of the sample hold circuit of plural stages provided for the plurality of sets of processing circuit being different.

In the analog filter, the number of stages of the sample hold circuit of plural stages provided for the plurality of sets of processing circuit decreases toward the end of the cascade connection in each of the first arithmetic operation section and the second arithmetic operation section.

The analog filter further comprises a preprocessing section for preprocessing individual ΔΣ-modulated discrete data according to a digital fundamental waveform that is the basis of a sampling function of finite carrier that converges to zero at finite sampling points to conduct the moving average operation or convolution operation on the output signal of the preprocessing section.

This invention further provides an analog filter comprising a first arithmetic operation section having a circuit composed of a sample hold circuit of 2^{i }stages for holding a signal, and an adder for adding the input and output signals of the sample hold circuit of 2^{i }stages, as one set of processing circuit, j sets of processing circuit being cascade connected, the number of stages of the sample hold circuit of 2^{i }stages provided for the j sets of processing circuit being i=j−1, j−2, . . . , 1, 0, and a second arithmetic operation section configured in the same way as the first arithmetic operation section, wherein the first arithmetic operation section and the second arithmetic operation section are cascade connected.

The invention further provides an analog filter comprising a first arithmetic operation section having a circuit composed of a sample hold circuit of 2^{i }stages for holding a signal, an adder for adding the input and output signals of the sample hold circuit of 2^{i }stages, and a ½ divider for dividing by two the output signal of the adder, as one set of processing circuit, j sets of processing circuit being cascade connected, the number of stages of the sample hold circuit of 2^{i }stages provided for the j sets of processing circuit being i=j−1, j−2, . . . , 1, 0, and a second arithmetic operation section configured in the same way as the first arithmetic operation section, wherein the first arithmetic operation section and the second arithmetic operation section are cascade connected.

The analog filter further comprises a sample hold circuit of one stage for holding an output signal of the second arithmetic operation section, an adder for adding the input and output signals of the sample hold circuit of one stage, and a ½ divider for dividing by two the output signal of the adder.

The invention further provides an analog filter comprising a preprocessing section for preprocessing individual ΔΣ-modulated discrete data according to a digital fundamental waveform that is the basis of a sampling function of finite carrier that converges to zero at finite sampling points, a first arithmetic operation section having a circuit composed of a sample hold circuit of 2^{i }stages for holding a signal, and an adder for adding the input and output signals of the sample hold circuit of 2^{i }stages, as one set of processing circuit, j sets of processing circuit being cascade connected, the number of stages of the sample hold circuit of 2^{i }stages provided for the j sets of processing circuit being i=j−1, j−2, . . . , 1, 0, and a second arithmetic operation section configured in the same way as the first arithmetic operation section, wherein the first arithmetic operation section and the second arithmetic operation section are cascade connected.

This invention is composed of the technical means as above, in which over-sampling and the moving average or convolution operation are conducted to interpolate the ΔΣ-modulated discrete data so that the envelope of the filter output may be a sampling function of finite carrier that converges to zero at finite sampling points to prevent phase distortion of a low pass filter and a discretization error due to the sinc function and produce a smooth analog signal with less distortion in the output waveform. Accordingly, if the analog filter of the invention is applied to the acoustic equipment, the sound quality can be conspicuously enhanced as compared with the conventional acoustic equipment.

With this invention, as compared with a conventional circuit for the moving average operation or convolution operation, the number of stages of the sample hold circuits and the number of adders can be significantly reduced, thereby simplifying the configuration.

**2**B and **2**C are diagrams for explaining an operation principle of the analog filter according to the first embodiment of the invention, and especially showing a process of performing the convolution operation;

**3**B and **3**C are diagrams for explaining the operation principle of the analog filter according to the first embodiment of the invention, and especially showing the waveforms obtained through the process of performing the convolution operation;

**8**B, **8**C, **8**D, **8**E and **8**F are timing charts showing the operation timing of the analog filter according to the second embodiment of the invention;

The preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

First Embodiment

An analog filter according to a first embodiment of the invention provides an analog signal having a smoother and less distorted waveform by over-sampling in certain times, and performing the moving average or convolution operation (hereinafter referred to as convolution) on individual ΔΣ-modulated binary signal (one bit).

**1** into an analog signal, with a unit time determined by a sampling frequency f being T (=1/f).

*n *times and the first convolution operation. A sequence of numerical values as listed in the top line in **1**. If this rectangular wave is shifted by time T and added n times, a symmetrical trapezoidal wave having the upper side (n+1)T, lower side (3n−1)T, and height n is produced, as shown in

That is, 16 lines of numerical values listed downward successively from the top line in

^{2 }is produced, as shown in

^{2 }is produced, as shown in

A function as shown in

The amplitude of the quadratic curve as shown in ^{2 }is an envelope of the filter output. When the discrete data of ΔΣ-modulated signal is input into the analog filter operating in this manner, quadratic curves having the amplitudes proportional to a series of discrete input values are synthesized, each shifted by time 2nT, so that the filter output becomes a smooth quadratic interpolation curve passing respective input values.

Since the sinc function as conventionally employed converges to zero when the sampling point t goes to ±∞, to obtain correctly an interpolated value at a certain interpolation position, it was required to acquire and synthesize the sinc function waves proportional to the discrete data till t=±∞. On the contrary, the function of

Accordingly, if one interpolated value is acquired, it is needed to take into consideration only a limited number of discrete data values, resulting in the smaller processing amount. The discrete data outside a range from t=1 to 65 is not ignored in view of the processing amount or precision, though it should be essentially considered, but is not theoretically required to consider, causing no discretization error.

A configuration example of the analog filter to implement the operation principle will be described below. In **10** operates in accordance with the clock of frequency Fs that is 2n times the reference sampling frequency f to perform the over-sampling of 2n times.

An analog filter **1** of this embodiment performs the convolution operation for the output signal of the analog integrator **10**. As shown in **1** of this embodiment comprises a first convolution operation section **2** _{-1 }for making the 16-stage convolution operation (first convolution operation as shown in **2** _{-2 }for making the 16-stage convolution operation (second convolution operation as shown in **2** _{-3 }for making the two-stage convolution operation (third convolution operation as shown in

The first convolution operation section **2** _{-1 }comprises the following constitutions **11** _{-1 }to **22** _{-1}. An eight-stage sample hold (S/H) circuit **11** _{-1 }provided on the most input side of the first convolution operation section **2** _{-1 }holds the output signal of the analog integrator **10** successively in accordance with the clock of frequency Fs. Namely, the signal input into the eight-stage S/H circuit **11** _{-1 }is delayed by time T_{1}=8/Fs and then output. An analog adder **12** _{-1 }adds the input and output signals of the eight-stage S/H circuit **11** _{-1}. A ½ divider **13** _{-1 }divides by two the output signal of the analog adder **12** _{-1}. A set of processing circuit is made up of the eight-stage S/H circuit **11** _{-1}, the analog adder **12** _{-1 }and the ½ divider **13** _{-1}.

A four-stage S/H circuit **14** _{-1 }holds the output signal of the ½ divider **13** _{-1 }successively in accordance with the clock of frequency Fs. Namely, the signal input into the four-stage S/H circuit **14** _{-1 }is delayed by time T_{2}=4/Fs and then output. An analog adder **15** _{-1 }adds the input and output signals of the four-stage S/H circuit **14** _{-1}. A ½ divider **16** _{-1 }divides by two the output signal of the analog adder **15** _{-1}.

A two-stage S/H circuit **17** _{-1 }holds the output signal of the ½ divider **16** _{-1 }successively in accordance with the clock of frequency Fs. Namely, the signal input into the two-stage S/H circuit **17** _{-1 }is delayed by time T_{3}=2/Fs and then output. An analog adder **18** _{-1 }adds the input and output signals of the two-stage S/H circuit **17** _{-1}. A ½ divider **19** _{-1 }divides by two the output signal of the analog adder **18** _{-1}.

A one-stage S/H circuit **20** _{-1 }holds the output signal of the ½ divider **19** _{-1 }successively in accordance with the clock of frequency Fs. Namely, the signal input into the one-stage S/H circuit **20** _{-1 }is delayed by time T_{4}=1/Fs and then output. An analog adder **21** _{-1 }adds the input and output signals of the one-stage S/H circuit **20** _{-1}. A ½ divider **22** _{-1 }divides by two the output signal of the analog adder **21** _{-1}.

The second convolution operation section **2** _{-2 }comprises the same constitutions **11** _{-2 }to **22** _{-2 }as those of the first convolution operation section **2** _{-1}. Namely, the same numerals with different subscripts designate the corresponding constitutions. The second convolution operation section **2** _{-2 }performs the same processing for the output signal of the first convolution operation section **2** _{-1 }as the first convolution operation section **2** _{-1}.

The third convolution operation section **2** _{-3 }comprises the same constitutions, namely, a one-stage S/H circuit **20** _{-3}, an analog adder **21** _{-3 }and a ½ divider **22** _{-3}, as the last stage of the constitutions **11** _{-1 }to **22** _{-1 }provided for the first convolution operation section **2** _{-1}. Also herein, the same numerals with different subscripts designate the corresponding constitutions. The third convolution operation section **2** _{-3 }performs the same processing for the output signal of the second convolution operation section **2** _{-2 }as the last stage of the first convolution operation section **2** _{-1}.

In this manner, in the first convolution operation section **2** _{-1 }for example, four analog adders and four S/H circuits that are different in the number of stages are cascade connected, thereby repeating a processing of sampling and holding the addition output at the former stage is S/H, and adding the input and output signals of the S/H circuit as two inputs at the latter stage. Thus, the same arithmetic operation can be made as shifting the input wave by time T and adding it 2^{4}=16 times.

Similarly, in the second convolution operation section **2** _{-2}, the same arithmetic operation can be also made as shifting the input wave by time T and adding it 2^{4}=16 times. In the third convolution operation section **2** _{-3}, the same arithmetic operation can be also made as shifting the input wave by time T and adding it once in one analog adder.

Accordingly, a row of numerical values in which a series of ΔΣ-modulated waves are convoluted and synthesized are produced successively by passing the integral value of the ΔΣ-modulated signal through the analog filter **1** operating in the above manner. The analog waveform determined by this row of numerical values has the amplitude multiplied by ½n^{2 }times in a plurality of ½ dividers and has the same amplitude as the original amplitude.

As described above, using the analog filter **1** of this embodiment, over-sampling and convolution of a ΔΣ-modulated signal according to the principle as described in connection with

Also, in the analog filter **1** of this embodiment, a multi-stage convolution circuit is made up of an S/H circuit having the number of stages decreasing toward the end of each arithmetic operation section like 8-stage, 4-stage, 2-stage and 1-stage, an analog adder for adding the input and output signals of the S/H circuit, and a ½ dividers for dividing by two the output signal of the analog adder.

With a conventional circuit for the convolution operation as shown in **2** _{-1 }as shown in **2** _{-2 }is met with S/H circuits of 15 stages and four analog adders, and the third convolution operation section **2** _{-3 }is met with S/H circuits of one stage and one analog adder. Thereby, the number of stages of the S/H circuits and the number of analog adders are much smaller compared with the conventional circuit, resulting in simplified constitution.

For reference, a waveform obtained in making the over-sampling in 64 times and convolution of 32 stages is shown in

Second Embodiment

A second embodiment of the invention will be described below.

An analog filter according to the second embodiment of the invention provides an analog signal having a smoother waveform by weighting a ΔΣ-modulated binary signal (one bit signal) with a digital fundamental waveform corresponding to a predetermined sampling function as described below, and performing the convolution operation as described in the first embodiment on its output signal.

A digital fundamental waveform as shown in

The function of

In this way, the function of

A configuration example of the analog filter to implement the operation principle will be described below. In **30** converts a ΔΣ-modulated binary signal (one bit signal) into a differential digital signal of two bits. This signal converting section **30** operates in accordance with the clock of the frequency Fs that is a multiple of the reference sampling frequency f. At the output stage of the signal converting section **30**, there are provided three flip-flops **31** _{-1}, **31** _{-2 }and **31** _{-3}. Each of three flip-flops **31** _{-1}, **31** _{-2 }and **31** _{-3 }comprises 32 stages of flip-flops for holding the two-bit differential digital signal successively in accordance with the clock of frequency Fs, whereby the input signal is delayed by time T_{0}=32/Fs and output.

Four read/write memories **32** _{-1}, **32** _{-2}, **32** _{-3 }and **32** _{-4 }are connected to the output taps of the signal converting section **30** and the flip-flops **31** _{-1}, **31** _{-2 }and **31** _{-3}, respectively. That is, a first read/write memory **32** _{-1 }is connected to an output tap of the signal converting section **30**, a second read/write memory **32** _{-2 }is connected to an output tap of the first flip-flop **31** _{-1}, a third read/write memory **32** _{-3 }is connected to an output tap of the second flip-flop **31** _{-2}, and a fourth read/write memory **32** _{-4 }is connected to an output tap of the third flip-flop **31** _{-3}.

Each of the read/write memories **32** _{-1}, **32** _{-2}, **32** _{-3 }and **32** _{-4 }has an area of the capacity for storing 32 steps of the two-bit differential digital signal, whereby the input differential digital signal is written in accordance with the clock of the frequency Fs, and read in accordance with the clock of double frequency 2Fs.

Two polarity switching/data selectors **33** _{-1 }and **33** _{-2 }are provided at the output stages of the read/write memories **32** _{-1}, **32** _{-2}, **32** _{-3 }and **32** _{-4}. That is, a first polarity switching/data selector **33** _{-1 }is connected to the output stages of the first and second read/write memories **32** _{-1 }and **32** _{-2}, and a second polarity switching/data selectors **33** _{-2 }is connected to the output stages of the third and fourth read/write memories **32** _{-3 }and **32** _{-4}.

Each of the polarity switching/data selectors **33** _{-1 }and **33** _{-2 }switches the positive or negative polarity of the differential digital signal input from two read/write memories at predetermined timing, and selects any signal for output. The signal output from each of the polarity switching/data selectors **33** _{-1 }and **33** _{-2 }is input into the first and third integral type digital/analog converters **34** _{-1 }and **34** _{-3 }for making the A/D conversion, which has the integral effect.

Each of the first and third integral type digital/analog converters **34** _{-1 }and **34** _{-3 }converts the differential digital signal output from the first and second polarity switching/data selectors **33** _{-1 }and **33** _{-2 }into analog signal. Also, a second integral type digital/analog converter **34** _{-2 }converts the differential digital signal output from the first flip-flop **31** _{-1 }into analog signal.

**34** _{-1}, **34** _{-2 }and **34** _{-3}.

**31** _{-1}, to the second integral type digital/analog converter **34** _{-2}, and the sub-data 1 to 4 mean the data input or output into or from the read/write memories **32** _{-1}, **32** _{-2}, **32** _{-3 }and **32** _{-4}, respectively.

As shown in **32** _{-1 }at time t**1** in accordance with the clock of frequency Fs, read twice from the first read/write memory **32** _{-1 }at next time t**2** in accordance with the clock of double frequency 2Fs, and input as the sub-data **1** into the first polarity switching/data selector **33** _{-1}.

At next time t**3**, a signal INH is input into the first read/write memory **321** and the input/output of data is suspended. Also, at the time t**3**, data a with delay is read from the first flop-flop **31** _{-1}, and input as the main data into the second integral type digital/analog converter **34** _{-2}. And at next time t**4**, data a is read twice from the first read/write memory **32** _{-1 }in accordance with the clock of double frequency 2Fs, and input as the sub-data **1** into the first polarity switching/data selector **33** _{-1}.

Thereby, data a is input into the first polarity switching/data selector **33** _{-1 }four times at time from t**2** to t**4** in accordance with the clock of double frequency 2Fs. Then, the first polarity switching/data selector **33** _{-1}, reverses the polarity for the data a input at the second and third times, and outputs its result to the first integral type digital/analog converter **34** _{-1}. Thereby, data a is input into the first integral type digital/analog converter **34** _{-1}, in the sequence of −a, a, a and −a.

As shown in **32** _{-2 }at time t**2** in accordance with the clock of frequency Fs, read twice from the second read/write memory **32** _{-2 }at next time t**3** in accordance with the clock of double frequency 2Fs, and input as the sub-data **2** into the first polarity switching/data selector **33** _{-1}.

At next time t**4**, signal INH is input into the second read/write memory **32** _{-2}, and the input/output of data is suspended. Also, at the time t**4**, data b with delay is read from the first flop-flop **31** _{-1}, and input as the main data into the second integral type digital/analog converter **34** _{-2}. And at next time t**5**, datab is read twice from the second read/write memory **32** _{-2 }in accordance with the clock of double frequency 2Fs, and input as the sub-data **2** into the first polarity switching/data selector **33** _{-1}.

Thereby, data b is input into the first polarity switching/data selector **33** _{-1}, four times at time from t**3** to t**5** in accordance with the clock of double frequency 2Fs. Then, the first polarity switching/data selector **33** _{-1 }reverses the polarity for the data b input at the second and third times, and outputs its result to the first integral type digital/analog converter **34** _{-1}. Thereby, data b is input into the first integral type digital/analog converter **34** _{-1 }in the sequence of −b, b, b and −b.

As shown in **32** _{-3 }at time t**3** in accordance with the clock of frequency Fs, read twice from the third read/write memory **32** _{-3 }at next time t**4** in accordance with the clock of double frequency 2Fs, and input as the sub-data **3** into the second polarity switching/data selector **33** _{-2}.

At next time t**5**, signal INH is input into the third read/write memory **32** _{-3}, and the input/output of data is suspended. Also, at the time t**5**, data c with delay is read from the first flop-flop **31** _{-1}, and input as the main data into the second integral type digital/analog converter **34** _{-2}. And at next time t**6**, data c is read twice from the third read/write memory **32** _{-3 }in accordance with the clock of double frequency 2Fs, and input as the sub-data **3** into the second polarity switching/data selector **33** _{-2}.

Thereby, data c is input into the second polarity switching/data selector **33** _{-2 }four times at time from t**4** to t**6** in accordance with the clock of double frequency 2Fs. Then, the second polarity switching/data selector **33** _{-2 }reverses the polarity for the data c input at the second and third times, and outputs its result to the third integral type digital/analog converter **34** _{-3}. Thereby, data c is input into the third integral type digital/analog converter **34** _{-3 }in the sequence of −c, c, c and −c.

As shown in **32** _{-4 }at time t**4** in accordance with the clock of frequency Fs, read twice from the fourth read/write memory **32** _{-4 }at next time t**5** in accordance with the clock of double frequency 2Fs, and input as the sub-data **4** into the second polarity switching/data selector **33** _{-2}.

At next time t**6**, signal INH is input into the fourth read/write memory **32** _{-4}, and the input/output of data is suspended. Also, at the time t**6**, data d with delay is read from the first flop-flop **31** _{-1}, and input as the main data into the second integral type digital/analog converter **34** _{-2}. And at next time t**7**, data d is read twice from the fourth read/write memory **32** _{-4 }in accordance with the clock of double frequency 2Fs, and input as the sub-data **4** into the second polarity switching/data selector **33** _{-2}.

Thereby, data d is input into the second polarity switching/data selector **33** _{-2 }four times at time from t**5** to t**7** in accordance with the clock of double frequency 2Fs. Then, the second polarity switching/data selector **33** _{-2 }reverses the polarity for the data d input at the second and third times, and outputs its result to the third integral type digital/analog converter **34** _{-3}. Thereby, data d is input into the third integral type digital/analog converter **34** _{-3 }in the sequence of −d, d, d and −d.

On and after, in the same manner for the data e, f, g, . . . reading and writing the main data and the sub-data 1 to sub-data 4 are performed successively. Also, the polarity switching is made in the same manner.

Through the above process, at the timing of t**4**, for example, data row a, −a with a period of 2Fs are input into the first integral type digital/analog converter **34** _{-1}, data b with a period of Fs are input into the second integral type digital/analog converter **34** _{-2}, and data row−c, c with a period of 2Fs are input into the third integral type digital/analog converter **34** _{-3}.

A weighting analog adder **35** weights and adds the analog signals output from the integral type digital/analog converters **34** _{-1}, **34** _{-2 }and **34** _{-3}. Herein, the output signals from the first integral type digital/analog converter **34** _{-1}, the second integral type digital/analog converter **34** _{-2 }and the third integral type digital/analog converter **34** _{-3 }are weighted at a ratio of 1:8:1.

Thereby, an analog fundamental waveform having the amplitude corresponding to the value of ΔΣ-modulated binary signal is produced. For example, at the timing of t**4**, an analog waveform coping with a basic digital waveform (−a, a, **8** *b*, **8** *b*, c, −c) having the amplitudes corresponding to the data values a, b and c input into the integral type digital/analog converters **34** _{-1}, **34** _{-2 }and **34** _{-3 }is produced.

The analog filter **1** is connected at the later stage of this weighting analog adder **35**. The analog filter **1** is constituted in the same manner as shown in **35**.

As described above, the analog filter **1** of this embodiment makes interpolation so that the envelope of the filter output may be the waveform as shown in

And in this embodiment, as the preprocessing for inputting the ΔΣ-modulated signal into the analog filter **1**, the discrete data of the ΔΣ-modulated signal is processed in accordance with the basic digital waveform that is the reference of the sampling function of finite carrier as shown in

In the above embodiment, as an example of the convolution operation, after the 16-stage convolution operation is conducted twice, two-stage convolution operation is conducted. However, this invention is not limited to the above example. For example, the 16-stage convolution operation may be conducted twice, and the last two-stage convolution operation may be omitted, thereby producing relatively smooth analog waveform. Also, the two-stage convolution operation may be conducted three times, and the eight-stage convolution operation may be conducted once. Thus, a few convolution operations of arbitrary stages may be combined in any form.

In the above embodiment, the ½ divider is provided at each of the output stages of plural analog adders, but a few or all ½ dividers maybe provided collectively at one region. For example, one 1/16 divider may be provided at each of the last stages of the first and second convolution operation sections **2** _{-1 }and **2** _{-2}, or one ½n^{2 }divider may be provided at the last stage of the third convolution operation section **2** _{-3}. In this case, a set of processing circuit is made up of the S/H circuit and the analog adder.

In the above embodiment, a set of processing circuit consists of a circuit having the S/H circuits of 2^{i }stages and the analog adders, j sets of processing circuit are connected in cascade, and the number of stages for the S/H circuits of 2^{i }stages gradually decreases toward the end of each arithmetic operation section such as i=j−1, j−2, . . . , 1, 0. This invention is not limited to this example. For example, the number of stages for the S/H circuits of 2^{i }stages may gradually increase toward the end of each arithmetic operation section such as i=0, 1, . . . , j−2, j−1, or the S/H circuits may be randomly disposed.

It is to be understood that the invention is not limited to the exact details of construction, operation, exact materials, or embodiments shown and described, as various modifications and equivalents will be made without departing from the spirit and scope of the invention.

[Industrisl Applicability]

This invention is beneficial to implement an optimal analog filter for the ΔΣ-modulated output, or an analog filter with less distortion in the output waveform and of a simple construction.

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Classifications

U.S. Classification | 708/819 |

International Classification | H03H15/02, H03H17/02, H03M3/02, G06G7/02, H04B14/06, H03H11/04 |

Cooperative Classification | H03H15/02 |

European Classification | H03H15/02 |

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Apr 29, 2009 | AS | Assignment | Owner name: NSC CO., LTD., JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SAKAI, YASUE;REEL/FRAME:022610/0227 Effective date: 20090326 |

Mar 8, 2010 | REMI | Maintenance fee reminder mailed | |

Aug 1, 2010 | LAPS | Lapse for failure to pay maintenance fees | |

Sep 21, 2010 | FP | Expired due to failure to pay maintenance fee | Effective date: 20100801 |

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