|Publication number||US7085935 B1|
|Application number||US 09/668,408|
|Publication date||Aug 1, 2006|
|Filing date||Sep 22, 2000|
|Priority date||Mar 31, 2000|
|Also published as||US7013484|
|Publication number||09668408, 668408, US 7085935 B1, US 7085935B1, US-B1-7085935, US7085935 B1, US7085935B1|
|Inventors||Carl M. Ellison, Roger A. Golliver, Howard C. Herbert, Derrick C. Lin, Francis X. McKeen, Gilbert Neiger, Ken Reneris, James A. Sutton, Shreekant S. Thakkar, Millind Mittal|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (104), Non-Patent Citations (38), Referenced by (14), Classifications (11), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This is a continuation-in-part of U.S. patent application Ser. No. 09/540,613 filed Mar. 31, 2000.
1. Field of the Invention
This invention relates to microprocessors. In particular, the invention relates to processor security.
2. Description of Related art
Advances in microprocessor and communication technologies have opened up many opportunities for applications that go beyond the traditional ways of doing business. Electronic commerce (E-commerce) and business-to-business (B2B) transactions are now becoming popular, reaching the global markets at a fast rate. Unfortunately, while modem microprocessor systems provide users convenient and efficient methods of doing business, communicating and transacting, they are also vulnerable to unscrupulous attacks. Examples of these attacks include theft of data, virus, intrusion, security breach, and tampering, to name a few. Computer security, therefore, is becoming more and more important to protect the integrity of the computer systems and increase the trust of users.
Threats caused by unscrupulous attacks may be in a number of forms. Attacks may be remote without requiring physical accesses. An invasive remote-launched attack by hackers may disrupt the normal operation of a system connected to thousands or even millions of users. A virus program may corrupt code and/or data of a single-user platform.
Existing techniques to protect against attacks have a number of drawbacks. Anti-virus programs can only scan and detect known viruses. Most anti-virus programs use a weak policy in which a file or program is assumed good until proved bad. For many security applications, this weak policy may not be appropriate. In addition, most anti-virus programs are used locally where they are resident in the platform. This may not be suitable in a group work environment. Security co-processors or smart cards using cryptographic or other security techniques have limitations in speed performance, memory capacity, and flexibility. Redesigning operating systems creates software compatibility issues and causes tremendous investment in development efforts.
The features and advantages of the present invention will become apparent from the following detailed description of the present invention in which:
In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one skilled in the art that these specific details are not required in order to practice the present invention. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention.
One principle for providing security in a computer system or platform is the concept of an isolated execution architecture. The isolated execution architecture includes logical and physical definitions of hardware and software components that interact directly or indirectly with an operating system of the computer system or platform. An operating system and the processor may have several levels of hierarchy, referred to as rings, corresponding to various operational modes. A ring is a logical division of hardware and software components that are designed to perform dedicated tasks within the operating system. The division is typically based on the degree or level of privilege, namely, the ability to make changes to the platform. For example, a ring-0 is the innermost ring, being at the highest level of the hierarchy. Ring-0 encompasses the most critical, privileged components. In addition, modules in Ring-0 can also access to lesser privileged data, but not vice versa. Ring-3 is the outermost ring, being at the lowest level of the hierarchy. Ring-3 typically encompasses users or applications level and executes the least trusted code. It is noted that the level of the ring hierarchy is independent to the level of the security protection of that ring.
Ring-0 10 includes two portions: a normal execution Ring-0 11 and an isolated execution Ring-0 15. The normal execution Ring-0 11 includes software modules that are critical for the operating system, usually referred to as kernel. These software modules include primary operating system (e.g., kernel) 12, software drivers 13, and hardware drivers 14. The isolated execution Ring-0 15 includes an operating system (OS) nub 16 and a processor nub 18. The OS nub 16 and the processor nub 18 are instances of an OS executive (OSE) and processor executive (PE), respectively. The OSE and the PE are part of executive entities that operate in a secure environment associated with the isolated area 70 and the isolated execution mode. The processor nub loader 52 is a protected bootstrap loader code held within a chipset in the system and is responsible for loading the processor nub 18 from the processor or chipset into an isolated area as will be explained later.
Similarly, ring-1 20, ring-2 30, and ring-3 40 include normal execution ring-1 21, ring-2 31, ring-3 41, and isolated execution ring-1 25, ring-2 35, and ring-3 45, respectively. In particular, normal execution ring-3 includes N applications 42 1 to 42 N and isolated execution ring-3 includes K applets 46 1 to 46 K.
One concept of the isolated execution architecture is the creation of an isolated region in the system memory, referred to as an isolated area, which is protected by both the processor and chipset in the computer system. Portions of the isolated region may also be in cache memory. Access to this isolated region is permitted only from a front side bus (FSB) of the processor, using special bus (e.g., memory read and write) cycles, referred to as isolated read and write cycles. The special bus cycles are also used for snooping. The isolated read and write cycles are issued by the processor executing in an isolated execution mode when accessing the isolated area. The isolated execution mode is initialized using a privileged instruction in the processor, combined with the processor nub loader 52. The processor nub loader 52 verifies and loads a ring-0 nub software module (e.g., processor nub 18) into the isolated area. The processor nub 18 provides hardware-related services for the isolated execution.
One task of the processor nub loader 52 and processor nub 18 is to verify and load the ring-0 OS nub 16 into the isolated area, and to generate the root of a key hierarchy unique to a combination of the platform, the processor nub 18, and the operating system nub 16. The operating system nub 16 provides links to services in the primary OS 12 (e.g., the unprotected operating system), provides page management within the isolated area, and has the responsibility for loading ring-3 application modules 45, including applets 46 1 to 46 K, into protected pages allocated in the isolated area. The operating system nub 16 may also load ring-0 supporting modules.
The operating system nub 16 may choose to support paging of data between the isolated area and ordinary (e.g., non-isolated) memory. If so, then the operating system nub 16 is also responsible for encrypting and hashing the isolated area pages before evicting the page to the ordinary memory, and for checking the page contents upon restoration of the page. The isolated mode applets 46 1 to 46 K and their data are tamper-resistant and monitor-resistant from all software attacks from other applets, as well as from non-isolated-space applications (e.g., 42 1 to 42 N), drivers and even the primary operating system 12. The software that can interfere with or monitor the applet's execution is the processor nub loader 52, processor nub 18 or the operating system nub 16.
The accessible physical memory 60 includes an isolated area 70 and a nonisolated area 80. The isolated area 70 includes applet pages 72 and nub pages 74. The non-isolated area 80 includes application pages 82 and operating system pages 84. The isolated area 70 is accessible only to elements of the operating system and processor operating in isolated execution mode. The non-isolated area 80 is accessible to all elements of the ring-0 operating system and to the processor.
The normal execution ring-0 11 including the primary OS 12, the software drivers 13, and the hardware drivers 14, can access both the OS pages 84 and the application pages 82. The normal execution ring-3, including applications 42 1 to 42 N, can access only to the application pages 82. Generally applications can only access to their own pages, however, the OS typically provides services for sharing memory in controlled methods. Both the normal execution ring-0 11 and ring-3 41, however, cannot access the isolated area 70.
The isolated execution ring-0 15, including the OS nub 16 and the processor nub 18, can access to both of the isolated area 70, including the applet pages 72 and the nub pages 74, and the non-isolated area 80, including the application pages 82 and the OS pages 84. The isolated execution ring-3 45, including applets 46 1 to 46 K, can access only applet pages 72. The applets 46 1 to 46 K reside in the isolated area 70. In general, applets can only access their own pages; however, the OS nub 16 can also provides services for the applet to share memory (e.g., share memory with other applets or with non-isolated area applications).
The processor 110 represents a central processing unit of any type of architecture, such as complex instruction set computers (CISC), reduced instruction set computers (RISC), very long instruction word (VLIW), or hybrid architecture. In one embodiment, the processor 110 is compatible with an Intel Architecture (IA) processor, such as the Pentium™ series, the IA-32™ and the IA-64™. The processor 110 includes a normal execution mode 112 and an isolated execution circuit 115. The normal execution mode 112 is the mode in which the processor 110 operates in a nonsecure environment, or a normal environment without the security features provided by the isolated execution mode. The isolated execution circuit 115 provides a mechanism to allow the processor 110 to operate in an isolated execution mode. The isolated execution circuit 115 provides hardware and software support for the isolated execution mode. This support includes configuration for isolated execution, definition of an isolated area, definition (e.g., decoding and execution) of isolated instructions, generation of isolated access bus cycles, and access checking.
In one embodiment, the computer system 100 can be a single processor system, such as a desktop computer, which has only one main central processing unit, e.g. processor 110. In other embodiments, the computer system 100 can include multiple processors, e.g. processors 110, 110 a, 110 b, etc., as shown in FIG. 1C. Thus, the computer system 100 can be a multi-processor computer system having any number of processors. For example, the multi-processor computer system 100 can operate as part of a server or workstation environment. The basic description and operation of processor 110 will be discussed in detail below. It will be appreciated by those skilled in the art that the basic description and operation of processor 110 applies to the other processors 110 a and 110 b, shown in
The processor 110 may also have multiple logical processors. A logical processor, sometimes referred to as a thread, is a functional unit within a physical processor having an architectural state and physical resources allocated according to some partitioning policy. Within the context of the present invention, the terms “thread” and “logical processor” are used to mean the same thing. A multi-threaded processor is a processor having multiple threads or multiple logical processors. A multi-processor system (e.g., the system comprising the processors 110, 110 a, and 110 b) may have multiple multi-threaded processors.
The host bus 120 provides interface signals to allow the processor 110 or processors 110, 100 a, and 110 b to communicate with other processors or devices, e.g., the MCH 130. In addition to normal mode, the host bus 120 provides an isolated access bus mode with corresponding interface signals for memory read and write cycles. The isolated access bus mode is asserted on memory accesses initiated while the processor 110 is in the isolated execution mode and it is accessing memory within the isolated area. The isolated access bus mode is also asserted on instruction pre-fetch and cache write-back cycles if the address is within the isolated area address range. The isolated access bus mode is configured within the processor 110. The processor 110 responds to a snoop cycle to a cached address when the isolated access bus mode on the FSB matches the mode of the cached address.
The MCH 130 provides control and configuration of system memory 140. The MCH 130 provides interface circuits to recognize and service isolated access assertions on memory reference bus cycles, including isolated memory read and write cycles. In addition, the MCH 130 has memory range registers (e.g., base and length registers) to represent the isolated area in the system memory 140. Once configured, the MCH 130 aborts any access to the isolated area that does not have the isolated access bus mode asserted.
The system memory 140 stores system code and data. The system memory 140 is typically implemented with dynamic random access memory (DRAM) or static random access memory (SRAM). The system memory 140 includes the accessible physical memory 60 (shown in FIG. 1B). The accessible physical memory includes a loaded operating system 142, the isolated area 70 (shown in FIG. 1B), and an isolated control and status space 148. The loaded operating system 142 is the portion of the operating system that is loaded into the system memory 140. The loaded OS 142 is typically loaded from a mass storage device via some boot code in a boot storage such as a boot read only memory (ROM). The isolated area 70, as shown in
The ICH 150 represents a known single point in the system having the isolated execution functionality. For clarity, only one ICH 150 is shown. The system 100 may have many ICH's similar to the ICH 150. When there are multiple ICH's, a designated ICH is selected to control the isolated area configuration and status. In one embodiment, this selection is performed by an external strapping pin. As is known by one skilled in the art, other methods of selecting can be used, including using programmable configuring registers. The ICH 150 has a number of functionalities that are designed to support the isolated execution mode in addition to the traditional I/O functions. In particular, the ICH 150 includes an isolated bus cycle interface 152, the processor nub loader 52 (shown in FIG. 1A), a digest memory 154, a cryptographic key storage 155, an isolated execution logical processor manager 156, and a token bus interface 159.
The isolated bus cycle interface 152 includes circuitry to interface to the isolated bus cycle signals to recognize and service isolated bus cycles, such as the isolated read and write bus cycles. The processor nub loader 52, as shown in
The non-volatile memory 160 stores non-volatile information. Typically, the non-volatile memory 160 is implemented in flash memory. In one embodiment, the non-volatile memory 160 includes the processor nub 18. The processor nub 18 provides set-up and low-level management of the isolated area 70 (in the system memory 140), including verification, loading, and logging of the operating system nub 16, and the management of the symmetric key used to protect the operating system nub's secrets. The processor nub loader 52 performs some part of the setup and manages/updates the symmetric key before the processor nub 18 and the OS nub 16 are loaded. The processor nub 18 The processor nub 18 may also provide interface abstractions to low-level security services provided by other hardware. The processor nub 18 may also be distributed by the original equipment manufacturer (OEM) or operating system vendor (OSV).
The mass storage device 170 stores archive information such as code (e.g., processor nub 18), programs, files, data, applications (e.g., applications 42 1 to 42 N), applets (e.g., applets 46 1 to 46 K) and operating systems. The mass storage device 170 may include compact disk (CD) ROM 172, floppy diskettes 174, and hard drive 176, and any other storage devices. The mass storage device 170 provides a mechanism to read machine-readable media. When implemented in software, the elements of the present invention are the code segments to perform the necessary tasks. The program or code segments can be stored in a processor readable medium or transmitted by a computer data signal embodied in a carrier wave, or a signal modulated by a carrier, over a transmission medium. The “processor readable medium” may include any medium that can store or transfer information. Examples of the processor readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable programmable ROM (EPROM), a floppy diskette, a compact disk CD-ROM, an optical disk, a hard disk, a fiber optical medium, a radio frequency (RF) link, etc. The computer data signal may include any signal that can propagate over a transmission medium such as electronic network channels, optical fibers, air, electromagnetic, RF links, etc. The code segments may be downloaded via computer networks such as the Internet, an Intranet, etc.
I/O devices 175 may include any I/O devices to perform I/O functions. Examples of I/O devices 175 include a controller for input devices (e.g., keyboard, mouse, trackball, pointing device), media card (e.g., audio, video, graphics), a network card, and any other peripheral controllers.
The token bus 180 provides an interface between the ICH 150 and various tokens in the system. A token is a device that performs dedicated input/output functions with security functionalities. A token has characteristics similar to a smart card, including at least one reserved-purpose public/private key pair and the ability to sign data with the private key. Examples of tokens connected to the token bus 180 include a motherboard token 182, a token reader 184, and other portable tokens 186 (e.g., smart card). The token bus interface 159 in the ICH 150 connects through the token bus 180 to the ICH 150 and ensures that when commanded to prove the state of the isolated execution, the corresponding token (e.g., the motherboard token 182, the token 186) signs only valid isolated digest information. For purposes of security, the token should be connected to the digest memory via the token bus 180.
A Chipset Circuit to Manage a Secure Platform
The overall architecture discussed above provides a basic insight into a hierarchical executive architecture to manage a secure platform. The elements shown in
The chipset 205 is an integrated device that provides the necessary infrastructure for the isolated execution mode in the platform. In one embodiment, the chipset 205 is the input/output controller hub (ICH) 150 shown in FIG. 1C. The chipset 205 includes a chipset circuit 210. The chipset circuit 210 includes the functionalities to allow a platform to operate in a secure environment. The secure environment is associated with the isolated memory area (e.g., the isolated memory area 70 shown in
The executive entities 220 include a number of executives that are designed to operate in the secure environment. The executive entities 220 are associated with the isolated memory area 70 (FIG. 1C). The executive entities 220 include a processor executive (PE) handler 230, a PE 240, and an operating system executive (OSE) 250. The PE handier 230 handles the PE 240. The PE 240 handles the OSE 250. The OSE 250 interfaces to a subset of the operating system (OS) 260 running on the platform. As mentioned above, the PE handler 230, the PE 240, and the OSE 250 are abstract models of the processor nub loader 52, the processor nub 18, and the operating system nub 16, respectively, shown in
The initialization storage 310 is used to initialize the chipset 205 for isolated execution mode. The initialization storage is accessed by an initialization storage access signal 305. The initialization storage access signal 305 represents an input/output bus access cycle decoded to the initialization storage address as generated by one of the processors in the system (e.g., processor 110 in FIG. 1C).
The PE handler storage 320 stores PE handler data 322. The PE handler data 322 include a PE handler image 323, a PE handler cryptographic identifier 325, a PE handler size 327, and a PE handler address 329. The PE handler image 323 is to be loaded into the isolated memory area 70 after the chipset 205 is initialized. The loaded PE handler image 323 corresponds to the PE handler 230 in the executive entities 220 (FIG. 2).
The thread count storage 330 stores a thread count 332 to indicate the number of threads currently initialized for operating in the isolated execution mode. The thread count 332 is useful for a thread to know if it is the first thread to initialize the platform in the isolated execution mode and whether it is the last thread to close the isolated area. The limit comparator 335 compares the thread count 332 with high and low limits to determine if the thread count has exceeded the maximum threads. When a maximum limit is exceeded, a failure or fault condition is generated. When the thread count reaches a minimum limit (e.g., zero), the log lock storage 375 is initialized to its initial conditions. The updated thread count is one of an incremented thread count and a decremented thread count. The incremented thread count is returned when one of the threads enrolls in the isolated execution mode. The decremented thread count is returned when one of the enrolled threads withdraws from the isolated execution mode.
The mode storage 350 stores a chipset mode 352. The mode circuit 360 writes the chipset mode 352 into the mode storage 350. The chipset mode 352 indicates a mode of operation of the chipset 205. This mode of operation includes an initialization waiting mode, a PE initialization in-progress mode, a PE initialization completion mode, an OSE loaded mode, a closing mode, and a failure mode. The initialization waiting mode indicates that the chipset is waiting for initialization. The PE initialization in-progress mode indicates that the PE is being executed. The PE initialization completion mode indicates that the PE is completed. The OSE loaded mode indicates the OSE has been loaded. The closing mode indicates that the isolated execution mode is closed. The failure mode indicates that there is a failure.
The identifier log storage 370 stores cryptographic identifiers 372 1 to 372 N of the executive entities loaded in the isolated execution mode even if they are later loaded. The cryptographic identifiers 372 1 to 372 N are read-only when in lock. The log lock storage 375 stores a lock pattern 376 to indicate which of the cryptographic identifiers 372 1 to 372 N is in lock. To be “in lock” means that the corresponding identifier cannot be modified or written. The lock pattern 376 is initialized when the thread count reaches the minimum limit. The cryptographic identifiers 372 1 to 372 N are locked based on the lock pattern 376.
The platform key storage 380 stores a platform key 385. The platform key 385 is used in handling the executive entities 220. The platform key 385 is returned when the platform key storage 380 is read in an initialization waiting mode as set by the mode storage 350 which will be described later. The platform key 385 is programmed at manufacturing time to a random value 387.
The scratch storage 390 stores isolated settings 392 used to configure the isolated execution mode. The isolated settings 392 include an isolated base value, an isolated length value, and a processor executive entry address. The isolated base and length values define the isolated memory area 70, and are essentially the same as the isolated base and length values as stored in the processor 110 and other chipsets (e.g., the MCH 130 in FIG. 1C).
The status storage 395 stores a status value 396 of an isolated unlock pin 397.
Upon START, the process 400 boots up the platform and configures the platform in the isolated execution mode (Block 410). Then, the process 400 writes the chipset mode as the initialization waiting mode (Block 420). Then, the process 400 determines if the thread operation is a thread enrollment or a thread withdrawal (Block 430). If it is a thread enrollment, the process 400 enrolls the thread (Block 440). If it is a thread withdrawal, the process 400 withdraws the thread (Block 450) and is then terminated.
After the process 400 enrolls the thread, the process 400 loads the PE handler image into the isolated memory area (Block 460). The loaded PE handler image becomes the PE handler. Next, the process 400 initializes, invokes PE and OSE and write chipset mode (Block 470). Then, the process 400 is terminated.
Upon START, the process 440 accesses the enrollment storage (Block 510). The process 440 determines if the thread count has reached the high limit or if the error mode is set (Block 520). If yes, the process 440 writes the chipset mode as a failure mode (Block 530), returns the current thread count (Block 540) and is terminated. Otherwise, the process 440 increments the thread count (Block 550). The process 440 then determines if failure mode is set (Block 560). If yes, the process 440 returns the current thread count (Block 540). Otherwise, the process 440 returns incremented thread count (Block 570). The process 440 is terminated.
Upon START, the process 450 accesses the withdrawal storage (Block 610). The process 450 checks to see if the error/failure mode is set (Block 615). If yes, the process 450 returns the decrement thread count current (Block 660). The process 450 is terminated. Otherwise, the process 450 decrements the thread count (Block 620). Then, the process 450 determines if the thread count has reached a minimum limit (Block 630). If no, the process 450 returns the decremented thread count (Block 660)
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|U.S. Classification||726/2, 711/170, 711/110, 713/182, 709/250, 712/300, 713/164, 712/10|
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