|Publication number||US7087958 B2|
|Application number||US 10/771,957|
|Publication date||Aug 8, 2006|
|Filing date||Feb 3, 2004|
|Priority date||Mar 28, 2003|
|Also published as||US20040195620|
|Publication number||10771957, 771957, US 7087958 B2, US 7087958B2, US-B2-7087958, US7087958 B2, US7087958B2|
|Inventors||Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng, Hsing-Huang Hsieh|
|Original Assignee||Mosel Vitelic, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (21), Referenced by (31), Classifications (31), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority from R.O.C. Patent Application No. 092107170, filed Mar. 28, 2003, the entire disclosure of which is incorporated herein by reference.
The present invention relates to a termination structure and more particularly to a termination structure applied to trenched DMOS devices.
The DMOS (diffused MOS) device is an important power transistor widely used in high voltage systems such as power suppliers, power control devices, etc. Among many known structures of power transistors, a trenched power transistor is a notable design. Some reports note that trenched MOSFETs have better improvement than planar power MOSFETs in efficiency and integration.
Although trenched power transistors are better than planar ones, the process for forming a trenched power transistor needs more lithographic processes because a trenched power transistor has a more complex structure than a planar one. It is desirable to provide an improved process for forming trenched power transistors.
In addition, because the power transistor devices usually bear a high voltage, a termination structure is necessary for preventing electric breakdown from early happening. There are several conventional termination structures widely used, such as a local oxidation of silicon (LOCOS), a field plate, and a guard ring, etc., among which the LOCOS is the simplest. As shown in
Moreover, it is for the field oxide layer 22 as the main portion of a termination structure. As shown in
Due to the process characteristics of the LOCOS method, the field oxide layer 22 has a bird beak structure penetrating into the neighboring P-type active area 12. Not only does it affect the precision of the transistor device dimension, but also causes electric field crowding in the neighborhood. This results in the increase of leakage current and decline of the performance of the active area.
In order to solve the above problem, there have been some designs proposed.
The '929 patent can eliminate the lithographic processes applied to the polysilicon layer and used to form the field oxide layer 22. However, due to the process characteristics, the thickness of the dielectric oxide layer 53 is limited, so that it affects the efficiency of the isolation between the polysilicon gate and the source metal contact layer.
In addition, for the power transistor design, to prevent the effect of electrostatic discharge, an ESD (electrostatic discharge) device 16 is introduced as a protective method. As shown in
Embodiments of the present invention provide a new termination structure to replace the conventional field oxide layer. Not only is the termination structure formed simultaneously during the process of the power transistor, but it also prevents the electric field crowding resulting from the bird beak of the field oxide layer. The present invention solves the problems coming from the formation of the P-type active area with an implantation or thermal diffusion methods.
In accordance with an aspect of the present invention, a trenched DMOS device having a termination structure comprises a silicon substrate of a first conductive type, having a first epitaxial layer of the first conductive type and a second epitaxial layer of a second conductive type formed thereon. A DMOS trench is formed in the first epitaxial layer and the second epitaxial layer. A first trench is formed in the first epitaxial layer and the second epitaxial layer disposed close to an edge of the second epitaxial layer. The first trench is to be utilized as a main portion of the termination structure having a bottom disposed in the first epitaxial layer. A second trench is disposed between the DMOS trench and the first trench. The second trench has another bottom disposed in the second epitaxial layer adjacent to a region of the second conductive type. A gate oxide layer is disposed on the DMOS trench and the first trench. The gate oxide layer has extended portions covering an upper surface of the second epitaxial layer adjacent the DMOS trench and of the second epitaxial layer adjacent the first trench. A first polysilicon layer is formed in the DMOS trench. A second polysilicon layer is formed over the gate oxide layer in the first trench, and has another extended portion covering the upper surface of the second epitaxial layer adjacent the first trench. The second polysilicon layer has an opening to expose the gate oxide layer disposed at the bottom of the first trench to split the second polysilicon layer into two discrete parts. An isolation layer is formed on the first polysilicon layer in the DMOS trench and extended portions of the gate oxide layer adjacent the DMOS trench, on the second polysilicon layer, and on the gate oxide layer over the second epitaxial layer at the bottom of the first trench. The isolation layer has a first contact window to expose the second polysilicon layer over the second epitaxial layer and a second contact window to expose the second trench. A source metal contact layer is formed over the isolation layer and fills both the first contact window and the second contact window. The source metal contact layer has a connection with a source of the DMOS device and further having an edge beside the first contact window.
In accordance with another aspect of the invention, a semiconductor device set comprises at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and comprises a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and comprises an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features.
In some embodiments, the at least one trench-typed MOSFET and the trench-typed termination structure are formed on a DMOS device comprising an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure penetrate through the P epitaxial layer into the N epitaxial layer. The DMOS device further comprises a first P region located between the trench-typed termination structure and the trench-typed MOSFET which is adjacent to the trench-typed termination structure, at least one second P region located between the trench-typed MOSFETs, at least one N source region surrounding the trench profiles.
The conventional technology uses the field oxide layer as the termination structure. For forming the field oxide layer, there must be one lithographic process of the active area used to define the location of the field oxide layer during the manufacturing processes. Moreover, the conventional technology uses the ion implantation to define the active area. However, due to the limitation of the ion implantation, the dope concentration of the active area can be quite homogeneous.
Compared with the conventional technology, embodiments of the present invention use an isolation trench to replace the field oxide layer. The isolation trench can be formed simultaneously during the process of etching gate trenches. Therefore, a conventional lithographic process for defining the location of the field oxide layer therefore is no longer needed. In addition, by using an epitaxial layer to form an active area, the uniform dopant concentration can be obtained.
The exemplary embodiment of the invention disclosed herein is directed to a termination structure of DMOS device. In the following description, numerous details are set forth in order to provide a clear understanding of the present invention. It will be appreciated by one skilled in the art that variations of these specific details are possible while still achieving the results of the present invention. In other instance, well-known components are not described in detail in order not to unnecessarily obscure the present invention.
As illustrated in
Afterward, a thermal oxidation process is carried out to form a gate oxide layer 110. The gate oxide layer may have a thickness of about 15˜100 nm. In a preferred embodiment, the gate oxide layer 110 has a thickness of about 30˜70 nm. The bottom of the first trench 131 to be utilized as a the main part of the termination structure is located in the first epitaxial layer 100B. The bottoms of the DMOS trenches 130 are also located in the first epitaxial layer 100B.
As shown, an NPN bipolar transistor structure is formed by the N-type DMOS source 162, the P-type second epitaxial layer 10A, and the N-type first epitaxial layer 100B. Combining the bipolar transistor structure with the DMOS gate formed in the second epitaxial layer 10A, the gate oxide layer 110, and the first polysilicon layer 141, a complete DMOS transistor is formed.
Finally, referring to
As mentioned, the N-type sources 162, the P-type second epitaxial layer 10A, and the source metal contact layer 191 have the same electrical potential. By applying a driving voltage to a drain metal contact layer 192 deposited on the backside of the silicon substrate 100C and a control voltage to the first polysilicon layer 141, the operation of the DMOS device can be controlled.
In a preferred embodiment, the isolation layer 181 may be formed of doped silicate glass, and the source metal contact layer 191 may be composed of a stack of Ti, TiN, and AlSiCu alloy layers.
The above-described embodiment is based on the usage of N+ silicon substrate. Therefore, if a P+ silicon substrate is used instead, all the N-type dopants should be replaced by P-type dopants, and vice versa.
In contrast to the prior art in
The DMOS device and the termination structure shown in
Also referring to the DMOS device and the termination structure shown in
In another embodiment, as shown in
The above-described arrangements of apparatus and methods are merely illustrative of applications of the principles of this invention and many other embodiments and modifications may be made without departing from the spirit and scope of the invention as defined in the claims. For example, the shapes and sizes of the components that form the camera supporting device may be changed. The scope of the invention should, therefore, be determined not with reference to the above description, but instead should be determined with reference to the appended claims along with their full scope of equivalents.
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|U.S. Classification||257/335, 257/340, 257/334, 257/342, 257/328, 257/339, 257/338, 257/333, 257/341, 257/332, 257/329, 257/343, 257/337, 257/336, 257/330, 257/331|
|International Classification||H01L29/40, H01L29/76, H01L29/94, H01L29/78, H01L31/062, H01L21/336, H01L31/119, H01L21/76, H01L31/113|
|Cooperative Classification||H01L29/7813, H01L29/407, H01L29/402|
|European Classification||H01L29/40P6, H01L29/40P, H01L29/78B2T|
|Sep 19, 2005||AS||Assignment|
Owner name: MOSEL VITELIC, INC., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHUANG, CHIAO-SHUN;CHANG, CHIEN-PING;TSENG, MAO-SONG;ANDOTHERS;REEL/FRAME:016551/0892
Effective date: 20050902
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|Jun 27, 2013||AS||Assignment|
Owner name: PROMOS TECHNOLOGIES INC., TAIWAN
Effective date: 20120118
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