|Publication number||US7089555 B2|
|Application number||US 10/179,100|
|Publication date||Aug 8, 2006|
|Filing date||Jun 25, 2002|
|Priority date||Jun 27, 2001|
|Also published as||US20030002440|
|Publication number||10179100, 179100, US 7089555 B2, US 7089555B2, US-B2-7089555, US7089555 B2, US7089555B2|
|Inventors||Jean Louis Calvignac, Gordon Taylor Davis, Marco Heddes, Steven Kenneth Jenkins, Ross Boyd Leavens, Robert Brian Likovich, Jr.|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (54), Non-Patent Citations (24), Referenced by (30), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims the benefit of the filing date of provisional application Ser. No. 60/301,598, filed Jun. 27, 2001.
The invention relates to semaphore management subsystems and more particularly to generic ordered semaphore management subsystems and a method for managing ordered semaphores suitable for use with any multi-threaded (multi-processor) system requiring in part or in hole in line or sequential processing of a task divided and distributed among a plurality of threads or processors for later recombination.
While the invention is generic in nature and capable of use with a large variety of multi-threaded processor systems, it will be described in conjunction with a multi-threaded processor system such as the IBM Part No. IBM32NPR161EPXCAE133 Network Processor which employs a plurality of processors or threads each of which concurrently process data frames which may be from the same or different data flows. The individual threads/processors share common resources in the network processor. Semaphores defined to be associated with specific resources are used to allocate the specific resources to the individual threads as requested.
Within such a network processor several data frames are processed at the same time. Each data frame is processed by one processor/thread. Each processor/thread operates independently from all the other processors/threads. Thus, as the software (picocode) processes a data frame, the software has no knowledge of other frames which have been, are being, or will be processed. As data frames are processed, a thread may need access to a shared resource. This shared resource is shared among all threads. To allow a thread access to the resource without interference from other threads, semaphores are used. A semaphore is a mechanism which allows a processor/thread to use a resource without interference from another processor/thread. Semaphores exist in almost every multi-processor environment where multiple processors can access common resources. A semaphore is used to ensure that one and only one processor/thread has “ownership” or use of a given resource at any given time.
A network processor is a multi-processor environment with resources which can be accessed by all processors/threads. Thus, semaphores are an intricate part of network processors. As discussed above, network processors process data frames which belong to one or more data flows. Traditionally, semaphores are implemented in software using “read modify write” or “test and set” instructions. When these instructions are used as a basis to create and allocate semaphores, valuable system resources must be used. To implement a semaphore, system memory must be used. To access a semaphore, several lines of code must be executed. If these system resources were not used for semaphore implementation, they could be used for other functions or provide a performance increase by not executing extra line(s) of code.
When semaphores are implemented in software, several lines of code must be executed to access and lock the semaphore, impacting performance. If the semaphore is unavailable (locked by another thread/processor), the software would need to poll on the semaphore. This would waste valuable bandwidth on the arbitrated memory holding semaphore locks to be accessed by all threads/processors. To implement a fair semaphore access in software requires more system memory and lines of code. For example, if a semaphore is locked, the thread/processor would need to put itself in a queue waiting for access. This queue would be implemented in system memory and require software management impacting performance. This allows threads/processors to have fair access to resources.
In a software semaphore environment, multiple threads/processors cannot unlock their respective semaphores at the same time. Typically, all the semaphores are in the same system memory. Each thread/processor must arbitrate to access the memory to unlock their semaphore. This may add to the processing time of other threads/processors waiting to access the same memory to access the semaphore locks. The same is true for locking semaphores. When semaphores are implemented in software, only one semaphore can be unlocked/locked at a time since all the semaphores reside in a common area of system memory.
In the IBM Network Processor System identified above a device termed Completion Unit monitors the order in which frames or packets in a flow are processed by the threads or Dyadic Protocol Processor Units (DPPUs) and generates information used by a semaphore sub-system to control the order in which semaphores are assigned. Such systems require ordered semaphores which must perform two functions. First, the well known semaphore function, ensure that one and only one processor/thread has access to a single resource at any time. And second, ordered semaphores must ensure that the processors/threads which are processing data frames of the same data flow access the common resource in frame order, for example, an e-mail message which must be encrypted using an encryption co-processor shared among all of the processors/threads. The encryption of the data frames must occur in order to properly encrypt the message. The software would use an ordered semaphore mechanism to access the encryption co-processor.
This would ensure two things. First, only one processor/thread accesses the co-processor at a time. And second, the encryption of the data frames of the data flow (e-mail message) occurs in order. Ordered Semaphores are needed since processing time for each data frame can be different. Data frames from the same data flow will take different amounts of time to process. For example, tree searches for each data frame can take different amounts of time. Threads which share a common ALU will stall occasionally to allow the other thread to process data. Thus, frames in the same data flow being processed by different threads will attempt to access a shared resource at different times and not in data flow order. Because of this, ordered semaphores are required to ensure the shared resource is accessed in data flow order.
The Completion Unit logic block contains all the information required to put processed data frames (received from processors/threads) back in the correct order for each data flow. USPTO applications Ser. No. 09/479,028 filed Jan. 7, 2000, now issued as U.S. Pat. No. 6,633,920 and Ser. No. 09/548,906 filed Apr. 13, 2000, now issued as U.S. Pat. No. 6,977,928 incorporated herein by reference describe how the Completion Unit performs this function. Within the completion unit, linked lists of the data frames assigned to processors/threads represent the data frame order of the data flows. One linked list exists for each data flow which currently has a data frame being processed by a processor/thread. The head of the linked list is associated with a processor/thread. It is from this processor/thread that the next processed data frame is to be taken from and sent out onto the network. When the processed data frame is sent, the head of the linked list is removed and the next element of the linked list is examined; see the referenced applications for details.
The invention contemplates an ordered semaphore management subsystem and method for use in an application system which includes a plurality of shared resources each of which is controlled by a unique semaphore; a plurality of processors adapted to perform similar tasks using one or more shared resources controlled in a sequential manner by the semaphores on assigned segments of a continuous data stream; a linked list of processor labels each identifying a processor and defining the order in which the processed data is to be assembled. Each label includes, a data flow ID, a data flow head field, a data flow tail field, and a pointer field pointing to the next label in the linked list.
The subsystem includes a logic circuit responsive to the creation of a label included in the linked list for generating and encoding a predetermined state in an ordered semaphore field (OSF) corresponding to the created label. The states include:
As pointed out above the completion unit of the IBM network processor system contains all the information required to put processed data frames (received from processors/threads) back in the correct order for each data flow. By adding a two bit Ordered Semaphore Field (OSF) to each element in the linked lists of the completion unit, ordered semaphore management can be achieved. The OSF allows the Semaphore Manager/Co-processor logic block to walk the linked list(s) within the completion unit before the processed data frames are sent out onto the network. The lists can reside in the completion unit or alternatively updated copies of the lists can be provided by the completion unit to the semaphore manager subsystem.
The OSF added to the linked list elements represent one of four states: (1) this element is currently the Semaphore Head (SH), (2) this element is currently behind the Semaphore Head (BSH), (3) the SH is currently behind this element (SHB), and (4) this element has been removed from the linked list (Skip), with respect only to ordered semaphores.
When a new element (label/thread number) is loaded into the completion unit (due to a dispatch), the Ordered Semaphore Field (OSF) will be set to one of three states. The OSF can be set to indicate the element has been removed from the linked list (with respect to ordered semaphores). This is used in the case where ordered semaphores are disabled or it is known that the software will not use ordered semaphores to process the dispatched frame. If the label/thread being loaded into the completion unit is linked into an existing linked list behind an existing Semaphore Head (SH) field, the OSF is marked as BSH. If the label/thread being loaded into the completion unit is the start of a new linked list, or is being linked into an existing linked list which does not have a OSF=SH, the OSF is marked SH.
When an element is SH, this allows the Semaphore Manager/Co-processor to grant an ordered semaphore for the thread to access the protected resource. When an element is in the BSH state, the Semaphore Manager/Co-processor must wait to grant the thread access to the ordered semaphore protected resource even if the resource is available. At any time, a thread can indicate to the Semaphore Manager/Co-processor (using the reservation release command) that it no longer needs the ordered semaphore access. If this occurs when the thread is the SH, the two bit field is changed to indicate this element is currently SHB, and the next element which has not been removed from the linked list (with respect to ordered semaphores) is marked as the SH.
If the Semaphore Manager/Co-processor, in response to the reservation release command, indicates that a particular thread no longer needs the ordered semaphore access and the thread is currently BSH, the element will be marked Skip and removed from the linked list with respect to ordered semaphores. When the semaphore head reaches this thread, the semaphore head will simply skip to the next element (thread) in the list. By adding additional Ordered Semaphore Fields, more than one ordered semaphore can be supported per data flow. For example, consider adding two Ordered Semaphore Fields to each element within the completion unit. The software can be designed to access two different resources, or the same resource twice, using Ordered Semaphores. Again, the additional logic to the completion unit interface logic block is minimal if the function is included in the completion unit logic block.
The Semaphore Manager/Co-processor does not add or remove labels/thread numbers from the linked lists within the completion unit. The Semaphore Manager/Co-processor can mark labels/thread numbers as Skip. This allows the thread to continue processing without having to access the ordered semaphore. The “Reservation Release” command of the Semaphore Coprocessor/Manager can mark a label/thread as “Skip”. When the thread in front releases the ordered semaphore, the ordered semaphore head will pass to the thread behind the thread marked “Skip”. The Semaphore Manager/Co-processor is simply walking the pre-existing linked lists within the completion unit (if they are included in the completion unit logic block) to achieve ordered semaphore operation. The OSF can be used to mark the associated label/thread number as “removed” from the linked list with respect to ordered semaphores by setting the OSF to Skip. The label/thread numbers remain in linked lists to support the enqueue of processed data frames. The “Reservation Release” or “skip” marking is non-blocking on every thread. Thus, threads performing “Reservation Release” commands do not wait to become the head of the ordered semaphore queue before completing the instruction. This increases system performance by reducing processing time.
Each of the processors 13-1–13-n includes a semaphore coprocessor 13 p which interfaces a hardware semaphore manager subsystem 16 constructed according to the invention. The semaphore subsystem 16 is implemented in hardware and interfaces with, for example, the Dyatic Protocol Processor Unit (DPPU) of the using processing system. Each DPPU contains four threads which can each process one data frame. Each DPPU has one Semaphore Co-Processor associated with it. The threads in a given DPPU interface to the one Semaphore Co-Processor within the DPPU. The multiple Semaphore Co-Processors all communicate with the central Semaphore Manager subsystem. The Semaphore Manager subsystem 16 contains all of the tables and control logic to lock, unlock, and arbitrate for semaphores. The semaphore manager 16 communicates with the completion unit 14 over a bus 17.
Only one processor instruction is executed to lock a semaphore, and only one processor instruction is executed to unlock a semaphore. This saves instruction memory and processing time when compared to software implementations of semaphores. An unlock instruction from a thread executes immediately. Nothing can block unlock instructions within the Semaphore Manager subsystem, including other unlock instructions from other threads. When semaphores are implemented in software, only one semaphore can be unlocked at a time since all the semaphores reside in a common area of system memory.
Fairness algorithms can be implemented in the Hardware Semaphore Manager subsystem. This provides fairness of access to a semaphore when multiple threads/processors request access to the same semaphore. This eliminates the need for software and system memory to be utilized to implement fairness algorithms. This increases performance by reducing frame processing time and instruction memory utilization, and does not use any system memory.
The Hardware Semaphore Manager subsystem contains the semaphores. Each semaphore is an N bit value. For example, each semaphore could be 32 bits. This allow 2^32 resources to be managed by the Semaphore Manager. Since the Semaphore Manager subsystem is generic and designed to be used by a wide variety of systems, it is the responsibility of the using system programmer to attach a meaning to a semaphore. That is, the Semaphore Manager does not know what a Semaphore represents. It is just a string of 32 bits. Semaphores can be seen as having 32-bit address space and the programmer can map this to anything, like the Tree Search Memory, the Data Store, the Embedded PowerPC, etc. There are two advantages here. First, no system memory is used for semaphore management. Second, the Hardware Semaphore Manager implementation is generic with respect to the number of and types of system resources which must be managed by semaphores. As the Network Processor evolves and shared resources are added or removed, the Semaphore Manager does not need to change. The Hardware Semaphore Co-processor and Manager does not use any system memory. This eliminates the need for memory accesses, and allows the memory bandwidth to be used for other functions.
A semaphore can be locked when a software thread issues a single command “Semaphore Lock” (Sem_Lock) with two parameters. The first parameter is the “Semaphore Value” (Sem_Val). This is, for example, a 32 bit value which the thread wishes to lock. The second parameter is the “Timeout Enable” (Timeout_Enable) bit. When the Timeout Enable bit is set and the requested semaphore is already locked by a different thread, the Semaphore Lock command will terminate without locking the semaphore.
In the preferred embodiment, each thread has an assigned register in the semaphore value storage and is thus identified as the source of the semaphore value requested. Alternatively, the requested semaphore value could be placed in any available register along with a thread or flow ID.
The non-winning threads at block 406 loop back to block 404 while the semaphore request from the winning thread is examined 407 in the semaphore value storage to determine if that semaphore value is currently locked. If the semaphore value is not locked it is examined in block 408 to determine if the request is ordered. If the request is ordered, the thread is removed from the ordered queue by sending a Pop signal 409 and the semaphore value requested is locked 410 for thread N. If the request was not ordered the requested semaphore value is locked for thread N 410 and in either case the operation for thread N is complete 411.
If the locked semaphore value requested by thread N is already locked by thread N 412, a lock same semaphore value error for thread N is generated 413 and the operation completes at 411. If the requested semaphore value 412 was not locked by thread N the timeout bit is examined 414 and if it is not set it loops back to 404 via C. If it is set a signal is generated for thread N indicating that the requested semaphore was not available 415 and the operation completes 411.
When a thread completes an operation with a resource controlled by a semaphore it sends a semaphore unlock command to the semaphore manager,
When thread N exits (processing is complete for the data frame) 601
When the software on thread N issues a reservation release command 701
The completion unit in the referenced IBM network processor employs a linked list(s) of labels for managing the reordering of data frames processed by the different threads. The label illustrated in
Applicants have modified the label of the referenced IBM network management system by adding a two bit ordered semaphore field (OSF) 806 to the label. This field defines one of four states (00, 01, 10 & 11) that a thread enabled for ordered semaphores can assume. A first state SH (which can be occupied by only one thread in a linked list of 800's), indicates that the thread is currently the semaphore head. A second state BSH indicates that the thread is currently behind the semaphore head. A third state, SHB indicates that the SH is currently behind the thread. And the fourth state Skip indicates that the thread has been removed (but only with respect to ordered semaphores) from the linked list. How these states are applied and managed will become apparent from the description of
The semaphore manager needs access to the linked list(s) of labels. In those instances where the application system allows access, the logic necessary to manage the OSF (which is the case with the IBM network system) can be achieved through the completion unit interface logic 26. If access is not available then the application system needs to make updated copies of the linked list(s) available to the interface logic 26. The location of the linked list(s) is not critical to the invention and in the descriptions which follow it will be assumed that the application system allows the semaphore manager access to the linked list(s) via the interface 26.
The flow diagram of
If block 902 is negative, block 907 determines if the enqueue data flow head was set to one when the label was written. If it was, the OSF is set to SHB 908. If block 907 is negative, block 909 determines if the OSF of the old tail was SHB and sets the OSF of the label to SHB 908. If block 909 is negative the label OSF is set to Skip 910.
When a Pop command (
When the completion unit receives a data flow enqueue command from a thread
The foregoing is illustrative of the present invention and is not to be construed as limiting the invention. While several embodiments of this invention have been described in detail, those skilled in this art will readily appreciate that many modifications are possible without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined by the claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and structural functional equivalents thereof. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the claims appended hereto.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4316245 *||Dec 7, 1978||Feb 16, 1982||Compagnie Honeywell Bull||Apparatus and method for semaphore initialization in a multiprocessing computer system for process synchronization|
|US4805106||Jul 9, 1987||Feb 14, 1989||American Telephone And Telegraph Company, At&T Bell Laboratories||Method of and arrangement for ordering of multiprocessor operations in a multiprocessor system with redundant resources|
|US4907228||Sep 4, 1987||Mar 6, 1990||Digital Equipment Corporation||Dual-rail processor with error checking at single rail interfaces|
|US5142632||May 10, 1989||Aug 25, 1992||U.S. Philips Corporation||Control unit for processing instruction using chained processing modules by providing downstream flow of operative commands and upstream validation information|
|US5159686||Mar 7, 1991||Oct 27, 1992||Convex Computer Corporation||Multi-processor computer system having process-independent communication register addressing|
|US5233701||Mar 29, 1989||Aug 3, 1993||Nec Corporation||System for managing interprocessor common memory|
|US5261106||Dec 13, 1991||Nov 9, 1993||S-Mos Systems, Inc.||Semaphore bypass|
|US5276886||Oct 11, 1990||Jan 4, 1994||Chips And Technologies, Inc.||Hardware semaphores in a multi-processor environment|
|US5339443||Dec 17, 1992||Aug 16, 1994||Sun Microsystems, Inc.||Arbitrating multiprocessor accesses to shared resources|
|US5485593||Mar 3, 1994||Jan 16, 1996||Northern Telecom Limited||Data structure access control circuit and method utilizing tag bits indicating address match and memory fullness conditions|
|US5548780||Jul 21, 1994||Aug 20, 1996||Apple Computer, Inc.||Method for semaphore communication between incompatible bus locking architectures|
|US5613139||May 11, 1994||Mar 18, 1997||International Business Machines Corporation||Hardware implemented locking mechanism for handling both single and plural lock requests in a lock message|
|US5664092||Sep 20, 1995||Sep 2, 1997||National Instruments Corporation||System and method for performing locked test and set operations in an instrumentation system|
|US5675829||Jul 7, 1995||Oct 7, 1997||Sun Microsystems, Inc.||Method and apparatus for coordinating data transfer between hardware and software by comparing entry number of data to be transferred data to entry number of transferred data|
|US5696939||Sep 29, 1995||Dec 9, 1997||Hewlett-Packard Co.||Apparatus and method using a semaphore buffer for semaphore instructions|
|US5734909||Sep 1, 1995||Mar 31, 1998||International Business Machines Corporation||Method for controlling the locking and unlocking of system resources in a shared resource distributed computing environment|
|US5842018||Jun 6, 1995||Nov 24, 1998||Microsoft Corporation||Method and system for referring to and binding to objects using identifier objects|
|US5852731||Sep 29, 1997||Dec 22, 1998||International Business Machines Corporation||Computer program product for synchronizing static variable initialization and reference under a multi-threaded computer environment|
|US5862180||Feb 1, 1997||Jan 19, 1999||Heinz; Gary L.||Differential encoding of self-clocking data streams|
|US5864653||Dec 31, 1996||Jan 26, 1999||Compaq Computer Corporation||PCI hot spare capability for failed components|
|US5893157||May 28, 1997||Apr 6, 1999||International Business Machines Corporation||Blocking symbol control in a computer system to serialize accessing a data resource by simultaneous processor requests|
|US5901308||Mar 18, 1996||May 4, 1999||Digital Equipment Corporation||Software mechanism for reducing exceptions generated by speculatively scheduled instructions|
|US6018785||Mar 18, 1996||Jan 25, 2000||Cypress Semiconductor Corp.||Interrupt-generating hardware semaphore|
|US6026427||Nov 21, 1997||Feb 15, 2000||Nishihara; Kazunori||Condition variable to synchronize high level communication between processing threads|
|US6029190||Sep 24, 1997||Feb 22, 2000||Sony Corporation||Read lock and write lock management system based upon mutex and semaphore availability|
|US6070254||Oct 17, 1997||May 30, 2000||International Business Machines Corporation||Advanced method for checking the integrity of node-based file systems|
|US6079013||Apr 30, 1998||Jun 20, 2000||International Business Machines Corporation||Multiprocessor serialization with early release of processors|
|US6105085||Dec 26, 1997||Aug 15, 2000||Emc Corporation||Lock mechanism for shared resources having associated data structure stored in common memory include a lock portion and a reserve portion|
|US6108756 *||Jan 17, 1997||Aug 22, 2000||Integrated Device Technology, Inc.||Semaphore enhancement to allow bank selection of a shared resource memory device|
|US6119246||Mar 31, 1997||Sep 12, 2000||International Business Machines Corporation||Error collection coordination for software-readable and non-software readable fault isolation registers in a computer system|
|US6122713||Jun 1, 1998||Sep 19, 2000||National Instruments Corporation||Dual port shared memory system including semaphores for high priority and low priority requestors|
|US6125401||Mar 28, 1996||Sep 26, 2000||International Business Machines Corporation||Server detection of client process termination|
|US6128706||Feb 3, 1998||Oct 3, 2000||Institute For The Development Of Emerging Architectures, L.L.C.||Apparatus and method for a load bias--load with intent to semaphore|
|US6131094||Apr 24, 1998||Oct 10, 2000||Unisys Corp.||Method for performing asynchronous writes to database logs using multiple insertion points|
|US6134579||Aug 15, 1997||Oct 17, 2000||Compaq Computer Corporation||Semaphore in system I/O space|
|US6134619||Jun 3, 1999||Oct 17, 2000||Intel Corporation||Method and apparatus for transporting messages between processors in a multiple processor system|
|US6154847||Sep 1, 1994||Nov 28, 2000||International Business Machines Corporation||Method and system for performing resource updates and recovering operational records within a fault-tolerant transaction-oriented data processing system|
|US6161169||Aug 22, 1997||Dec 12, 2000||Ncr Corporation||Method and apparatus for asynchronously reading and writing data streams into a storage device using shared memory buffers and semaphores to synchronize interprocess communications|
|US6173313||Jun 24, 1998||Jan 9, 2001||Oracle Corporation||Methodology for hosting distributed objects at a predetermined node in a distributed system|
|US6182108||Jan 31, 1995||Jan 30, 2001||Microsoft Corporation||Method and system for multi-threaded processing|
|US6199094||Jun 5, 1998||Mar 6, 2001||International Business Machines Corp.||Protecting shared resources using mutex striping|
|US6594736 *||Aug 15, 2000||Jul 15, 2003||Src Computers, Inc.||System and method for semaphore and atomic operation management in a multiprocessor|
|US6839811 *||Mar 7, 2002||Jan 4, 2005||Fujitsu Limited||Semaphore management circuit|
|EP0953903A2||Feb 10, 1999||Nov 3, 1999||International Computers Ltd.||Semaphore for a computer system|
|EP1033654A1||Mar 1, 1999||Sep 6, 2000||Sony International (Europe) GmbH||Buffered communication between entities operating at different data rates|
|JP2001005694A||Title not available|
|JP2001022720A||Title not available|
|JPH0944376A||Title not available|
|JPH1139176A||Title not available|
|JPH04361340A||Title not available|
|JPH08329019A||Title not available|
|JPH11231123A||Title not available|
|JPH11272480A||Title not available|
|WO1996003697A1||Jul 20, 1995||Feb 8, 1996||Apple Computer, Inc.||Method for semaphore communication between incompatible bus locking architectures|
|1||Chung Wu Chaio et al., "The Design and Implementation of a Distributed Semaphore Facility: DISEM", Proceedings of the National Science Council, Republic of China, Part A, vol. 19, No. 4, Jul. 1995, pp. 319-320.|
|2||D. Scholefield, "Proving Properties of Real-Time Semaphores", Science of Computer Programming, vol. 24, No. 2, Apr. 1995, pp. 159-181.|
|3||D. Weiss, "Shared Bus Semaphore Detector Proposal", Motorola Technical Developments, vol. 3, Mar. 1983, pp. 74-78.|
|4||E. Chang, "N-Philosophers: an Exercise in Distributed Control", Computer Networks vol. 4, No. 2,, Apr. 1980, pp. 71-76.|
|5||Heng Liao et al., "Hardware Support for Process Synchronization Algorithms", Mini-Micro Systems, vol. 16, No. 9, Sep. 1995, pp. 7-13.|
|6||IBM Technical Disclosure Bulletin No. 9. Feb. 1991, "System Support for Multiprocessing Without an Atomic Storage", pp. 18-23.|
|7||IBM Technical Disclosure Bulletin vol. 30, No. 3, Aug. 1987, p. 1203, "Non-Atomic (Ordered) Semaphore Operations".|
|8||IBM Technical Disclosure Bulletin vol. 30, No. 5, Oct. 1987, "Fast Method for Simultaneous Exclusive Table Modifications", pp. 348-350.|
|9||IBM Technical Disclosure Bulletin vol. 33, No. 4, Sep. 1990, "Store Purge Pipeline for Mid-Range Processor", pp. 299-301.|
|10||IBM Technical Disclosure Bulletin vol. 36, No. 6A, Jun. 1993, "Emulator DosExit Processing for Reporting Errors", pp. 255-256.|
|11||IBM Technical Disclosure Bulletin vol. 37, No. 06A, Jun. 1994, "Shared Memory Cluster-A Scalable Multiprocessor Design", pp. 503-507.|
|12||IBM Technical Disclosure Bulletin vol. 37, No. 12, Dec. 1994, "Error Handler Installation Procedure", pp. 239-240.|
|13||IBM Technical Disclosure Bulletin vol. 38 No. 4, Apr. 1995, "Hardware Contention Serialization Algorithm", pp. 73-77.|
|14||J. Milde et al., "Realization of Synchronization Tools and their Efficiency in the Multiprocessor System M5PS", 10<SUP>th </SUP>IMACS World Congress on System Simulation and Scientific Computation, vol. 1, 1982, pp. 333-335.|
|15||J. Thornley et al., "Monotonic counters: a New Mechanism for Thread Synchronization", Proceedings 14<SUP>th </SUP>International Parallel and Distributed Processing Symposium, IPDPS 2000, pp. 573-582.|
|16||K. C. Tai et al., "VP: A New Operation for Semaphores", Operating Systems Review, vol. 30, No. 3, Jul. 1996, pp. 5-11.|
|17||Mei Chen Chia et al., "A Resource Synchronization Protocol for Multiprocessor Real-Time Systems", Proceedings of the 1994 International Conference on Parallel Processing, Pt. vol. 3, 1994, pp. 159-162.|
|18||N. Marovac, "Interprocess Synchronization and Communication in Distributed Architectures", 3<SUP>rd </SUP>InternaTional Conf. On Computer Science) Chile, 1983 pp. 1-16.|
|19||N. Marovac, "On Interprocess Interaction in Distributed Architectures", Computer Architecture News vol. 11, No. 4, Sep. 1983, pp. 17-22.|
|20||N. Wait, "VME-a Microcomputer Bus for Europe", New Electronics vol. 15, No. 16,Aug. 17, 1992, pp. 57-58.|
|21||P. Bohannon et al., "Recoverable User-Level Mutual Exclusion", Proceedings, 7<SUP>th </SUP>IEEE Symposium on Parallel and Distributed Processing (Cat. No. 95TB8131), 1995, pp. 293-301.|
|22||Research Disclosure No. 317, Sep. 1990, "Improved Error Detection Using MP Fields".|
|23||Research Disclosure, Aug. 2000, p. 1442, article 436131, "User lever writing to a pinned kernel buffer in an SMP system".|
|24||T. Balph, "Interprocessor Communication in a Tightly coupled Multiple Processor Architecture", Second Annual Phoenix Conference on Computers and Communications, 1983 Conf. Proceedings pp. 21-25.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7143414 *||Sep 19, 2002||Nov 28, 2006||International Business Machines Corporation||Method and apparatus for locking multiple semaphores|
|US7305446 *||Nov 3, 2003||Dec 4, 2007||International Business Machines Corporation||Method and system for processing ingress messages for a state based application associated with a network processor|
|US7437535 *||Nov 1, 2004||Oct 14, 2008||Applied Micro Circuits Corporation||Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller|
|US7478130 *||Dec 5, 2003||Jan 13, 2009||International Business Machines Corporation||Message processing apparatus, method and program|
|US7797463 *||Jun 30, 2005||Sep 14, 2010||Intel Corporation||Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications|
|US7844585 *||Aug 17, 2007||Nov 30, 2010||International Business Machines Corporation||Method, system, and program for managing locks and transactions|
|US7870111||Jul 13, 2007||Jan 11, 2011||International Business Machines Corporation||Method, system, and program for lock and transaction management|
|US8161018||Jun 26, 2008||Apr 17, 2012||International Business Machines Corporation||Managing locks and transactions|
|US8200643||Dec 6, 2010||Jun 12, 2012||International Business Machines Corporation||Lock and transaction management|
|US8429144 *||Jul 16, 2010||Apr 23, 2013||International Business Machines Corporation||Interprocess communication using a single semaphore|
|US8495131||Oct 8, 2002||Jul 23, 2013||International Business Machines Corporation||Method, system, and program for managing locks enabling access to a shared resource|
|US8527456 *||Mar 28, 2012||Sep 3, 2013||International Business Machines Corporation||Interprocess communication using a single semaphore|
|US8719829||Feb 4, 2010||May 6, 2014||International Business Machines Corporation||Synchronizing processes in a computing resource by locking a resource for a process at a predicted time slot|
|US8768905||Mar 12, 2012||Jul 1, 2014||International Business Machines Corporation||Managing locks and transactions|
|US9342379 *||Jan 21, 2011||May 17, 2016||Wind River Systems, Inc.||Lock free acquisition and release of a semaphore in a multi-core processor environment|
|US20030061259 *||Sep 19, 2002||Mar 27, 2003||International Business Machines Corporation||Method and apparatus for locking multiple semaphores|
|US20040068563 *||Oct 8, 2002||Apr 8, 2004||International Business Machines Corporation||Method, system, and program for managing locks enabling access to a shared resource|
|US20040202165 *||Dec 5, 2003||Oct 14, 2004||International Business Machines Corporation||Message processing apparatus, method and program|
|US20050114451 *||Nov 3, 2003||May 26, 2005||International Business Machines Corporation||State based ingress packet selection mechanism for a packet processing system in a network processor|
|US20070005810 *||Jun 30, 2005||Jan 4, 2007||William Halleck||Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications|
|US20070282839 *||Jul 13, 2007||Dec 6, 2007||International Business Machines Corporation||Method, system, and program for lock and transaction management|
|US20070282966 *||Aug 17, 2007||Dec 6, 2007||International Business Machines Corporation||Method, system, and program for managing locks and transactions|
|US20080263549 *||Jun 26, 2008||Oct 23, 2008||International Business Machines Corporation||Managing locks and transactions|
|US20090172686 *||Oct 9, 2008||Jul 2, 2009||Chen Chih-Ho||Method for managing thread group of process|
|US20100229174 *||Feb 4, 2010||Sep 9, 2010||International Business Machines Corporation||Synchronizing Resources in a Computer System|
|US20110078126 *||Dec 6, 2010||Mar 31, 2011||International Business Machines Corporation||Method, system, and program for lock and transaction management|
|US20120016855 *||Jul 16, 2010||Jan 19, 2012||International Business Machines Corporation||Interprocess communication using a single semaphore|
|US20120185875 *||Mar 28, 2012||Jul 19, 2012||International Business Machines Corporation||Interprocess communication using a single semaphore|
|US20120192194 *||Jan 21, 2011||Jul 26, 2012||Raymond Richardson||Lock Free Acquisition and Release of a Semaphore in a Multi-Core Processor Environment|
|CN101751293B||Dec 16, 2008||Oct 30, 2013||智邦科技股份有限公司||Method for managing thread group of program|
|U.S. Classification||718/100, 718/104, 710/200|
|International Classification||H04J1/16, G06F9/46, G06F12/00|
|Sep 3, 2002||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CALVIGNAC, JEAN LOUIS;DAVIS, GORDON TAYLOR;HEDDES, MARCO;AND OTHERS;REEL/FRAME:013250/0589;SIGNING DATES FROM 20020710 TO 20020828
|Mar 15, 2010||REMI||Maintenance fee reminder mailed|
|Aug 8, 2010||LAPS||Lapse for failure to pay maintenance fees|
|Sep 28, 2010||FP||Expired due to failure to pay maintenance fee|
Effective date: 20100808