|Publication number||US7093206 B2|
|Application number||US 10/690,238|
|Publication date||Aug 15, 2006|
|Filing date||Oct 21, 2003|
|Priority date||Oct 21, 2003|
|Also published as||US20050086615|
|Publication number||10690238, 690238, US 7093206 B2, US 7093206B2, US-B2-7093206, US7093206 B2, US7093206B2|
|Inventors||Minakshisundaran B. Anand, Matthew S. Angyal, Alina Deutsch, Ibrahim M. Elfadel, Gerard V. Kopcsay, Barry J. Rubin, Howard H. Smith|
|Original Assignee||International Business Machines Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (7), Non-Patent Citations (1), Referenced by (28), Classifications (9), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention is related to circuit design systems and more particularly to computer aided design (CAD) systems for designing integrated circuits (ICs) operating over a wide frequency band and with circuit interconnects that might experience transmission line effects.
2. Background Description
Sets of software programs are well known in the art as computer aided design (CAD) tools. Typical CAD tools include automatic layout tools, timing analysis tools, logic synthesis tools, and so forth. In addition, a CAD tool may include electromagnetic (EM) field solvers (also known as parameter extractors) and circuit simulators for circuit conductor (interconnect) analysis and design. Integrated circuit (IC) designers have found CAD tools invaluable for designing, analyzing and verifying complex ICs and IC chip designs, such as microprocessors, microcontrollers, communications circuits and the like.
Providing an acceptable wide-band conductor description requires an accurate description of the particular conductor, e.g., its geometry and construction materials. This information may be available to the semiconductor process technologist but usually is not passed to the circuit designer. Instead, the circuit designer receives a set of ground rules that describes a range of results based on those conductor properties, e.g., capacitance/resistance/inductance per unit length or per unit area. These lump values at best provide rule of thumb design guidance and do not lend themselves to accurate wide-band electrical circuit characterizations of high-performance electrical interconnect structures.
Designers have used EM field solvers to compute conductor electrical properties, such as capacitance and inductance, from conductor geometric and physical specifications. Then, the designer can use the EM field solver results in a circuit simulator to simulate the transient or AC response, i.e., how the particular circuit devices connected by and driving the conductors respond to excitatory input signals. The excitatory input signals can be modeled to include either or both wanted and unwanted input signals, e.g., a driving logical signal such as from another such circuit, and noise signals, such as electromagnetic interference from the neighboring conductors and/or coupled noise from adjacent lines (cross talk).
For circuit signal stability the circuit model must have a valid low frequency or DC response, as well as an acceptable very high frequency transient response, e.g., to 100 GigaHertz (100 GHz) and beyond. This complicates circuit design because in addition to active element models that are accurate over the expected operating frequency range, either the circuit model must somehow accommodate wide-band models for on-chip conductors or different conductor models must be employed at each of a number of points across the frequency spectrum to accommodate the full range of conductor characteristics. Modeling conductors across this range requires a very-high level of expertise in computational models for electromagnetism that even the best IC designers do not normally have. See, e.g., Alina Deutsch et al., “On-Chip Wiring Design Challenges for Gigahertz Operation,” Proceedings of The IEEE, Vol. 89, No. 4, April 2001, pp. 529–555.
Thus, there is a need for electrical circuit conductor descriptions that are valid over a very wide range of operating frequencies and in particular there is a need for such conductor descriptions in circuit design.
It is a purpose of the invention to facilitate electrical circuit interconnect design for optimal circuit performance;
It is another purpose of the invention to bridge the gap between semiconductor process information and semiconductor circuit design information;
It is yet another purpose of the invention to provide IC designers with the most accurate semiconductor process parameter descriptions;
It is yet another purpose of the invention to avail integrated circuit (IC) designers with the best available expertise and practices of computational electromagnetism for interconnect modeling and analysis.
The present invention relates to a computer aided design (CAD) system. A template generation engine generates templates from interconnect configuration files. A field solver generates wide band passive element relationships from the templates. A circuit builder generates circuit description files from device technology models and from wide band passive element relationships. A simulator simulates circuit responses for transmission line models from the circuit description files. Interconnect configuration files may be generated by a geometry and material definition module that receives process description data from a designer.
The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:
Turning now to the drawings and, more particularly,
Process variation selection is provided in a back end of the line (BEOL) description file 102, which may be altered interactively, e.g., through a graphical user interface (GUI) as displayed on a computer monitor (not shown). A user input file 104 (e.g., a collection of files, interactively input through the GUI, or both) includes interconnect parameter selections in addition to normal circuit topography and operating parameters. Device (transistor, junction capacitance and etc.) models are contained within a device technology model file 106 and transmission line loads are selected, defined and modeled in a transmission line macromodel file 108. The BEOL description file 102 and user input file 104 are inputs to a geometry and material definition module 110. The geometry and material definition module 110 combines selections from the BEOL description file 102 and user input file 104 to generate an interconnect configuration. A template generation engine 112 receives the interconnect configuration from the material definition module 110 and generates individual interconnect definitions for a circuit being simulated. A field solver 114 generates a transient interconnect model, e.g., a three dimensional (3D) interconnect model. A circuit builder 116 combines device models from device technology model file 106 with the interconnect model to generate a complete circuit model, e.g., a Spice simulation input file. Transmission line macromodels 108 pass through application program interface (API) 118 to a simulator 120. Simulator 120 simulates the complete circuit driving a load provided by the transmission line macromodels 108. Simulator results 122 may be provided in a printout or displayed at the GUI.
Advantageously, the present invention provides a user-friendly, reliable computing environment that facilitates characterizing and optimizing interconnect structures, especially on-chip BEOL wiring structures. Technologists and designers are graphically interfaced to a full BEOL stack description for modeling and analyzing on-chip wiring structures. This full BEOL stack description may be embodied in a data file that can be created, shared, viewed, and edited through a GUI by any tool user. Further, since each data file is common to a particular technology definition, designers can evaluate circuit performance in planned semiconductor technologies as the technologies are being defined.
In addition, the present invention improves evaluating, modeling, designing, and verifying electrical circuit interconnects for a broad range of applications, especially for microprocessors, application specific integrated circuits (ASICs), radio frequency circuits, and semiconductor memories. Further the present invention does not require a domain expert to generate electrical circuit interconnects models. So, designers can evaluate electrical circuit interconnects over a very wide band of operating frequencies. Correspondingly, technologists can graphically evaluate how process options and parameter changes affect circuit electrical parameters. Process data may be formatted to allow semiconductor process engineers to accurately access IC interconnect structure performance parameters, such as wire delay, slew, and crosstalk. Thus, semiconductor process engineers can tune the semiconductor process parameters to meet specific electrical performance criteria. As a result, circuit interconnects models are consistent and accurate over whole regions of interconnect parameter space. Circuit netlists can be generated for simulation based on an equivalent synthesized circuit representation of the frequency-dependent behavior. The netlists may be parameterized netlists in a format suitable for other CAD tools. Thus, the present invention provides a single tool with three technology facets seamlessly integrated into a graphical interface. The single tool includes electrical wiring structure parameter extraction with three-dimensional full wave electromagnetic analysis, nonlinear circuit simulation, and on-chip transmission line modeling.
While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.
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|U.S. Classification||716/115, 703/14, 716/136|
|International Classification||G06F9/455, G06F19/00, G06G7/62, G06F17/50|
|Oct 30, 2003||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:ANAND, MINAKSHISUNDARAN B.;ANGYAL, MATTHEW S.;DEUTSCH, ALINA;AND OTHERS;REEL/FRAME:014089/0464;SIGNING DATES FROM 20031010 TO 20031017
|Mar 22, 2010||REMI||Maintenance fee reminder mailed|
|Aug 15, 2010||LAPS||Lapse for failure to pay maintenance fees|
|Oct 5, 2010||FP||Expired due to failure to pay maintenance fee|
Effective date: 20100815