|Publication number||US7096451 B2|
|Application number||US 10/605,103|
|Publication date||Aug 22, 2006|
|Filing date||Sep 9, 2003|
|Priority date||Sep 9, 2003|
|Also published as||US20050055660|
|Publication number||10605103, 605103, US 7096451 B2, US 7096451B2, US-B2-7096451, US7096451 B2, US7096451B2|
|Inventors||Alice L. Donaldson, Jason L. Frankel, John A. Ludwig, Kenneth A. Papae, Rafael Perez-Acevedo, C. Timothy Ryan, Paul R. Walling|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (28), Non-Patent Citations (1), Referenced by (3), Classifications (6), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to integrated circuit design, and more particularly, to generation of a mesh plane for a chip module design and a related file storage technique.
A mesh plane is a structure of interconnected lines in a cross-hatch pattern (90-degree relative angles) on a given layer of a single-chip or multiple chip module (SCM or MCM), used to tie power or ground vias together. A mesh plane provides both a means of lowering the inductance of the power/ground connections, and of providing noise shielding and power/ground coupling to the signal lines above and below the given layer. Mesh planes include difficult areas to design, such as a chipsite and other dense via regions, which require careful consideration to assure proper connections for the power and ground networks.
Conventionally, mesh planes are designed for an IC carrier design manually. In particular, mesh planes are conventionally designed by an additive approach in which features are added line-by-line to a field until the design is complete. This process is slow and tedious work. For example,
Another shortcoming of the above approach is that conventional IC carrier design tools store each line as a separate feature for storage purposes. Conventional chip module design tools also treat each “T” junction of active lines as a line break point 12. (Crossing of lines do not cause a similar segmentation). For example, sub-layout 10 includes twelve features in total: two crossed lines 14 at each corner and then four lines 16 coupling line break points 12 to a via 18 (size exaggerated so viewable) in the center. Each of these twelve lines or features are stored separately. An unfortunate result of this line-by-line storage approach is that as IC carrier design has increased in complexity, the ultimate IC design files have become very large, which makes storage difficult and may burden system resources, e.g., during revisions.
In view of the foregoing, there is a need in the art for a way to generate a mesh plane for an IC design that does not suffer from the problems of the related art.
The invention includes a method, system and program product implementing storage of a (power or ground) mesh plane file using a multiple line shape, possibly with the storage of lines also, to reduce file size. In addition, the invention implements an activate-substantial-portion-and-remove technique to generate mesh planes rather than the conventional additive approach, which improves the speed of designing the IC carriers. A resulting mesh plane design file may be decreased by as much as half the size of a file generated using the conventional line-by-line and storage approaches.
A first aspect of the invention is directed to a method of generating a mesh plane for an IC carrier design, the mesh plane being defined on a field of grid points, the method comprising the steps of: activating a substantial portion of grid points of an intended mesh plane with active lines; and removing at least one active line to generate the mesh plane.
A second aspect of the invention is directed to a method of generating a mesh plane for an IC carrier design, the method comprising the steps of: generating a mesh plane having a plurality of active lines; and storing a set of active lines of the mesh plane as a multiple line shape.
A third aspect of the invention is directed to a computer program product comprising a computer useable medium having computer readable program code embodied therein for generating a mesh plane for an IC carrier design where the mesh plane is defined on a field of grid points, the program product comprising: program code configured to activate a substantial portion of grid points of an intended mesh plane with active lines; and program code configured to remove at least one active line to generate the mesh plane.
A fourth aspect of the invention is directed to an IC carrier design system comprising: a mesh plane generating unit including: means for activating a substantial portion of grid points of an intended mesh plane with active lines, the grid points being part of a field used to define the mesh plane; and means for removing at least one active line to generate the mesh plane; and a mesh plane storage unit including means for storing a set of active lines of the mesh plane as a multiple line shape.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.
The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
With reference to the accompanying drawings,
As shown in
As noted above, a “mesh plane” is a structure of interconnected lines in a cross-hatch pattern (90-degree relative angles) on a given layer of an IC carrier design, used to tie power or ground vias together. Referring to
In a first step S1 (
A “substantial portion” is defined to include a large enough portion, e.g., a majority, of grid points 102 such that an intended mesh plane can be formed without addition of active lines, i.e., solely by removal of active lines. It should be recognized that the size of field 100 may vary according to user preference. In addition, while an entire field 100 has been shown filled with active lines 106, a field may not necessarily require all possible lines activated. For example, a particular sub-field 110 (
Illustrative ways in which an active line may be removed will now be discussed relative to
As shown by comparing
As shown by comparing
As shown in
To illustrate the advantages of the above-described invention,
To further illustrate,
In the previous discussion, it will be understood that the method steps discussed are performed by a processor, such as CPU 34 of system 30, executing instructions of program product 42 stored in memory. It is understood that the various devices, modules, mechanisms and systems described herein may be realized in hardware, software, or a combination of hardware and software, and may be compartmentalized other than as shown. They may be implemented by any type of computer system or other apparatus adapted for carrying out the methods described herein. A typical combination of hardware and software could be a general-purpose computer system with a computer program that, when loaded and executed, controls the computer system such that it carries out the methods described herein. Alternatively, a specific use computer, containing specialized hardware for carrying out one or more of the functional tasks of the invention could be utilized. The present invention can also be embedded in a computer program product, which comprises all the features enabling the implementation of the methods and functions described herein, and which—when loaded in a computer system—is able to carry out these methods and functions. Computer program, software program, program, program product, or software, in the present context mean any expression, in any language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after the following: (a) conversion to another language, code or notation; and/or (b) reproduction in a different material form.
While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.
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|U.S. Classification||716/126, 174/255|
|International Classification||G06F17/50, H05K1/00|
|Sep 9, 2003||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:DONALDSON, ALICE L.;LUDWIG, JOHN A.;PEREZ-ACEVEDO, RAFAEL;AND OTHERS;REEL/FRAME:013950/0033;SIGNING DATES FROM 20030828 TO 20030903
|Jan 21, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Apr 4, 2014||REMI||Maintenance fee reminder mailed|
|Aug 22, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Oct 14, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20140822