Publication number | US7098708 B2 |

Publication type | Grant |

Application number | US 11/186,451 |

Publication date | Aug 29, 2006 |

Filing date | Jul 20, 2005 |

Priority date | Oct 14, 2003 |

Fee status | Paid |

Also published as | US6958635, US20050077934, US20050253632, WO2005038636A1 |

Publication number | 11186451, 186451, US 7098708 B2, US 7098708B2, US-B2-7098708, US7098708 B2, US7098708B2 |

Inventors | Amr M. Fahim |

Original Assignee | Qualcomm, Incorporated |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (4), Referenced by (4), Classifications (25), Legal Events (2) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 7098708 B2

Abstract

An MN counter with analog interpolation (“MNA counter”) includes an MN counter, a multiplier, a delay generator, and a current generator. The MN counter receives an input clock signal and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal with the desired frequency. The multiplier multiplies the accumulator value with an inverse of M and provides an L-bit control signal. The current generator implements a current locked loop that provides a reference current for the delay generator. The delay generator is implemented with a differential design, receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

Claims(3)

1. An integrated circuit comprising:

a counter operative to receive an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer values, and to generate a counter signal having a second frequency determined by the M value and the N value, wherein the counter is operative to accumulate the M value using a modulo-N accumulator for each cycle of the input clock signal; and

a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal.

2. A device in a communication system, comprising:

a counter operative to receive an input clock signal with a first frequency, an M value, and an N value, where the M value and the N value are integer values, and to generate a counter signal having a second frequency determined by the M value and the N value, wherein the counter is operative to accumulate the M value using a modulo-N accumulator for each cycle of the input clock signal; and

a delay generator operative to receive the counter signal and an L-bit control signal, where L is an integer value greater than one, to generate a differential signal based on the counter signal and the L-bit control signal, and to use the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal.

3. A method comprising:

receiving an input clock signal with a first frequency, an M value and an N value, where the M value and the N value are each integer values;

generating a counter signal having a second frequency determined by the M value and the N value by accumulating the M value using a modulo-N accumulator for each cycle of the input clock signal;

receiving the counter signal and an L-bit control signal, where L is an integer greater than one;

generating a differential signal based on the counter signal and the L-bit control signal;

using the differential signal to provide an output clock signal having the second frequency, wherein leading edges of the output clock signal are variably delayed in accordance with the L-bit control signal.

Description

This application is a continuation of U.S. patent application Ser. No. 10/684,797, filed on Oct. 14, 2003, now U.S. Pat. No. 6,958,635.

1. Field

The present invention relates generally to electronics circuits, and more specifically to a direct digital synthesizer (DDS).

2. Background

In a modem communication device, multiple clock signals with frequencies that are unrelated may be needed for various functions. For example, a clock signal with a first frequency may be needed for a digital signal processing subsystem, another clock signal with a second frequency may be needed for a sampled analog subsystem, and so on.

Multiple clock signals with unrelated frequencies may be generated in various manners. In one conventional design, a clock generator with a single phase locked loop (PLL) is operated at a high frequency. The clock signal from this generator is divided in frequency by different integer values to obtain multiple output clock signals with different frequencies. This design places stringent requirements on the PLL in terms of performance and power consumption. In another conventional design, a separate PLL is provided for each subsystem requiring a clock signal with a different frequency. This design is undesirable because multiple PLLs for multiple clock signals normally consume a large amount of power and occupy a large area.

In yet another conventional design, an MN counter is used to divide an input clock signal (e.g., from a PLL) by a divider value to obtain an output clock signal with the desired frequency. The divider value is a ratio of two integer values M and N (i.e., N/M), where M<2·N for proper operation of the MN counter and N/M may be an integer or non-integer value. If the N/M divider value is not an integer, which is often the case, then the desired frequency is obtained by dividing the input clock signal in frequency by └N/M┘ for some of the time and by ┌N/M┐ for the remainder of the time, where └x┘ is a floor operator that provides the nearest lower integer value for x and ┌x┐ is a ceiling operator that provides the nearest higher integer value for x. This division with two integer values of └N/M┘ and ┌N/M┐ results in the output clock signal having inherent jitter that can be as large as one period of the input clock signal. For example, if the input clock frequency is 100 MHz, then the worst-case jitter for the output clock signal from the MN counter is 10 nsec.

Various methods for reducing jitter in the output clock signal from an MN counter have been proposed. For example, some methods reduce jitter by estimating the amount of phase shift needed in each output clock cycle to eliminate the jitter and then adjusting the output clock phase accordingly. In any case, most of these methods rely on absolute (voltage and/or current) reference levels to perform the phase shift estimation and/or adjustment and are thus prone to performance degradation due to circuit component mismatches and integrated circuit (IC) process variations.

There is therefore a need in the art for techniques to generate a clock signal having less jitter.

An MN counter with analog interpolation (referred to herein as an “MNA counter”) capable of generating an output clock signal having improved jitter performance is described herein. The jitter performance is minimally affected by IC process variations and system offsets using the design techniques described herein.

In a specific embodiment, the MNA counter includes an MN counter, a dither generator, an inverse unit, a multiplier, a delay generator, and a current generator. The dither generator provides a dither signal used to suppress spurious signals in the output clock signal caused by periodic jitter. The MN counter receives an input clock signal, the dither signal, and M and N values, accumulates M for each input clock cycle using a modulo-N accumulator, and provides an accumulator value and a counter signal. The counter signal has a frequency determined by the input clock frequency and the M and N values, and includes a pulse whenever the modulo-N accumulator wraps around. The inverse unit provides a Q value that is an inverse of M. The multiplier (which may be implemented with multiple pipelined stages to achieve higher operating speeds) multiplies the accumulator value with the Q value and provides an L-bit control signal. The current generator provides a reference current for the delay generator. The delay generator receives the counter signal and the L-bit control signal, compares a differential signal generated based on the counter and control signals, and provides the output clock signal. The leading edges of the output clock signal have variable delay determined by the L-bit control signal and the reference current.

The delay generator may be implemented with a differential design that utilizes two banks of capacitors. The capacitors in each bank may be implemented with binary decoding or thermal decoding and are selectable by the L-bit control signal. The selected capacitors in one bank are charged by one current source, and the selected capacitors in the other bank are discharged by another current source. The differential signal is defined by the two voltages on the selected capacitors in the two banks. The variable delay is determined by the amount of time taken for the two voltages to cross each other. Details of the delay generator are described below.

The current generator may be implemented with a replica delay generator and a current locked loop. The replica delay generator has the same design as the delay generator and is configured to provide a predetermined amount of delay (e.g., one half input clock period of delay) when the proper reference current is received. The current locked loop adjusts the reference current so that the predetermined amount of delay is obtained. The capacitors for the replica delay generator are matched to the capacitors for the delay generator, and the capacitors for both delay generators are arranged in a two-dimensional array using a common centroid layout to achieve good matching. Low-power is achieved by enabling the replica delay generator a sufficient number of (e.g., two) input clock cycles prior to each output clock edge transition, then disabling the replica delay generator after the transition is complete.

Various aspects, embodiments, and features of the invention are described in further detail below.

The features and nature of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout and wherein:

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

**100** that includes a phase locked loop (PLL) **110** and a direct digital synthesizer (DDS) **120**. PLL **110** receives a reference signal (Ref) and generates an input clock signal (CLKin). The input clock signal has its frequency and/or phase locked to that of the reference signal. PLL **110** may be implemented with a phase-frequency detector (PFD), a loop filter, a voltage controlled oscillator (VCO), and a divider, as is known by one skilled in the art. DDS **120** receives the input clock signal and generates an output clock signal (CLKout) having a frequency that is a fraction of the input clock frequency.

**220** that may be used for DDS **120** in **220** receives the input clock signal and the M and N values, each of which is an integer one or greater, and generates the output clock signal having a frequency that is N/M times that of the input clock signal. Within MN counter **220**, a summer **224** receives and adds M to an accumulator value (ACC) from a register **222** and provides a first combined value (V**1**) to a summer **226** and to a ‘1’ input of a multiplexer (MUX) **228**. Summer **226** receives and subtracts N from the first combined value and provides a second combined value (V**2**) to a ‘0’ input of multiplexer **228**. Summer **226** also provides a one-bit inverted overflow signal (OVFb) to an inverter **230** and to a select input of multiplexer **228**. The OVFb signal is logic low if there is an overflow (described below) and logic high otherwise. Multiplexer **228** provides the first combined value if there is no overflow and the second combined value if there is an overflow. Register **222** receives and stores the value from multiplexer **228**. Inverter **230** receives and inverts the OVFb signal and provides the output clock signal.

MN counter **220** operates as follows. Register **222**, summers **224** and **226**, and multiplexer **228** collectively implement a modulo-N accumulator that stores a value ranging from 0 to N−1. For each input clock cycle, the accumulator accumulates M with the current accumulator value and provides the first combined value, which is stored back in register **222** if an overflow has not occurred. An overflow occurs whenever the first combined value exceeds N and is indicated by the OVFb signal being at logic low. When an overflow occurs, N is subtracted from the first combined value and the result is stored in register **222**. A pulse is provided on the output clock signal when an overflow occurs.

**220**. For the example shown in **222** is reset and the accumulator value (ACC) is equal to zero. The accumulator value increases by M=3 in each of input clock cycles **2** and **3**. In input clock cycle **4**, the first combined value is nine, which exceeds N=8. A value of eight is then subtracted from the first combined value, and a value of one is stored in register **222**. The same computation proceeds for each subsequent input clock cycle. A clock pulse is provided on the output clock signal whenever an overflow occurs and eight is subtracted from the first combined value.

As _{CLKin}/3, as desired, where T_{CLKin }is one input clock period. However, the output clock signal has instantaneous periods of 3T_{CLKin}, 3T_{CLKin}, and 2T_{CLKin}, which give a worst-case cycle-to-cycle jitter of T_{CLKin}. Moreover, the jitter has a periodicity of 8T_{CLKin }since the jitter follows a pattern that repeats every eight input clock periods. This periodic jitter results in spurs appearing in the spectrum of the output clock signal. The spurs can have relatively large amplitude and may be detrimental for some applications (e.g., high quality audio) that require spectrally pure clock signals.

An MN counter with analog interpolation (an “MNA counter”) can be used to reduce jitter and spurs. The MNA counter attempts to reduce jitter by shifting the position of the leading edges (e.g., rising edges) of the output clock signal such that all output clock periods are the same. This is achieved by determining the amount of phase shift needed for each output clock cycle to obtain the desired output clock period and then advancing the leading edge accordingly.

_{CLKin}/3 for each clock cycle. The amount of phase shift to achieve the ideal output clock period can be expressed as:

where ACC_{i }is the accumulator value at the time of overflow. The leading edge of the output clock is advanced by T_{CLKin}/3 when the accumulator value is one, advanced by 2T_{CLKin}/3 when the accumulator value is two, and not advanced when the accumulator value is zero.

If the phase shift can be generated exactly and if the leading edges can be advanced by this phase shift without errors, then all of the output clock cycles will have equal period and the ideal MNA counter will have zero jitter. A delay generator can be used to generate the desired phase shift for the MNA counter. The delay generator can be designed to generate phase shifts in discrete steps. Higher accuracy can be attained for the delay generator with greater circuit complexity, more die area, and higher power consumption. Thus, there is a trade-off between the accuracy of the delay generator and other system considerations.

_{CLKin}/8, then 22T_{CLKin}/8, then 21T_{CLKin}/8, and so on, as shown in _{CLKin}/8 with the 3-bit delay generator.

For a delay generator with L-bit accuracy, where L>1, the required phase shift can be estimated as:

A phase shift to advance the output clock edge (i.e., a negative phase shift) can be obtained by operating the delay generator one input clock cycle early and generating a delay that is complementary to the negative phase shift. The delay may be expressed as:

In general, for an L-bit delay generator, the worst-case cycle-to-cycle jitter is T_{CLKin}/2^{L}, which is a reduction by a factor of 2^{L }over the jitter generated by the MN counter. Jitter is thus exponentially reduced for larger values of L (assuming no degradation due to circuit implementation). However, circuit complexity, area, and power consumption also increase exponentially with L. A suitable choice for L can be determined based on jitter requirements and other factors.

**400** that may be used for DDS **120** in **400**, an MN counter **420** receives the input clock signal (CLKin), the M and N values, and a dither signal from a dither generator **440**. The dither signal is used to suppress large amplitude spurious signals in the output clock signal caused by periodic jitter. MN counter **420** performs accumulation of M with a modulo-N accumulator to implement an “M divided by N” operation, as described above. MN counter **420** provides an accumulator value (ACC) and a counter signal (Ce**2**). The counter signal has the desired frequency and is derived based on an overflow signal within MN counter **420**. A D flip-flop (D-FF) **422** receives and delays the Ce**2** signal by one input clock cycle and provides a delayed counter signal (Ce**1**). Another D flip-flop (D-FF) **424** receives and delays the Ce**1** signal by one input clock cycle and provides another delayed counter signal (Cout). The Ce**1** and Ce**2** signals are early with respect to the Cout signal by one and two input clock cycles, respectively, as indicated by the “e**1**” and “e**2**” designations. Since the phase shift needs to be generated before the overflow occurs, as shown in **420** is delayed by two input clock cycles to obtain the Cout signal. The Ce**1** and Ce**2** signals are used to enable generation of the desired delay prior to the Cout signal.

Dither generator **440** generates the dither signal and is described below. An inverse unit **450** receives M, derives an inverse of M, and provides an inverse value (Q), where Q≅1/M. A multiplier **460** receives the ACC value, the Q value, and the Ce**2** signal. Multiplier **460** multiplies the ACC value with the Q value, when enabled by the Ce**2** signal, and provides a P value for an L-bit control signal. The P value corresponds to the term (1−F_{i}/2^{L}) in equation (4). The P value is obtained by quantizing the product of ACC_{i }and Q using L bits (with rounding for the least significant bit) and inverting all of the L bits. The P value is indicative of the amount of delay (if any) required for the current output clock cycle. A delay generator **470** receives the P value and the Ce**1** and Ce**2** signals and generates the output clock signal (CLKout). The output clock signal has each leading edge shifted by the delay indicated by the P value. A current generator **480** generates the reference currents, I_{refp }and I_{refn}, for delay generator **470**. Each of the units in MNA counter **400** is described in further detail below.

**420** within MNA counter **400**. When N is not a power of 2, two full adders operate serially to perform accumulation of M using a modulo-N accumulator, as described above for **400**, high-speed circuitry is used to implement the two full adders.

Within MN counter **420**, a carry-save adder (CSA) **524** receives and combines M, the dither signal, and the accumulator value (ACC) (i.e., three input terms) and provides two output terms. A CSA **526** receives and sums the two output terms from CSA **524** and subtracts N and provides two output terms. A carry lookahead adder (CLA) **528** *a *combines the two output terms from CSA **524** and provides the first combined value (V**1**) to a multiplexer **530**. A CLA **528** *b *combines the two output terms from CSA **526** and provides the second combined value (V**2**) to multiplexer **530**. CLA **528** *b *also provides the Ce**2** signal. Multiplexer **530** provides either the V**1** or V**2** value to a register **522** depending on the Ce**2** signal. MN counter **420** can be operated at a high operating speed because of the use of carry-save adders and carry lookahead adders. However, other designs may also be used for MN counter **420**.

Dither generator **440** provides the one-bit dither signal that is used to randomize the jitter and reduce the amplitude of the spurs caused by periodic jitter from MN counter **420**. The dither signal can be generated based on a pseudo-random number (PN) sequence. Dither generator **440** may thus be implemented with a linear feedback shift register (LFSR) that is configured to implement a polynomial generator for a PN sequence. For example, a 26-bit LFSR that implements a polynomial generator x^{25}+x^{24}+x^{20}+1 may be used for dither generator **440**. The dither signal comprises a repeating pseudo-random sequence of +1 and −1 and does not introduce an average frequency offset to the output clock frequency. Other designs for generating the one-bit dither signal may be used without affecting the scope of the embodiments herein.

Inverse unit **450** generates a value of Q≅1/M. Inverse unit **450** may be implemented with a serial division algorithm, a look-up table, or some other manner. Since the Q value is typically computed once and does not change for a given operating mode, this value may be provided by a unit external to MNA counter **400**. For example, a controller can compute and provide the Q value via a register.

**460** within MNA counter **400** in **460** operates when an overflow occurs in MN counter **420**, which may be infrequent for some values of M and N. Although the activity rate may be low, the execution window for multiplier **460** is equal to the input clock rate, which may be relatively high. To support a high input clock frequency, multiplier **460** is implemented as a three-stage pipelined multiplier.

For the first pipeline stage, latches **612** *a *and **612** *b *latch the ACC and Q values, respectively, with the Ce**2** signal. Latches **612** *a *and **612** *b *inhibit the ACC value from rippling through multiplier **460** if no overflow occurs in MN counter **420**. A partial product tree generator **614** performs multiplication of the ACC and Q values by generating partial product terms and accumulating these terms in multiple accumulation stages. Partial product tree generator **614** provides two partial product terms.

For the second pipeline stage, D flip-flops **622** *a *and **622** *b *store the two partial product terms from partial product tree generator **614**. A carry-select adder **624** combines the two partial product terms from D flip-flops **622** *a *and **622** *b *and provides the final result. The partial product accumulation is divided into two pipeline stages to support higher operating speed for multiplier **460**. The multiplication can be partitioned into more than two stages for even higher operating speed.

For the third pipeline stage, a D flip-flop **632** *a *stores the most significant bits (MSB) of the final result from carry-select adder **624** and a D flip-flop **632** *b *stores the least significant bit (LSB) of the final result. An AND gate **634** performs a logical AND of the LSB from D flip-flop **632** *b *with a Round Enable signal. A CSA **636** combines the MSB of the final result from D flip-flop **632** *a *with the output of AND gate **634** and provides the combined result to a D flip-flop **638**. The rounding of the final result can reduce truncation errors by ½ LSB. D flip-flop **638** provides the P value, which is approximately equal to ACC/M and quantized to L bits. For illustrative ease, the bit inversion to obtain the term (1−F_{i}/2^{L}) in equation (4) is not explicitly shown in **460** may also be implemented with other designs (e.g., a look-up table that is indexed by the accumulator value).

A delay generator can generate a number of discrete delays by charging and discharging a bank of capacitors. Different delays can be obtained by turning on (i.e., selecting) different combination of capacitors in the bank. The delay generated by the delay generator can be expressed as:

where C_{load }is the load capacitance (which is dominated by the selected capacitors in the bank), I_{ch }is the current used to charge and discharge the load capacitor, and V_{swing }is the voltage swing of the delay generator. Equation (5) shows that the delay is dependent on three parameters that are in turn dependent on the IC manufacturing process. Since accurate generation of the delay is needed to achieve good jitter performance, techniques are described herein to mitigate the effects of C_{load}, V_{swing}, and I_{ch }on jitter performance.

**470** within MNA counter **400** in **470** uses a differential design to provide good rejection of power supply noise and to mitigate the effects of circuit component mismatches. Delay generator **470** also uses a reference current from a current locked loop (CLL) to accurately generate the charging current.

Delay generator **470** includes two banks of capacitors, **710** and **720**. Bank **710** includes S capacitors **712** *a *through **712** *s*, each having one end coupled to circuit ground and the other end coupled to a node V_{p }via switches **714** *a *through **714** *s*, respectively. S is dependent on the number of bits (L) and the design for delay generator **470**. Bank **720** includes S capacitors **722** *a *through **722** *s*, each having one end coupled to circuit ground and the other end coupled to a node V_{n }via switches **724** *a *through **724** *s*, respectively. A switch **732** has one end coupled to node V_{p }and the other end coupled to circuit ground. A switch **734** has one end coupled to node V_{p }and the other end coupled to one end of a current source **736**. The other end of current source **736** couples to a supply voltage (V_{DD}). A switch **742** has one end coupled to node V_{n }and the other end coupled to V_{DD}. A switch **744** has one end coupled to node V_{n }and the other end coupled to one end of a current source **746**. The other end of current source **746** couples to circuit ground.

A comparator **750** has a non-inverting input coupled to node V_{p}, an inverting input coupled to node V_{n}, and an output that provides the output clock signal. A decoder **770** receives the P value from multiplier **460** and generates control signals for switches **714** and **724** to select the desired capacitors and deselect the remaining capacitors.

Current source **736** receives the reference current I_{refp }from current generator **480** provides a charging current of I_{dg}. Current source **746** receives the reference current I_{refn }from current generator **480** and provides a discharging current of I_{dg}. Current sources **736** and **746** may be implemented with constant-g_{m }current sources or some other types of current sources. Capacitors **712** and **722**, switches **714** and **724**, and decoder **770** may be implemented as described below.

Delay generator **470** operates as follows. When the Ce**2** signal is activated due to an overflow in MN counter **420**, switches **714**, **724**, **732**, and **742** are all turned on for one input clock cycle, capacitors **712** in bank **710** are discharged to circuit ground by switch **732**, capacitors **722** in bank **720** are precharged to V_{DD }by switch **742**, node V_{p }is at circuit ground, node V_{n }is at V_{DD}, and the output clock signal is at logic low. One input clock cycle later, switches **732** and **742** are turned off and only selected ones of switches **714** and **724** in banks **710** and **720** are turned on by the P value from multiplier **460**. The selected capacitors in banks **710** and **720** are those with their associated switches turned on. In this same input clock cycle, switches **734** and **744** are turned on by the Ce**1** signal, the selected capacitors in bank **710** are charged toward V_{DD }by current source **736**, the selected capacitors in bank **720** are discharged toward circuit ground by current source **746**, the voltage on node V_{p }rises, and the voltage on node V_{n }drops. A differential signal is defined by the voltages on nodes V_{p }and V_{n}. When the voltage on node V_{p }exceeds the voltage on node V_{n }(i.e., when the two voltages cross), the output clock signal transitions to logic high. The leading edge of the output clock signal is thus determined by the amount of delay provided by delay generator **470**. The enable signals for delay generator **470** are delayed appropriately to line up with the arrival of the P signal from multiplier **460**.

The output clock signal provided by delay generator **470** within MNA counter **400** does not have 50% duty cycle. To obtain an output clock signal with 50% duty cycle, the M value may be doubled, and the output signal from comparator **750** may be divided by two (2) to obtain the output clock signal. The maximum N/M ratio is then limited to 0.5 for proper operation of the MNA counter.

The delay generated by delay generator **470** may be expressed as:

where C_{unit }is a unit capacitance. In equation (6), the factor V_{DD}/2 is the voltage swing for the capacitors in each bank with the differential design and corresponds to V_{swing }in equation (5). The factor 2^{L}·C_{unit }is the total capacitance for all capacitors in one bank. The factor [1−ACC_{i}/M] corresponds to the P value from multiplier **460**. The factor C_{dg}=2^{L}·C_{unit}·[1−ACC_{i}/M] is the capacitance for all selected capacitors in one bank and corresponds to C_{load }in equation (5). The unit capacitance C_{unit }and the charging current I_{dg }are selected such that delay generator **470** provides one input clock period (T_{CLKin}) of delay when all capacitors in the bank are selected (i.e., when C_{dg}=2^{L}·C_{unit}). The capacitor size directly affects jitter, area, and power consumption. A suitable capacitor size can be selected based on a tradeoff of all of these considerations.

The accuracy of delay generator **470** is dependent on the accuracy of the unit capacitance C_{unit}, the voltage swing V_{DD}, and the charging current I_{dg}, which can vary due to IC process variations. A current locked loop can be used to generate a requirement current that tracks process variation of the delay generator circuitry and mitigates the effects of these three parameters on the accuracy of delay generator **470**.

**480** *a*, which is one embodiment of bias current generator **480** in **480** *a*, a divide-by-2 unit **812** receives and divides the input clock signal (CLKin) by two and provides a divided clock signal (CLK**2**). Unit **812** uses the trailing edges of the input clock signal to perform the divide-by-2. An AND gate **814** performs a logical AND of the CLKin signal and the CLK**2** signal and provides a reference clock signal (R). A replica delay generator **870** delays the CLK**2** signal by one half input clock period and provides a delayed clock signal (V). Although not shown in **2** signal may be provided to a dummy AND gate matched to AND gate **814**, and the output of the dummy AND gate can be provided to delay generator **870**.

A phase-frequency detector (PFD) **830** compares the phase of the reference clock signal and the phase of the delayed clock signal and provides a phase error. PFD **830** may be implemented with an early-late detector that is known in the art. A charge pump **832** converts the phase error into a current. A loop filter, implemented with a single capacitor **834**, filters the current from charge pump **832** and also converts the current into a voltage. Capacitor **834** can be a small capacitor if the input clock rate is high. A voltage-to-current (V-to-I) converter **840** converts the voltage on capacitor **834** back into a current using current mirrors and provides the reference currents I_{refp }and I_{refn }to replica delay generator **870**. Replica delay generator **870** adjusts its delay based on the reference currents I_{refp }and I_{refn }such that the delayed clock signal is time-aligned with the reference clock signal. V-to-I converter **840** also provides the reference currents I_{refp }and I_{refn }to current sources **736** and **746** within delay generator **470**.

**480** *a*. The reference clock signal is the input clock signal divided by two and delayed by one half input clock period. Replica delay generator **870** generates a delay of one half input clock period for the divided clock signal when the correct reference current is received from V-to-I converter **840**. The current lock loop adjusts the reference current such that the leading edges of the reference clock signal and the delayed clock signal are time-aligned.

The closed loop transfer function H(s) for current locked loop **480** *a *may be expressed as:

where I_{cp }is the current of charge pump **832**, C_{lf }is the capacitance of capacitor **834** for the loop filter, K_{v2i }is the gain of V-to-I converter **840** (in units of μA/V), and K_{dg }is the gain of replica delay generator **870** (in units of nsec/μA). Equation (7) indicates that current locked loop **480** *a *is a single pole system that is unconditionally stable. However, similar to a delay locked loop, the current locked loop can false lock to a zero time period or a double time period. False lock can be prevented by ensuring that the forward gain is not too large. One method of achieving this is to control the charge pump current I_{cp }(e.g., from 5 μA to 40 μA, in 5 μA steps). A large charge pump current I_{cp }may be used initially to achieve fast locking. A small current may be used thereafter to prevent the current locked loop from overshooting. The gain K_{v2i }is adjusted such that delay generator **870** is capable of producing one half input clock period of delay for the entire range of input clock frequencies and over all process corners. The gain K_{dg }is controlled by the size of the capacitors in delay generator **870**.

Replica delay generator **870** has the same design as delay generator **470**. The delay generated by replica delay generator **870** may be expressed as:

where C_{rdg }is the capacitance and I_{rdg }is the charging current for replica delay generator **870**. Replica delay generator **870** is designed to provide a delay of T_{CLKin}/2 with capacitance C_{rdg }and current I_{rdg}. Delay generator **470** is designed to provide a delay of T_{CLKin }with capacitance 2^{L}·C_{unit }and current I_{dg}. The capacitance to current (C/I) ratio for replica delay generator **870** is thus one half of the C/I ratio for delay generator **470**, since the same voltage swing V_{DD }is used for both generators. For example, the same charging current may be used for both delay generators (i.e., I_{dg}=I_{rdg}), and the capacitance of replica delay generator **870** may be set to half of the total capacitance of delay generator **470** (i.e., C_{rdg}=2^{L}·C_{unit}/2). In this case, the accuracy of delay generator **470** is dependent on the matching between the capacitance of delay generator **470** and the capacitance of replica delay generator **870**. Current locked loop **480** *a *thus removes the effects of the supply voltage V_{DD }and the charging current I_{dg}, and the accuracy of delay generator **470** is not impacted by these two parameters. Current locked loop **480** *a *also effectively removes the effect of the load capacitor C_{dg}, and the accuracy of delay generator **470** is dependent on the matching of the capacitors for generators **470** and **870** instead of the capacitance of these capacitors.

The capacitors for delay generator **470** and replica delay generator **870** may be implemented in various manners. In one embodiment, binary decoding is used for the capacitors in each of banks **710** and **720** in _{unit}, 2C_{unit}, 4C_{unit}, . . . and 2^{L−1}·C_{unit}. Each capacitor is selected or deselected based on a respective bit of the P value from multiplier **460**. In another embodiment, thermal decoding is used for the capacitors in each bank to improve linearity. For this embodiment, 2^{L }capacitors are provided for each bank, and each capacitor has the same capacitance of C_{unit}. The 2^{L }capacitors can be matched more easily because they all have the same dimension. Consequently, smaller matching error is encountered and greater linearity is achieved. As many of the 2^{L }capacitors are selected as necessary based on the P value. The selected capacitors may be dispersed (e.g., randomly selected) among the 2^{L }capacitors to reduce gradient linearity error (if any), which is a systematic error across an IC die caused by manufacturing.

**710** and decoder **770**. For this embodiment, delay generator **470** has 6-bit accuracy (i.e., L=6) and thermal decoding is used for the capacitors. Bank **710** includes 64 capacitors arranged in a 4×16 array with four rows and sixteen columns. Each capacitor has a capacitance of C_{unit}. Decoder **770** receives the 6-bit P value and generates the controls for the 64 capacitors. Within decoder **770**, a thermal decoder **912** receives the four MSBs of the P value and provides to a D flip-flop **922** sixteen column controls for the sixteen columns of the 4×16 array. A thermal decoder **914** receives the two LSBs of the P value and provides to a D flip-flop **924** four row controls for the four rows of the 4×16 array. D flip-flops **922** and **924** provide controls for the columns and rows, respectively, and ensure glitch free transition in delay generator **470**.

**718** *x *among 2^{L }capacitor units for capacitor bank **710** for an implementation using thermal decoding. Capacitor cell **718** *x *is for one row of one column of the 4×16 array shown in **718** *x *includes a capacitor **712** *x*, an N-channel transistor **714** *x*, and a logic unit **716** *x*. Capacitor **712** *x *is one of capacitors **712** in bank **710** and has a capacitance of C_{unit}, and N-channel transistor **714** *x *is for one of switches **714** in bank **710**. Logic unit **716** *x *receives a control for row i and controls for column j and j+1 from decoder **770** and generates a gate signal for N-channel transistor **714** *x *based on the three input controls. To individually select 64 capacitors in the 4×16 array for bank **710**, 64 control signals would be needed. To reduce the number of control signals required, the capacitors in the 4×16 array are selected one column at a time. For example, to select nine capacitors, all four capacitors in the first and second columns are selected, and one capacitor in the third column is selected. If any capacitor in the next column j+1 is selected, then all capacitors in the current column j are selected. When enabled, N-channel transistor **714** *x *couples capacitor **712** *x *to node V_{p}. The size of N-channel transistor **714** *x *can affect the jitter reduction capability of MNA counter **400**. A small-size N-channel transistor **714** *x *can provide better jitter performance.

With the current locked loop, the accuracy of delay generator **470** is dependent on the matching between the capacitors for delay generator **470** and replica delay generator **870**. To achieve good matching, the capacitors for both delay generators **470** and **870** can be implemented as one array arranged in a two-dimensional (2-D) common centroid layout.

**1100** for delay generator **470** and replica delay generator **870** using a 2-D interdigitated, common centroid layout. In this example, delay generator **470** has 6-bit accuracy, and the 64 capacitors for each of banks **710** and **720** are arranged into four rows, as described above. Capacitor array **1100** includes twelve rows—four rows for the capacitors in bank **710**, four rows for the capacitors in bank **720**, and four rows for the capacitors in replica delay generator **870**.

For the exemplary implementation shown in **1100** includes six sections **1110** *a *through **1110** *f*. Section **1110** *a *includes capacitor row **3** for both banks **710** and **720**, section **1110** *b *includes capacitor rows **1** and **3** for replica delay generator **870**, section **1110** *c *includes capacitor row **1** for both banks, section **1110** *d *includes capacitor row **0** for both banks, section **1110** *e *includes capacitor rows **0** and **2** for replica delay generator **870**, and section **1110** *f *includes capacitor row **2** for both banks. The capacitors in rows **0**, **1**, **2**, and **3** for bank **710** are coupled to node V_{p }when enabled. The capacitors in rows **0**, **1**, **2**, and **3** for bank **720** are coupled to node V_{n }when enabled. The capacitors for replica delay generator **870** are always on and no controls are needed, as indicated in **870** are coupled to two corresponding nodes V_{rp }and V_{m }within the generator **870**.

The MNA counter design described herein provides good performance and other advantages. The differential design allows for a reduction in the size of the capacitors in delay generators **470** and **870**. The smaller capacitor size results in less power being consumed to generate the desired delay. Moreover, a smaller area is required to implement the smaller-size capacitors. The current locked loop removes the dependency on voltage swing and charging current, which improves the accuracy of the delay generator. To reduce power consumption, the current locked loop and multiplier may be turned on one or two input clock cycles before they are needed (e.g., using the Ce**1** and Ce**2** signals) and turned off thereafter.

**1200** in a wireless communication system. Wireless device **1200** may be a cellular phone, a terminal, a handset, or some other devices or designs. The wireless communication system may be a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a multiple-input multiple-output (MIMO) system, an orthogonal frequency division multiplexing (OFDM) system, an orthogonal frequency division multiple access (OFDMA) system, and so on. Wireless device **1200** is capable of providing bi-directional communication via a receive path and a transmit path.

For the receive path, signals transmitted by base stations are received by an antenna **1212**, routed through a duplexer (D) **1214**, and provided to a receiver unit (RCVR) **1216**. Receiver unit **1216** conditions (e.g., filters, amplifies, and frequency downconverts) the received signal and digitizes the conditioned signal to provide samples, which are provided to a digital signal processor (DSP) **1220** for further processing. For the transmit path, data to be transmitted from wireless device **1200** is provided by DSP **1220** to a transmitter unit (TMTR) **1218**. Transmitter unit **1218** conditions (e.g., filters, amplifies, and frequency upconverts) the data and generates a modulated signal, which is routed through duplexer **1214** and transmitted via antenna **1212** to the base stations.

DSP **1220** includes various processing units such as, for example, an internal controller **1222**, a processor **1224**, a memory unit **1226**, a bus control unit **1228**, and an audio processor **1236**, all of which are coupled via a bus **1238**. DSP **1220** further includes a PLL **1230** that receives a reference signal (e.g., from a temperature compensated crystal oscillator (TCXO)) and generates a master clock for DSP **1220**. PLL **1230** may generate various clock signals (e.g., by dividing the master clock with different integer values) for the processing units within DSP **1220** and possibly for processing units external to DSP **1220** (e.g., a main controller **1240** and a main memory unit **1242**). An MNA counter **1234** receives the master clock and generates a first low-jitter clock signal for audio processor **1236**. An MNA counter **1234** receives the master clock and generates a second low-jitter clock signal for another processing unit (e.g., analog-to-digital converters within receiver unit **1216**). The first and second low-jitter clock signals have different frequencies. In general, one MNA counter may be used to generate each different clock frequency that is not an integer multiple of the master clock. MNA counters **1232** and **1234** may each be implemented with MNA counter **400** in **1220** may include various processing units and perform various functions, which may be dependent on the specific design of DSP **1220** and the communication system.

The direct digital synthesizer with analog interpolation (i.e., the MNA counter) described herein may be implemented in an application specific integrated circuit (ASIC), a digital signal processor (DSP), a digital signal processing device (DSPD), a programmable logic device (PLD), a field programmable gate array (FPGA), a processor, a controller, a micro-controller, a microprocessor, and other electronic units. The MNA counter may be implemented within the one or multiple integrated circuit (IC) dies and in the one or multiple ICs. For example, all units of the MNA counter may be implemented on one IC die. As another example, the digital portion of the MNA counter (e.g., MN counter **420**, dither generator **440**, inverse unit **450**, multiplier **460**, and D flip-flops **422** and **424** in **470** and current generator **480**) may be implemented on another IC die.

The MNA counter may also be fabricated with various IC process technologies such as CMOS, NMOS, BJT, and so on. The MNA counter may also be fabricated using different device size technologies (e.g., 0.13 mm, 30 nm, and so on).

Portions of the MNA counter (e.g., inverse unit **450** and multiplier **460**) may be implemented in software. For a software implementation, the modules (e.g., procedures, functions, and so on) may be used to perform some of the functions described herein. The software codes may be stored in a memory unit (e.g., memory unit **1226** or **1242** in **1224** or controller **1240**). The memory unit may be implemented within the processor or external to the processor, in which case it can be communicatively coupled to the processor via various means as is known in the art.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US6359950 * | Mar 5, 2001 | Mar 19, 2002 | Infineon Technologies. | Digital PLL (phase-locked loop) frequency synthesizer |

US6583674 * | Mar 9, 2001 | Jun 24, 2003 | Nokia Mobile Phones Ltd | Fractional multimodulus prescaler |

US6731176 * | Mar 13, 2002 | May 4, 2004 | Atheros Communications, Inc. | Synthesizer with lock detector, lock algorithm, extended range VCO, and a simplified dual modulus divider |

US6836526 * | Feb 25, 2003 | Dec 28, 2004 | Agency For Science, Technology And Research | Fractional-N synthesizer with two control words |

Referenced by

Citing Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US7667504 * | Mar 11, 2008 | Feb 23, 2010 | International Business Machines Corporation | Signal delay element, method and integrated circuit device for frequency adjustment of electronic signals |

US7764208 * | Nov 21, 2008 | Jul 27, 2010 | Stmicroelectronics S.R.L. | Clock dithering process for reducing electromagnetic interference in D/A converters and apparatus for carrying out such process |

US20090021288 * | Mar 11, 2008 | Jan 22, 2009 | International Business Machines Corporation | Signal Delay Element, Method and Integrated Circuit Device for Frequency Adjustment of Electronic Signals |

US20090140896 * | Nov 21, 2008 | Jun 4, 2009 | Stmicroelectronics S.R.L. | Clock dithering process for reducing electromagnetic interference in d/a converters and apparatus for carrying out such process |

Classifications

U.S. Classification | 327/155, 377/48, 377/47, 327/160 |

International Classification | H03K5/00, H03K5/135, G06F1/08, G06F1/02, H03L7/081, H03L7/06, H03K23/68, H03K3/017, H03K5/156 |

Cooperative Classification | H03K5/1565, G06F1/022, H03K2005/00071, H03L7/0814, G06F2211/902, H03K2005/00032, H03K5/135, G06F1/08 |

European Classification | H03K5/156D, H03K5/135, H03L7/081A1, G06F1/02W |

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