|Publication number||US7102874 B2|
|Application number||US 10/895,116|
|Publication date||Sep 5, 2006|
|Filing date||Jul 21, 2004|
|Priority date||Feb 2, 2004|
|Also published as||US20050168913|
|Publication number||10895116, 895116, US 7102874 B2, US 7102874B2, US-B2-7102874, US7102874 B2, US7102874B2|
|Inventors||Uei-Ming Jow, Ying-Jiunn Lai, Chun-Kun Wu, Pel-Shen Wei, Chang-Sheng Chen, Ching-Liang Weng|
|Original Assignee||Industrial Technology Research Institute|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (18), Referenced by (3), Classifications (19), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present invention shows a plurality of different-sized metal laminates stacked for a built-in capacitor in the manufacturing process of a printed circuit board (PCB), which is used to reduce the error in process and raise the capability of noise-immunity in a PCB.
2. Description of Related Art
In the age of high frequency and high-speed electrical systems, the need for accuracy of electrical devices is increasingly acute. The manufacturing process is the focus of efforts to raise the precision of active and passive elements. More particularly, it is a severe challenge to the manufacturing process of capacitor in a PCB, which will be operated at high frequency and is small in size.
In the prior art, there are two main capacitor techniques; one is a discrete component capacitor using surface mount technology (SMT) as an example, the other is a newly developed capacitive substrate. The discrete component capacitor has at least three problems, including: (1) the range of working bandwidth is insufficient; (2) the alternating impedance is not low enough; and (3) the capacitor cannot be integrated into the system in package. Current capacitive substrate elements also have three main drawbacks, including: (1) the via parasite effect is excessive; (2) the electric design thereof is only two-dimensional and the area thereof is too large; and (3) the dielectric material has considerable electric loss. But the PCB with built-in capacitor in the invention can reduce the usage of passive elements for reducing costs, volume, and number of welding points, while raising the reliability and the electric characteristics thereof as well.
The printed circuit board in prior art is usually composed of flat substrates with the same dielectric coefficient; for instance, the Fiberglass Fabric (FR4) is used. However, the noise-immunity of this PCB at high frequencies is bad, and the low passive element integration is a demerit thereof. With further improvement as provided by U.S. Pat. No. 5,079,069 shown in
In the prior art, the capacitor components are replaced by a built-in capacitive substrate as described in the following.
The role of current PCB is not only to be in charge of the function of, signal transferring as before, but also to integrate many passive or even active elements therein. Reference is made to
The advantages of the built-in capacitor in the prior art are described as follows: (1) the interference of high-frequency noise is suppressed; (2) the number of connection layers required in PCB is reduced; (3) the density integrated with the whole system is increased and the area of the PCB is reduced. For raising the capacitive characteristics and restraining noise in the PCB, different dielectric materials are added in the inner layer of substrate in prior art. The main purpose of forming a built-in capacitor using a high dielectric coefficient substrate is to reduce the area of the PCB. Nevertheless, once the area is reduced, inaccuracy increases due to the alignment error in the manufacturing process of the PCB. If the precision of the manufacturing process is insufficient, inaccuracy is easily produced by compression alignment errors, and a difference between the two plates in the manufacturing process will not provide high-precision discrete capacitor.
In the top view of built-in capacitor shown in
The present invention thus employs different sized plates formed with non-symmetrical electrodes as the capacitive apparatus of built-in capacitor, where the bigger one will cover the smaller one to reduce the error compression alignment and improve the noise-immunity and efficiency of a capacitive substrate with a high precision capacitor.
Broadly speaking, the present invention discloses a capacitive apparatus and manufacturing method for a built-in capacitor with non-symmetrical electrode, which employs a plurality of different sized metal laminates stacked built-in capacitor in the manufacturing process of a PCB and reduces the error in process of compression alignment for raising the capability of noise-immunity in a PCB and promoting integral capacitance.
The present invention relates to the non-symmetrical electrodes used in a PCB for increasing capacitance and promoting the precision in the manufacturing process thereof. The capacitive apparatus comprises a first plate and a second plate separated from the first plate by a distance. The size of the second plate is different from that of the first plate, and the bigger one covers the smaller one. A dielectric is located between the first and second plate.
The present invention will be readily understood by the following detailed description in conjunction with the accompanying drawings, in which:
The capacitor for noise-filtering or voltage-stabilizing in a printed circuit board (PCB) is required to work at high frequency and be small in size, such that a capacitive substrate must be built in the PCB. The present invention discloses a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode to reduce the effect of misalignment of substrates built in the PCB. In other words, to improve the precision of the capacitive substrate, the invention adopts a plurality of metal laminates with a non-symmetrical area to compensate for misalignment, and as a substitute for the capacitor with an equal-area electrode.
Reference is made to
The shape of the plates is not limited to a rectangle as described above. A built-in capacitor with triangular form (71,72) as shown in
When the size of plates is continuously enlarged, as the second equivalent capacitor C2 and third equivalent capacitor C3 shown in
Reference is made to
As shown in
Like the steps disclosed in
Reference is made to
The present invention relates to a capacitive apparatus and manufacturing method for a built-in capacitor with a non-symmetrical electrode used to raise the capability of noise-immunity of a capacitive PCB applied to high frequency/speed modules and systems, and also provides least-error capacitance to regular circuit design requiring compact package and high-precision capacitance in the future.
The many features and advantages of the present invention are apparent from written description above and those it is intended by appended claims to cover all. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and operation as illustrated and described. Hence, all suitable modifications and equivalents may be resorted to as falling within the scope of the invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4312024 *||Apr 24, 1980||Jan 19, 1982||General Electric Company||Fixed adjusted flat capacitor|
|US5027253 *||Apr 9, 1990||Jun 25, 1991||Ibm Corporation||Printed circuit boards and cards having buried thin film capacitors and processing techniques for fabricating said boards and cards|
|US5079069||Aug 23, 1989||Jan 7, 1992||Zycon Corporation||Capacitor laminate for use in capacitive printed circuit boards and methods of manufacture|
|US5745333 *||Nov 21, 1994||Apr 28, 1998||International Business Machines Corporation||Laminar stackable circuit board structure with capacitor|
|US6349456 *||Dec 31, 1998||Feb 26, 2002||Motorola, Inc.||Method of manufacturing photodefined integral capacitor with self-aligned dielectric and electrodes|
|US6421225 *||Jun 15, 1999||Jul 16, 2002||Telefonaktiebolaget Lm Ericsson (Publ)||Electric component|
|US20010014004 *||Mar 25, 1999||Aug 16, 2001||Robert J. Sanville||Parallel plate buried capacitor|
|US20030223177 *||Jun 3, 2003||Dec 4, 2003||Mitsutoshi Higashi||Substrate-embedded capacitor, production method thereof, and circuit board|
|US20040108134 *||Sep 16, 2003||Jun 10, 2004||Borland William J.||Printed wiring boards having low inductance embedded capacitors and methods of making same|
|US20040120097 *||Dec 23, 2002||Jun 24, 2004||Chambers Stephen T.||Methods of forming metal-insulator-metal capacitors|
|US20040124493 *||Mar 28, 2002||Jul 1, 2004||Chua Ah Lim||Method for forming a printed circuit board and a printed circuit board formed thereby|
|US20040231885 *||Feb 4, 2004||Nov 25, 2004||Borland William J.||Printed wiring boards having capacitors and methods of making thereof|
|US20050078432 *||Jan 27, 2004||Apr 14, 2005||Maxwell Technologies, Inc.||Capacitor with battery form factor housing|
|JP2001291637A||Title not available|
|TW330370B||Title not available|
|TW511417B||Title not available|
|TW524381B||Title not available|
|TW564445B||Title not available|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7884409 *||Jun 8, 2007||Feb 8, 2011||Samsung Electronics Co., Ltd.||Semiconductor device and method of fabricating the same|
|US8077443||Apr 25, 2008||Dec 13, 2011||Industrial Technology Research Institute||Capacitor structure with raised resonance frequency|
|US20080054329 *||Jun 8, 2007||Mar 6, 2008||Kim Yoon-Hae||Semiconductor device and method of fabricating the same|
|U.S. Classification||361/311, 361/761, 361/301.4, 361/323|
|International Classification||H05K1/16, H01G4/06, H01G4/30, H01G4/08, H01G4/012, H01G4/005, H05K1/00|
|Cooperative Classification||H05K1/0298, H05K2201/09518, H01G4/012, H05K2201/09672, H05K1/162, H05K2201/09509|
|European Classification||H01G4/012, H05K1/16C|
|Jul 21, 2004||AS||Assignment|
Owner name: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUE, TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:JOW, UEI-MING;LAI, YING-JIUNN;WU, CHUN-KUN;AND OTHERS;REEL/FRAME:015601/0917
Effective date: 20040713
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