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Publication numberUS7113008 B2
Publication typeGrant
Application numberUS 11/222,011
Publication dateSep 26, 2006
Filing dateSep 8, 2005
Priority dateSep 8, 2004
Fee statusPaid
Also published asUS20060057998
Publication number11222011, 222011, US 7113008 B2, US 7113008B2, US-B2-7113008, US7113008 B2, US7113008B2
InventorsBevin George Perumana, Sudipto Chakraborty, Chang-Ho Lee, Joy Laskar, Sang-hyun Woo
Original AssigneeSamsung Electronics Co., Ltd., Georgia Tech Research Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Frequency mixing apparatus
US 7113008 B2
Abstract
A frequency mixing apparatus is provided. In the frequency mixing apparatus, a PMOS transistor is coupled to an NMOS transistor in a cascode configuration and an LO signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal. High isolation between the bulks and gates of the transistors resulting from application of the LO signal to the bulks prevents leakage of the LO signal, thereby decreasing a DC offset voltage. This renders the frequency mixing applicable to a DCR. Also, due to the cascade configuration similar to an inverter configuration, the frequency mixing apparatus can be incorporated in an FPGA of a MODEM in SDR applications. Frequency mixing based on switching of a threshold voltage decreases a noise factor and enables frequency mixing in a low supply voltage range, thereby decreasing power consumption.
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Claims(5)
1. A frequency mixing apparatus comprising:
a P-channel metal oxide semiconductor (PMOS) transistor having a source connected to a power voltage, a gate for receiving an input signal, and a bulk for receiving a local oscillator (LO) signal; and
an N-channel metal oxide semiconductor (NMOS) transistor having a source connected to the ground, a drain connected to a drain of the PMOS transistor, a gate for receiving the input signal, and a bulk for receiving the LO signal,
wherein the input signal is mixed with the LO signal and a mixed signal is output through the drains of the PMOS transistor and the NMOS transistor.
2. The frequency mixing apparatus of claim 1, further comprising:
a first capacitor serially connected between the bulk of the PMOS transistor and a port to which the LO signal is applied; and
a second capacitor serially connected between the bulk of the NMOS transistor and the port to which the LO signal is applied.
3. The frequency mixing apparatus of claim 1, further comprising:
a first resistor connected in parallel between the source and bulk of the PMOS transistor; and
a second resistor connected in parallel between the source and bulk of the NMOS transistor.
4. The frequency mixing apparatus of claim 1, further comprising a third resistor connected in parallel between the ground and a port which connects the drain of the PMOS transistor to the drain of the NMOS transistor.
5. The frequency mixing apparatus of claim 1, further comprising an inductor between a port to which the input signal is applied and a port which connects the gate of the PMOS transistor to the gate of the NMOS transistor.
Description
PRIORITY

This application claims priority under 35 U.S.C. 119 to a provisional application entitled Harmonic Frequency Converter Using Four Terminal Square Law filed in the U.S. Patent Office on Sep. 8, 2004 and assigned Ser. No. 60/607,921 and an application entitled Frequency Mixing Apparatus filed in the Korean Intellectual Property Office on Mar. 11, 2005 and assigned Ser. No. 2005-20622, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a frequency mixing apparatus, and in particular, to a frequency mixing apparatus in which a P-channel metal oxide semiconductor (PMOS) transistor is coupled to an N-channel metal oxide semiconductor (NMOS) transistor in a cascode configuration and a local oscillator (LO) signal is applied to the bulks of the PMOS and NMOS transistors so that an input signal applied to their gates is mixed with the LO signal.

2. Description of the Related Art

Typically, a mixer is used for frequency conversion when designing a radio frequency (RF) transceiver in a mobile communication system. Since this mixer relies on the non-linearity of diodes or metal-semiconductor field effect transistors (MESFETs), a large number of harmonic waves and intermodulation distortion (IMD) signals are produced when an RF or intermediate frequency (IF) signal and a LO signal are applied.

FIG. 1 is a circuit diagram of a conventional frequency mixer. Referring to FIG. 1, the frequency mixer is a kind of multiplier. An output signal Vout is the product of an input signal Vin and a LO signal VLO. That is, the output signal Vout is a signal having the voltage level of the input signal Vin at the frequency of the LO signal VLO.

The frequency mixer includes three differential amplifiers. A differential amplifier with two transistors Q1 and Q2 generates an output proportional to the difference between inputs Vin, that is, the difference between the collector currents of the transistors Q1 and Q2, IC1IC2. Specifically, as the input signal Vin swings between positive (+) and negative (−) values, the collector currents IC1 and IC2 flowing through the transistors Q1 and Q2 also swing.

The collector current IC1 of the transistor Q1 is the output current of another differential amplifier with transistors Q3 and Q4. The collector current CC2 of the transistor Q2 is the output current of a third differential amplifier with transistors Q5 and Q6. These two differential amplifiers generate outputs proportional to the difference between LO signals VLO. More specifically, along with the swing of the LO signal VLO, the outputs (IC3IC5) and (IC4IC6) of the differential amplifiers also swing in opposite directions. Consequently, each of the transistor pairs Q3 & Q4 and Q5 & Q6 can be replaced with complementary switches. When viewed as switches, the two transistors Q3 and Q6 are turned on/off simultaneously and the two transistors Q4 and Q5 are also turned on/off simultaneously.

Current IL1 flowing through a resistor RL1 is the sum of the collector current IC3 of the transistor Q3 and the collector current IC5 of the transistor Q5. Current IL2 flowing through a resistor RL2 is the sum of the collector current IC4 of the transistor Q4 and the collector current IC6 of the transistor Q6.

Therefore, the differential amplifier with the transistors Q1 and Q2 operates depending on the operations of the differential amplifier with the transistors Q3 and Q4 and the differential amplifier with the transistors Q5 and Q6. This means that the output signal Vout is equivalent to the waves of the input signal Vin at the voltage level of the LO signal VLO. This type of frequency mixer is typical and its output signal Vout is expressed as Vout=RL/REVinVLO.

The above conventional frequency mixer mixes frequencies by controlling the switching of the input signal by means of the LO signal. It exhibits the drawbacks of very poor linearity, unavailability in a low supply voltage range, great power consumption in the case of increasing the supply voltage range, and the increase of high direct current (DC) offset voltage level caused by leakage current of transistors.

SUMMARY OF THE INVENTION

An object of the present invention is to substantially solve at least the above problems and/or disadvantages and to provide at least the advantages described below. Accordingly, an object of the present invention is to provide a frequency mixing apparatus with transistors coupled in a cascade configuration, for operating in a low supply voltage range.

Another object of the present invention is to provide a frequency mixing apparatus having a low DC offset voltage by applying an LO signal to the bulk ports of transistors.

The above object is achieved by providing a frequency mixing apparatus. In the frequency mixing apparatus, a PMOS transistor has a source connected to a power voltage, a gate for receiving an input signal, and a bulk for receiving an LO signal, an NMOS transistor has a source connected to the ground, a drain connected to a drain of the PMOS transistor, a gate for receiving the input signal, and a bulk for receiving the LO signal. The input signal is mixed with the LO signal and the mixed signal is output through the drains of the PMOS transistor and the NMOS transistor.

The frequency mixing apparatus may further include a first capacitor serially connected between the bulk of the PMOS transistor and a port to which the LO signal is applied, a second capacitor serially connected between the bulk of the NMOS transistor and the port to which the LO signal is applied, a first resistor connected in parallel between the source and bulk of the PMOS transistor, a second resistor connected in parallel between the source and bulk of the NMOS transistor, a third resistor connected in parallel between the ground and a port which connects the drain of the PMOS transistor to the drain of the NMOS transistor, and an inductor between a port to which the input signal is applied and a port which connects the gate of the PMOS transistor to the gate of the NMOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which:

FIG. 1 is a circuit diagram of a conventional frequency mixer;

FIG. 2 is a circuit diagram of a frequency mixing apparatus according to an embodiment of the present invention; and

FIG. 3 is a circuit diagram of a frequency mixing apparatus according to an alternative embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be described herein below with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

FIG. 2 is a circuit diagram of a frequency mixing apparatus according to an embodiment of the present invention. Referring to FIG. 2, in the frequency mixing apparatus, a PMOS transistor P1 is coupled to an NMOS transistor N1 in a cascade configuration. In other words, the drain of the PMOS transistor P1 is coupled to the drain of the NMOS transistor N1.

According to the present invention, the gate of the PMOS transistor P1 is coupled to that of the NMOS transistor N1 and an input signal Vin is applied to the gates. Also, the bulks of the PMOS transistor P1 and the NMOS transistor N1 are coupled to each other and an LO signal LO is applied to the bulks. An output signal Vout is output from the drains of the PMOS transistor P1 and the NMOS transistor N1. The source of the PMOS transistor P1 is connected to a power voltage Vdd and the source of the NMOS transistor N1 is grounded.

In operation, when an RF signal is applied as the input signal Vin, and it is mixed with the LO signal LO, an intermediate frequency (IF) signal is output as the output signal Vout. If the input signal Vin is an IF signal, and it is mixed with the LO signal LO, an RF signal is output as the output signal Vout.

The principle of frequency mixing will be described with reference to mathematical formulas.

For the NMOS transistor N1, current iD is given by Equation 1:
i D=β(v GS −v t)2(1+λv DS)  (1)
where β is a constant of electron mobility, oxide capacitance, device width, or device length, vGS is a voltage level between the gate and source of the NMOS transistor N1, vt is the threshold voltage level of the NMOS transistor N1, λ is a channel length modulation coefficient, and vDS is a voltage level between the drain and source of the NMOS transistor N1.

Then vt is expressed as Equation 2:
v t =v t0+γ(√{square root over (2φ +v SB)}−√{square root over (2φ)})  (2)
where vt0 is a threshold voltage level in the absence of body effect, γ is a body effect coefficient, φ is a work function, and vSB is a voltage level between the source and bulk of the NMOS transistor N1.

Equation 1 and Equation 2 combine to yield Equation 3:
(v GS −v t)2=(v GS −v t0−γ(√{square root over (2φ +v SB)}−√{square root over (2φ )})) 2  (3)

Using a Taylor series expansion for √{square root over (2φ+vSB)}−√{square root over (2φ )}, the following Equation 4 results:

( v GS - v t ) 2 = ( v GS - v t0 - γ 2 ϕ f ( 1 2 ( v SB 2 ϕ f ) - 1 8 ( v SB 2 ϕ f ) 2 + 1 16 ( v SB 2 ϕ f ) 3 - ) ) 2 ( 4 )

Equation 4 is in the form of (a−b)2. Conversion of Equation 4 to the form of 2ab leads to Equation 5:

2 v GS v t = 2 ( v GS - v t ) γ 2 ϕ f ( 1 2 ( v SB 2 ϕ f ) - 1 8 ( v SB 2 ϕ f ) 2 + 1 16 ( v SB 2 ϕ f ) 3 - ) ( 5 )

Equation 5 reveals that with application of the LO signal LO to the bulks of the PMOS transistor P1 and the NMOS transistor N1, subharmonic mixing is facilitated. For harmonic mixing, conversion gains can be derived from Equation 5.

The term (vGS−vt) is expressed as Equation 6:

( v GS - v t ) = A 1 + B 1 cos ( w RF t ) = A 1 + B 1 cos ( w RF t ) 2 γ 2 ϕ f ( 6 )
where A′1, B′1, A1 and B1 are constants and wRF is an RF frequency.

VSB is expressed by Equation 7:
v SB =A′ 2 +B′ 2 cos(w LO t)=[A 2 +B 2 cos(w LO t)]2φ  (7)
where A′2, B′2, A2 and B2 are constants and wLO is an LO frequency.

Since an RF signal is applied as VGS and the LO signal is applied as VSB, under the assumption that (vGS−vt) and VSB are given as Equation 6 and Equation 7, respectively, harmonic conversion gains are determined, according to Equation 5, by Equation 8, Equation 9 and Equation 10.

Frequency conversion by the LO frequency is represented by Equation 8:

1 X : 1 4 B 1 B 2 [ cos { ( w RF - w LO ) t } + cos { ( w RF - w LO ) t } ] ( 8 )

Frequency conversion by 2LO frequency is represented by Equation 9:

2 X : 1 32 B 1 ( B 2 ) 2 [ cos { ( w RF - 2 w LO ) t } + cos { ( w RF - 2 w LO ) t } ] ( 9 )

Frequency conversion by 3LO frequency is represented by Equation 10:

3 X : 1 128 B 1 ( B 2 ) 3 [ cos { ( w RF - 3 w LO ) t } + cos { ( w RF - 3 w LO ) t } ] ( 10 )

In this way, frequency mixing is carried out utilizing not the change of the drain current but the change of the threshold voltage.

FIG. 3 is a circuit diagram of a frequency mixing apparatus according to an alternative embodiment of the present invention. Like reference numeral denote the same components as shown in FIG. 2 and redundant descriptions are avoided herein.

Referring to FIG. 3, the frequency mixing apparatus further includes resistors Rb and RL, capacitors Cc, and an inductor L in addition to the components illustrated in FIG. 2.

The inductor L is used for impedance matching of the input signal Vin, and the capacitors Cc function to remove a DC component. The resistors Rb and RL are provided to control a DC voltage.

In accordance with the present invention as described above, since an LO signal is applied to the bulk of a transistor, the resulting high isolation between the bulk and gate of the transistor prevents leakage of the LO signal, thereby decreasing a DC offset voltage. Hence, the frequency mixing apparatuses of the present invention are applicable to a direct conversion receiver (DCR). Especially, the present invention provides a DC offset attenuation method applicable to general-purpose terminals, not limited to particular applications.

In the frequency mixing apparatuses of the present invention, a PMOS transistor is coupled to an NMOS transistor in a cascade configuration, which is similar to an inverter configuration. Therefore, they can be incorporated in a field-programmable gate array (FPGA) of a MODEM in software-defined radio (SDR) applications.

In addition, frequency mixing based on switching of a threshold voltage decreases a noise factor and is viable in a low supply voltage range. Therefore, power consumption is decreased. Since the output comes from between the PMOS and NMOS transistors, a higher gain can be achieved by increasing an output impedance.

While traditionally, a different DC offset attenuation method is used, application by application, and applications for which DC offset attenuation is viable are limited, the present invention eliminates the cause of DC offsets. Accordingly, the present invention can find its use in all small-size, low-power terminals including 4th generation (4G) mobile terminals as well as global system for mobile telecommunication (GSM), code division multiple access (CDMA), and wireless local area network (WLAN) terminals.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7622983 *Mar 16, 2007Nov 24, 2009Stmicroelectronics S.A.Method and device for adapting the voltage of a MOS transistor bulk
US8258861Jan 8, 2010Sep 4, 2012Analog Devices, Inc.Systems and methods for minimizing power consumption
Classifications
U.S. Classification327/113, 455/313
International ClassificationH03B19/00
Cooperative ClassificationH03D7/125
European ClassificationH03D7/12A
Legal Events
DateCodeEventDescription
Mar 5, 2014FPAYFee payment
Year of fee payment: 8
Mar 11, 2010FPAYFee payment
Year of fee payment: 4
Nov 1, 2005ASAssignment
Owner name: GEORGIA TECH RESEARCH CORPORATION, GEORGIA
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PERUMANA, BEVIN GEORGE;CHAKRABORTY, SUDIPTO;LEE, CHANG-HO;AND OTHERS;REEL/FRAME:017282/0458;SIGNING DATES FROM 20050902 TO 20050929