|Publication number||US7117346 B2|
|Application number||US 10/159,386|
|Publication date||Oct 3, 2006|
|Filing date||May 31, 2002|
|Priority date||May 31, 2002|
|Also published as||CN1856770A, CN100472453C, EP1573444A2, US20030226001, WO2003102723A2, WO2003102723A3|
|Publication number||10159386, 159386, US 7117346 B2, US 7117346B2, US-B2-7117346, US7117346 B2, US7117346B2|
|Inventors||William C. Moyer, John H. Arends|
|Original Assignee||Freescale Semiconductor, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Non-Patent Citations (3), Referenced by (4), Classifications (11), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to a data processing system, and more specifically, to a data processing system having multiple register contexts.
In data processing systems, such as microprocessors, a processor is utilized to control execution and processing of operations. The processor includes registers which store a register context which is utilized by the processor during normal operation and exception processing. When an interrupt or process switch occurs, the register context information may be corrupted because the interrupt processing program or the new process will use the same registers and may change some of the values therein.
One solution to the above mentioned problem is to save the current values of the register context in a memory prior to beginning the processing of the interrupt or the new process, and reading the saved register context values back into the registers from the memory when the interrupt processing is complete or when returning back to the current process. However, the overhead of saving the register context, and loading a new context is undesirable in a real-time or high-performance environment. Therefore, a need exists for a register context selection scheme in a data processing system which is flexible and reduces overhead.
The present invention is illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve the understanding of the embodiments of the present invention.
As used herein, the term “bus” is used to refer to a plurality of signals or conductors which may be used to transfer one or more various types of information, such as data, addresses, control, or status. The terms “assert” and “negate” (or “deassert”) are used when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one. The symbol “$” preceding a number indicates that the number is represented in its hexadecimal or base sixteen form. The symbol “%” preceding a number indicates that the number is represented in its binary or base two form.
Note that in some embodiments of the present invention, data processing system 10 is formed on a single integrated circuit. Additionally, in some embodiments, data processing system 10 may be a single chip microcontroller, a microprocessor, a digital signal processor, or any other type of data processing system. Furthermore, data processing system 10 may be implemented using any type of electrical circuitry. External device 2 may be any type of electrical circuit, including a memory or any type of peripheral device. Alternate embodiments may include more, fewer, or different external integrated circuits. In addition buses 4 and 6 can be implemented using any number of bits.
In operation, system integration 22 is used to allow communication between processor 12 and external device 2. That is, processor 12 passes data and address information via internal buses 14 and 13 to system integration 22 which then passes the data and address information via buses 4 and 6 in a method and format appropriate for external device 2. Processor 12 will be discussed in more detail below in reference to
Therefore, a register context refers to the contents of the registers described above (the registers of context 51). Alternate embodiments may define a register context as having all or some of the same registers of register context 51, or may include a different set of registers from those of register context 51. Therefore, as used herein, a register context can be defined to have any number and any type of registers. Typically, a register context contains register resources that form all or a portion of a programmers' register model for a processor. During normal operation or upon power up or reset, data processing system 10 may default to utilizing context 0 34. (Note that in alternate embodiments, normal operation may default to a different context.) However, when an interrupt or process switch occurs, so as not to corrupt the values in context 0 34, data processing system 10 selects a new context (from context 1 to N) for processing the interrupt or executing the new process or thread. Therefore, interrupt handling and process switching (e.g. multithreading) may result in a need for register context switching within data processing system 10. Also, in some embodiments, it may be desirable to share a portion of the registers within a register context with another register context. Therefore, as will be described below, portions of a register context may be mapped into another register context to help reduce overhead and increase the speed during a context switch.
In data processing system 10, exceptions and interrupts are recognized at a decode stage or an execution stage of instruction pipeline 28. Thus, when an instruction is provided to instruction decode circuit 30 and decoded, an interrupt may be recognized and processed, in lieu of normal instruction processing. In one embodiment described herein, there are multiple interrupt levels which determine whether a given interrupt has priority over any other interrupt. Thus, and interrupt with a high priority will get processed more quickly than an interrupt with a lower priority, which must wait for processing. Each interrupt or type of interrupt or interrupt having a same priority may therefore share a same register context if desired.
When an interrupt is received, data processing system 10 begins to execute an exception processing sequence. During this sequence, vector offset generator 39 provides a vector offset value via vector offset bus 27 to address generator 26. Address generator 26 uses the vector offset value to form an instruction address at which execution is to begin for processing the interrupt. In one embodiment, in addition to the vector offset value, vector offset generator also provides a context selector indicating the register context to be used for the interrupt processing. In one embodiment, the context selector is a part of the vector offset value, or may be a separate value provided by vector offset generator 39. Also, the context selector can be provided directly to register file 32. In alternate embodiments, the context selector can be a value read from a memory (not illustrated) or may be received via an instruction. In the case of data processing system 10 having 8 register contexts in register file 32, the context selector may be a 3-bit value used to identify one of the register contexts.
Also, data processing system 10 may be capable of process switching where processor 12 is capable of switching from one process to another, where each process may operate in a different register context. For example, in a multi-threading application, processor 12 may continually switch among various processing threads, where different processing threads (or groups of processing threads) use a different register context. In the case of process switching, an interrupt may be used to indicate a process switch to data processing system 10 (where the interrupt handling includes switching processes). Alternatively, other methods may be used to indicate to address generator 26 that a process switch is necessary such that address generator 26 can generate a starting address for the new process. Also, upon a process switch, a context selector is also provided to indicate which register context is needed for the new process. As described above, the context selector can be provided in a variety of different ways (i.e. from vector offset generator 39, from a memory, from a user instruction, etc.) and can be provided directly or indirectly (e.g. via address generator 26) to register file 32 such that the correct register context can be selected.
Once a register context has been established, instructions executed by processor 12 will reference the appropriate general purpose registers (GPRs 50) or special purpose registers (e.g. LR 54, CTR 56, CR 58, XER 60, MSR 62, or CTXCR 64) corresponding to the currently established context. Registers within other contexts will not be affected (unless a mapping has been established as will be described below), thus no saving or restoring of alternate contexts to memory need be performed prior to execution of instructions for the currently established context. This provides for a savings in overhead.
Note that stack pointer register 76 (of context 0 70) and stack pointer register 78 (of context 1 72) are not mapped; therefore, when operating in these register contexts, no other register contexts need to be accessed when accessing the stack pointer. Context control registers 77, 79, and 75 within each of register contexts 70, 72, and 74, respectively, indicate whether the stack pointer of the corresponding register context is mapped, and if so, to which other register context it is mapped to. The details of the context control register will be discussed in more detail below in reference to
The register contexts of
For example, as illustrated by arrow 120, group 118 of register context 2 92 is mapped to group 106 of register context 1 90. As shown by arrow 126, group 112 of register context 3 94 is also mapped to group 106 of register context 1 90. That is, the registers of group 106 are shared by all three register contexts: register context 1 90, register context 2 92, and register context 3 94. Therefore, when executing either Process B or Process C, an access to GPR 28–31 of the current register context (register context 2 92 or register context 3 94, respectively) actually results in an access to GPR 28–31 of register context 1 90. Also illustrated in
The mappings of each register context is defined in the context control register of each register context (for example, context control registers 128, 130, and 132 of
Bit 0 of context control register 140 corresponds to a context enable field 142 which enables the use of multiple register contexts. For example, if context enable field 142 is negated, only a single context is enabled, all other control fields in context control 140 are ignored, and the current context is set to the default register context (which, in the embodiment illustrated in
Bits 6–8 correspond to a current context field 146 which defines the currently enabled register context. In one embodiment, this field is cleared to 0 upon reset to indicate that the default register context is register context 0. The current context field 146 corresponds to the context selector discussed above which may be provided in a variety of different ways, such as by vector offset generator 39 of
Note that while each register context has its own context control register, some of the fields may be shared among the different context control registers. For example, a single context enable bit, a single number of contexts field, and a single current context field may be implemented which is used by all the context control registers since the value is always the same among the different context control registers. Alternate embodiments may use a context enable or a number of contexts field or a current context field for each context control register, but by using a single shared field for each reduces hardware requirements.
Bits 9–11 correspond to a saved context field 148 which defines the previously enabled context. Note that this field can also be cleared to 0 upon reset. Therefore, in the above example of switching from Process A to Process B (referring to
Bits 12–14 correspond to the alternate context field 150 which defines an alternately enabled context which is used to define a context mapping for register groups. Bits 15–18 correspond to mapping fields 151. Bit 15 corresponds to a register group A (defined as GPR 4–7), bit 16 to corresponds to register group B (defined as GPR 8–11), bit 17 to register group C (defined as GPR 16–23), and bit 18 to register group D (defined as GPR 27–31). Each of the register groups A–D can be independently enabled by asserting the corresponding bit. For example, if bit 15 is asserted, group A is enabled such that group A is mapped to the register context defined by the alternate context field. If bit 15 is negated, group A is not mapped. Similarly, if bits 16, 17, or 18 are asserted, then the corresponding group of registers (B, C, or D, respectively) is mapped to the register context defined by the alternate context field. If bits 16, 17, or 18 are negated, then the corresponding group of registers (B, C, or D, respectively), are not mapped. Therefore, referring to
In the example context control register, context control register 140, of
Bit 24 of context control register 140 corresponds to a stack pointer context enable field 152 which enables mapping of the stack pointer, as discussed in reference to both
The context control register can be programmed in a variety of different ways. For example, in one embodiment, each context control register can be user programmed directly. Alternatively, the context control registers can be mapped indirectly using the alternate context field of the current context control register. For example, in one embodiment, upon power up or reset, data processing system defaults to register context 0. The alternate context field can then be set to a value indicating which register context's context control register is to be programmed. For example, while in register context 0, a writing of a value of 2 to the alternate context field of the context control register of register context 0 allows access to the programming of the context control register of register context 2 via a special purpose register. After all of the context control fields have been programmed, they can all be enabled simultaneously (which, in the case of having a single shared context enable field is done by asserting this bit). Also, in one embodiment, interrupt processing may be turned off during the programming of context control registers.
Note that context control register 140 has been described in reference to particular fields and bit locations. Note that alternate embodiments may include more or less fields, as needed, and each field may include more or less bits, as needed. Also, in alternate embodiments, context control registers may be located anywhere within data processing system 10, or may be located external to data processing system 10.
Therefore, it can be appreciated how the context control register can be used to provide for flexible context selection with reduced overhead. Upon a context switch within data processing system 10, the context control register of the new register context is updated. For example, the new register context is written to the current context field, the previous context gets written to the saved context field, and the register mappings provided within the mapping fields are used when operating within the new register context. The register mappings allow for different register contexts to share register values. Also, the register mappings allow for access of other register contexts outside the current register context, as defined by the context control register of the current register context. Also, the user programmable context control registers allow for flexibility in how the mappings are defined. Therefore, one aspect of the present invention described herein provides a flexible mechanism to map portions of an alternate register context onto a current register context (and vice versa) and provides for flexible sharing of common stack pointers among multiple contexts, thus resulting in improved real-time performance. By mapping portions of the current context onto an alternate context, the overhead of transferring information values between operating contexts can be removed or eliminated, resulting in improved performance and flexibility.
In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. For example, the block diagrams may have different blocks than those illustrated and may have more or less blocks or be arranged differently. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5386563 *||Oct 13, 1992||Jan 31, 1995||Advanced Risc Machines Limited||Register substitution during exception processing|
|US5426766 *||Aug 23, 1994||Jun 20, 1995||Nec Corporation||Microprocessor which holds selected data for continuous operation|
|US5680599 *||Dec 22, 1995||Oct 21, 1997||Jaggar; David Vivian||Program counter save on reset system and method|
|US5812868||Sep 16, 1996||Sep 22, 1998||Motorola Inc.||Method and apparatus for selecting a register file in a data processing system|
|US6029242||Oct 20, 1997||Feb 22, 2000||Sharp Electronics Corporation||Data processing system using a shared register bank and a plurality of processors|
|US6134578||May 2, 1996||Oct 17, 2000||Texas Instruments Incorporated||Data processing device and method of operation with context switching|
|US6145049||Dec 29, 1997||Nov 7, 2000||Stmicroelectronics, Inc.||Method and apparatus for providing fast switching between floating point and multimedia instructions using any combination of a first register file set and a second register file set|
|US6154832||Dec 4, 1998||Nov 28, 2000||Advanced Micro Devices, Inc.||Processor employing multiple register sets to eliminate interrupts|
|US6170997||Jul 22, 1997||Jan 9, 2001||Intel Corporation||Method for executing instructions that operate on different data types stored in the same single logical register file|
|US20020002667||Dec 21, 2000||Jan 3, 2002||Kelsey Nicholas J.||System and method for instruction level multithreading in an embedded processor using zero-time context switching|
|WO2000079394A1||Jun 21, 2000||Dec 28, 2000||Bops Inc||Methods and apparatus for providing manifold array (manarray) program context switch with array reconfiguration control|
|1||Kogge, Peter M. et al.; "PIM Architectures to Support Petaflops Level Computation in the HTMT Machine"; 2000; pp. 35-44; IEEE.|
|2||Konuru, Ravi et al.; "A User-Level Process Package for PVM"; 1994; pp. 48-55; IEEE.|
|3||Nuth, Peter R. et al.; "The Named-State Register File: Implementation and Performance"; 1995; pp. 4-13; IEEE.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7401206 *||Jun 30, 2004||Jul 15, 2008||Sun Microsystems, Inc.||Apparatus and method for fine-grained multithreading in a multipipelined processor core|
|US7562207 *||Oct 26, 2005||Jul 14, 2009||Innovasic, Inc.||Deterministic microcontroller with context manager|
|US7590774 *||Dec 1, 2005||Sep 15, 2009||Kabushiki Kaisha Toshiba||Method and system for efficient context swapping|
|US20060004995 *||Jun 30, 2004||Jan 5, 2006||Sun Microsystems, Inc.||Apparatus and method for fine-grained multithreading in a multipipelined processor core|
|U.S. Classification||712/228, 712/217, 712/E09.027, 712/244|
|International Classification||G06F9/30, G06F12/00, G06F, G06F9/00, G06F1/00|
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