|Publication number||US7117469 B1|
|Application number||US 10/264,691|
|Publication date||Oct 3, 2006|
|Filing date||Oct 3, 2002|
|Priority date||Nov 28, 2001|
|Publication number||10264691, 264691, US 7117469 B1, US 7117469B1, US-B1-7117469, US7117469 B1, US7117469B1|
|Original Assignee||Magma Design Automation, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (1), Referenced by (32), Classifications (8), Legal Events (11)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This patent application claims priority to the copending provisional patent application Ser. No. 60/334,137, entitled “PADRING DESIGN,” and with filing date Nov. 28, 2001. This patent application claims priority to the copending provisional patent application Ser. No. 60/352,920, entitled “PADRING GENERATION,” and with filing date Jan. 28, 2002.
1. Field of the Invention
Embodiments of the present invention generally relate to generating chip layout designs. More particularly, embodiments of the present invention relate to generating the padring layout design.
2. Related Art
Typically, the integrated circuit (or chip) design process begins with a specification which describes the functionality of the chip and may include a variety of constraints. Then, during a logic design phase, the logical implementation of the integrated circuit is determined. Several operations are performed to obtain a logical representation of the integrated circuit. Generally, EDA software tools use register transfer logic (RTL) to represent the integrated circuit. However, additional EDA software tools may be used.
After completing the logic design phase, the chip undergoes a physical layout design phase. Typically, the output of the logic design phase is a netlist, which is then used in the physical layout design phase. Here, EDA software tools layout the integrated circuit to obtain a layout representation of the physical components in the integrated circuit, whereas the layout representation indicates the manner in which the integrated circuit will be fabricated on a semiconductor wafer. A variety of operations are performed on the layout of the integrated circuit.
At the end of the physical layout design phase, the final layout representation of the semiconductor chip (in which the integrated circuit is implemented is sent to a semiconductor manufacturing plant. Typically, the semiconductor chip is fabricated and then coupled to a package, whereas an electrical coupling is established between the padring of the semiconductor chip and the package.
During the physical layout design phase, the padring layout design is generated. The padring is an area where differing electrical, timing, physical, and logical views of the physical layout design come together. In particular, the padring is an interface for input signals, output signals, power signals, and ground signals between a semiconductor chip and off-chip components.
Moreover, laying out a padring with a high pin count, fast clock, low skew, and/or tight design schedule is a daunting task that can occupy a designer for months. The sheer amount of details that must be tracked and incorporated into the padring layout design is a management task in and of itself. Figuring out a pinout that will route in the package and still satisfy the constraints on the die (or chip) involves knowledge in many areas. High clock rates and tight skew requirements demand precision and regularity in the layout of I/O cells and associated routes in the padring. Considerations dealing with the die such as the distance from the core of the die to the I/O area in the padring can disclose the fact that the distance is often too far to guarantee timing. On the package side, the layout of the bumps/bond pads in the padring has to be coordinated with the package to deliver a system that works together. Last minute changes and design schedule pressure can help this problem become a nightmare unless a systematic approach is used.
Methods for generating a padring layout design are described. In particular, these methods utilize automation while still allowing customization. The task of generating the padring layout design is greatly aided by software configured to generate padring layout designs.
The variety of problems encountered when laying out padrings are addressed. Automation is emphasized as much as possible so that more time can be used to solve the various problems that make each padring layout design unique. A framework in which regular patterns can be described, replicated, and tailored is provided. The padring is broken down into zones in which slots having bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas are laid out in a regular pattern through an instantiation process. Edge logic, which is comprised of standard cells, is pulled from the core of the chip because these cells couple directly to I/O cells and are critical for timing. The framework allows the bumps/bond pads, I/O cells, and edge logic cells to be laid out in respective bumps/bond pads areas, I/O cell areas, and/or edge logic cell areas according to algorithms associated with the patterns and using a variety of maps which associate the logical netlist with the physical layout design.
In an embodiment, an editor and a GUI and a perl environment are provided which allow the resulting padring layout to be tailored to handle custom layout or exceptions in the patterns. This provides an environment for generating prototypes quickly to see if a pinout is feasible and determining packaging requirements. The padring layout design is generated in conjunction with package routing/selection and partitioning/floorplanning of the chip so that the chip-package-board system will work together. Finally, patterns can be saved and modified for use with future chips in the same chip family. This allows padring layout designs to be utilized despite shrinking and variability in future chip designs.
These and other advantages of the present invention will no doubt become apparent to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the present invention.
The drawings referred to in this description should not be understood as being drawn to scale except if specifically noted.
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be recognized by one of ordinary skill in the art that the present invention may be practiced without these specific details.
Some portions of the detailed descriptions which follow are presented in terms of procedures, logic blocks, processing, and other symbolic representations of operations on data bits within a computer memory. These descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. In the present application, a procedure, logic block, process, etc., is conceived to be a self-consistent sequence of steps or instructions leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated in a computer system. It has proved convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.
It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussions, it is appreciated that throughout the present invention, a variety of terms are discussed that refer to the actions and processes of an electronic system or a computer system, or other electronic computing device/system. The computer system or similar electronic computing device manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission, or display devices. The present invention is also well suited to the use of other computer systems such as, for example, optical, mechanical, or quantum computers.
Aspects of the present invention can be implemented or executed on a computer system or any other computational system. Although a variety of different computer systems can be used with the present invention, an exemplary computer system 100 is shown in
With reference to
Computer system 100 includes an address/data bus 110 for communicating information, a central processor 101 coupled with bus 110 for processing information and instructions, a volatile memory 102 (e.g., random access memory RAM) coupled with the bus 110 for storing information and instructions for the central processor 101 and a non-volatile memory 103 (e.g., read only memory ROM) coupled with the bus 110 for storing static information and instructions for the processor 101. Exemplary computer system 100 also includes a data storage device 104 (“disk subsystem”) such as a magnetic or optical disk and disk drive coupled with the bus 110 for storing information and instructions. Data storage device 104 can include one or more removable magnetic or optical storage media (e.g., diskettes, tapes) which are computer-readable memories. Memory units of computer system 100 include volatile memory 102, non-volatile memory 103 and data storage device 104.
Exemplary computer system 100 can further include a signal generating device 108 (e.g., a network interface card “NIC”) coupled to the bus 110 for interfacing with other computer systems. Also included in exemplary computer system 100 of
Methods for generating padring layout designs in an automated manner that is easily configurable, repeatable, and customizable are described. In an embodiment, a set of baseline patterns can be selected from a template library and then adapted based on the needs of the specific design situation. Alternatively, new patterns can be formed since an editor and a GUI and a perl environment are provided which allow the resulting padring layout to be tailored to handle custom layout or exceptions in the patterns. Patterns can define one or more slots, each slot having a bumps/bond pads area, an I/O area, and/or an edge logic area. Moreover, patterns are then repeated over particular padring areas using an instantiation process to create slots. The padring layout design and the slots can be customized. Later, bumps/bond pads, I/O cells, and edge logic cells are placed in the respective bumps/bond pads areas, I/O areas, and edge logic areas of the slots. This pattern generation, instantiation to create slots, and customizing/editing provide several benefits. By using these methods for generating padring layout designs, the user can quickly prototype a padring layout for floorplanning, experiment with what-if scenarios, and implement a detailed padring layout design ready for sign-off in an efficient manner.
The variety of problems and constraints encountered when laying out padrings are addressed by the present invention. One of the problems is the distance from a bump/bond pad to the first/last flip-flop can be large and variable; trying to achieve closure on timing in this environment is difficult and problematic. Pulling selected logic out of the core and associating it with a particular I/O cell solves that problem but creates many others such as how this logic will be placed, routed, and powered.
Another problem is that the bumps/bond pads are placed on a grid that is different from the standard cell grid in the core. This can cause misalignment in power straps and cells placed in each area. The placement of the bumps/bond pads and I/O cells is tied to the bump/bond pad pitch and has more to do with the package than features on the chip.
There are parts of a padring that are repetitious and so making changes to these parts at the last minute is tedious and error prone. There are other parts that are asymmetric or unique (i.e. PLL placement and hookup, shielding for source synchronous buses, temperature compensation or impedance matching logic) and must be handcrafted for a particular design. Changing one-of-a-kind parts is easier since they often are fewer in number but their layout could still benefit from an automated padring layout approach.
When choosing a package size and vendor, it is useful to explore various pinouts, pitches, and number of rows of bumps/bond pads. The price point and routing of the package must balance against the floorplan, pinout, and associated timing on the chip. Once a package is chosen and sent off to be manufactured, another challenge is to maintain that pinout while the chip is laid out and the design matures and goes through final timing adjustments.
Library changes at the last minute can change whether pins are pulled to the edge of cells or inset, their timing characteristics, and how they connect to the rest of the design. A small change in a library can translate into a large change in the padring layout design.
The automated padring layout approach of the present invention is well suited to handle the problems and constraints described above by providing a systematic and organized approach to generating the padring layout designs.
A BGA (ball grid array) padring 300A in accordance with an embodiment of the present invention is depicted in
A bond pad 400B in accordance with an embodiment of the present invention is shown in
Typically, the bump 400A and the bond pad 400B are each coupled to an I/O cell via a route metal. Although the description of the present invention will focus on the layout of a BGA padring 300A (
Associated with each area 510–530 within the slot 500 can be a grid, ordering function, orientation, and placement algorithm (or arrangement) chosen from a library. Each slot 500 is given a name when it is generated and can also be given an alias to reference it. The slot 500 provides the capability to represent everything needed to bring one signal, power, or ground into the chip. Each area 510–530 is optional. For example, a power pad (bump or bond pad) may not need an I/O area 520 or an edge logic area 530. Also, the pad (bump or bond pad) may be missing, for example a N/C (no connect). There can be more than one of each if needed. In essence, the slot 500 describes areas where the bump/bond pad metal, I/O cell, and standard cells are placed and how they are placed. As will be described below, patterns are used to define the slot 500 and replicate the slot 500 in the padring area. A pattern can define more than one slot 500. Through an instantiation process, the slots 500 are created by using the pattern over and over again in the padring area. The instantiation of slots 500 is what fixes their bump/bond pad area 510, I/O area 520, and edge logic area 530 to a specific position on the padring area of the chip. In an embodiment, an editor and a GUI and a perl environment are provided which allow the resulting padring layout to be tailored to handle custom layout or exceptions in the patterns and to form the patterns.
By varying the style and combining different patterns, the user has control over where the I/O cells and the standard cells are placed for each bump/bond pad on the die. Often a combination of styles is required to generate the appropriate padring layout design. For example, a padring layout design may have an outer pinwheel CW style 650, an inner style for a power ring comprised of the edges style 610 and the corners style 620, and a core/array style 630 over the core of the die for slots that have power/ground bumps.
Each zone 680 is the area of the padring in which patterns are used to create slots using an instantiation process. Any layout regularity in the zone is determined and incorporated into the pattern for the zone. The pattern is used as a template to populate each zone 680 with slots. An orientation and placement algorithm (or arrangement) can be associated with each zone 680 for controlling how the slots are oriented and placed in each zone 680. Additionally, a symmetry attribute can be associated with each zone 680.
A plurality of rotation values for an orientation attribute in accordance with an embodiment of the present invention are illustrated in
A plurality of rotation symmetry values for a symmetry attribute in accordance with an embodiment of the present invention are depicted in
A plurality of spacing values for a spacing attribute in accordance with an embodiment of the present invention are illustrated in
The “gap” spacing places a fixed sized gap between slots as they are placed. Any extra space is centered.
Moreover, for wire-bonded packages, it is desirable to place the slots farther apart near the corners of the die and closer together near the middle of the edge. This helps to alleviate problems due to the angle the wire makes with the edge. This is called “non-linear” spacing.
Patterns 1100 are instantiated over areas of the chip called zones 680 (
Patterns 1100 and slots 500 (
Simple padrings can make use of patterns 1100 also. For example, in wire-bond linear padrings, the bond pads can be staggered in order to reduce the pitch between I/O cells. A pattern of two slots could be used to describe this situation where one slot represents the inner bond pad and the other represents the outer bond pad. Repeating this pattern would yield a staggered effect in the bond pad positions.
Although the second pattern 1200 and the third pattern 1300 each defines six slots, the I/O areas are positioned differently and the edge logic areas are positioned differently, demonstrating the variability in the formation of patterns.
Although the pattern 1100 and the fourth pattern 1400 each defines four slots, the I/O areas are positioned differently and the edge logic areas are positioned differently, again demonstrating the variability in the formation of patterns.
A first instantiation in accordance with an embodiment of the present invention is shown in
Every padring layout design process has to define how the logical netlist and the physical bumps/bond pads are connected. Although a Verilog netlist cannot express it, this mapping is intrinsic to the design and is intimately associated with both the netlist and the package. A set of maps (e.g., bump/bond pad names map, I/O hints map, I/O map, and edge logic map) are carefully formulated to provide the required information in a way that does not introduce unnecessary dependencies between the design engineers producing the information. These maps are used for prototyping and the final sign-off and verification process. After the chip is placed and routed, the information contained in these maps can be reconstructed independently and compared to the input maps (initial maps). The coordinates of each bump/bond pad for use when wire-bonding or verifying the package will mate with the bump pattern can be determined and printed out.
A bump/bond pad names map 1800A in a first format in accordance with an embodiment of the present invention is depicted in
An I/O hints map 1900 in accordance with an embodiment of the present invention is illustrated in
The edge logic map 2100 is used to tell which standard cells will be pulled from the core, repartitioned into the zones described above, and placed with the placement algorithm specified by the slots in the zones. The position of the edge logic can be placed in the core area even though logically it is in the edge logic area. The position of the edge logic is determined by the pattern. Since patterns can cover any area of the chip, the edge logic can be placed over any area of the chip. Moreover, the edge logic map 2100 is separate from the I/O map 2000 since packaging changes do not affect the association of logic with a certain I/O cell. The format for the edge logic map 2100 is flexible and regular expressions (in perl or sh (shell script), for example) can be used to describe entire levels or individual cells in the netlist. Note that the I/O map 2000 is split apart from the edge logic map 2100 because it is written by users concerned with the package and die pinout and routing. The split of information allows the pinout to change and not affect the assignment of edge logic (or standard cells) to a given I/O cell of a slot. Likewise, the netlist can be restructured and edge logic changed independent of the pinout of the chip.
Other formats for the maps described above are possible. One additional format is to group all the map information into one Excel spreadsheet for ease of use. This spreadsheet is then broken up into the four maps described above before use.
A placement of a bump metal cell 2320A in a bump/bond pad area 2300A in accordance with an embodiment of the present invention is illustrated in
A placement of a bond pad metal 2310B in a bump/bond pad area 2300B in accordance with an embodiment of the present invention is depicted in
In one aspect of the present invention, standard cells called “edge logic” or “affinity logic” are grouped. Edge logic is a group of standard cells that have a timing relation with the I/O of the chip. Edge logic is often comprised of the first or last flip-flop connected directly to the I/O cell but can be as large as an entire FIFO for bringing data across clock domains. In an embodiment, edge logic is usually kept to fewer than 100 standard cells per I/O cell. The edge logic is placed in the edge logic area near each I/O cell of a slot for timing purposes. This addresses the time delay and variability in routes between the I/O cells and the core. Placing edge logic near the I/O cell instead of leaving it in the core shortens the distance between the I/O cell and the first/last flip flop, and how it is placed for related signals (e.g., a bus) can have a large impact on the skew for those signals.
In an embodiment, three options for placing edge logic in the edge logic area of a slot. The first option utilizes cell groups supported by timing driven placers. A group is formed covering the edge logic area for a slot and then the timing driven placer tries to place the edge logic for the I/O cell of the slot in the edge logic area. The placement is timing driven and varies from slot to slot but it is better than the variability of having the edge logic far away from the I/O cells in the core.
The second option to place edge logic in the edge logic area is to use a deterministic placer. A deterministic placer is not timing driven, it places standard cells in the edge logic area one at a time while packing them closely to their neighbors according to an arrangement. The order in which standard cells are placed is controlled by a sorting function assigned to the particular edge logic area. In this way, a series of edge logic areas can all have the same placement if the Verilog netlist has the same cells instantiated for each edge logic area. This is useful when trying to meet skew requirements between related I/O signals. Note that the placement is deterministic but the routing is still based on a heuristically driven router. The variations in routing of edge logic areas will be small because the placement is the same or approximately the same, however for extremely tight skew specifications (i.e. skew approaching 0) it will not be good enough.
To address a very tight skew specification, a macro is created in which the edge logic is placed and routed. The macro is then placed in the edge logic area in the same position with respect to respective I/O cells and will satisfy even the tightest skew constraints. In this way, both the placement and routing are tightly controlled. The extra effort to create a macro and associated timing library entry is weighed against the skew specification and is used only when justified. Moreover, multiple edge logic areas can be specified in a slot. This is useful for cases where the first/last flip-flop is to be placed close and consistently with respect to the I/O cell and other logic is to be placed nearby but is not so severely constrained.
A second placement of standard cells in an edge logic area 2600B in accordance with an embodiment of the present invention is shown in
The generation of a padring layout design is influenced by several preliminary considerations. One critical preliminary consideration is the number of signals and the signal to power/ground ratio for the chip design. If the signals can switch at a high rate, it is a good idea to have power and ground resources nearby to supply the current that the I/O cells will consume. How many power and ground resources are placed nearby can be described by the signal to power/ground ratio. For example, a high-speed output bus may have a power and ground pair for every two data signals for a ratio of 2:1. A lower speed interface may require a 4:1 or even 6:1 ratio. A low ratio indicates that the number of pins in the package will be greater but they will be interspersed with more power and ground pins so the package may actually be easier to route. Also, the number of pins to support the power requirements of the core needs to be considered.
In general, chip designs can be placed on a spectrum ranging from core-limited to pad-limited designs. A core-limited design occurs when the area required to place and route the core provides more than enough edge area for the padring. This type of chip design is often implemented with linear padrings since high pin density is not a concern. At the other end of the spectrum is a pad-limited design where the die size required to place the number of pins at a certain pitch creates a core area with more than enough room for the core. This is where the tradeoff between an expensive package with more substrate layers and smaller bump pitch versus a larger die comes into play. The present invention provides the ability to generate padring layout designs quickly, enabling estimation of core area and area utilization which is critical to the chip design process. This facilitates making package-related determinations early in the chip design process, allowing the package to be manufactured earlier than previously possible.
At Block 305 of
Continuing at Block 310, the patterns are then used to create slots in the zones using an instantiation process which is automated. A pattern is like a rubber stamp repeatedly used to stamp the slots in each zone. The orientation and spacing of the pattern is taken into account during this process. For example, many linear padrings have different spacing rules for bond pads near a corner versus bond pads in the middle of an edge. The placement algorithm associated with an instantiated slot is chosen and configured based on the required spacing. A power grid for the edge logic is then created depending on the configuration. For a BGA padring design where there may be many rows of I/O cells near the edge of the chip, the I/O cells have a tendency to cutoff the power grid for the edge logic from the core power grid. Here, straps can be automatically inserted over/between the I/O cells to provide connectivity between these grids.
Optionally at Block 315, a bump/bond pad name map can be used to associate names with the slots. These names can be used for LVS or for marking the bump/bond pads on plots for visual inspection. The I/O and edge logic maps can use these names also. The names can be written with a naming convention the user understands. Multiple bump/bond pad names can be associated with a given slot. This is useful in that sometimes a bump/bond pad is referenced spatially (e.g., B-17) and sometimes logically (e.g., ClkIn).
At Block 320, a preliminary customization of the padring layout design is performed. After the slots are laid out in the zones, a variety of modifications can be made. This preliminary customization can include, for example, editing slot positions to make room for exceptions to the patterns, deleting slots, introducing unique cell layouts into the padring layout design, and resizing areas of the slots. This can be performed using an editor. Moreover, this preliminary customization can be performed using a graphical user interface (GUI). Additionally, this preliminary customization can be performed programmatically using software such as perl.
Moreover, at Block 325, the bump/bond pad metals are placed in the bump/bond pad area of each slot. Often this metal is in the form of a cell that can be placed, but it can also be drawn directly if shapes and layers are provided in the slot.
Optionally, at Block 330, an I/O hints map can be used to assign I/O cells to slots. If the design is not mature and floorplanning/partitioning experimentation is needed, an I/O hints map can be provided at this point to roughly assign I/O cells to slots. Regular expressions (in perl or sh (shell script), for example) are used to group I/O cells and assign them to groups of slots. The signal to power/ground ratio is taken into account to intersperse signals with power/ground pairs. This I/O hints map can be used to quickly identify if a bus will wrap around a corner or if a given die area and pattern provides enough slots for the design. Once the groups of I/O cells are assigned to groups of slots, the assignment can be written out in the form of an I/O map.
Now referring to
At Block 340, a mid-flow customization of the padring layout design is performed. Here, unique layouts can be introduced into the padring layout design. For example, a JTAG scan loop can be stitched and have repeaters added or preroutes associated with the I/O cells can be laid out (e.g., voltage references, temperature or impedance compensation signals). This can be performed using software such as perl and a library.
Moreover, at Block 345, standard cells are placed in the edge logic area of each slot using the edge logic map. The edge logic map is read. Groups of standard cells are collected and ordered as prescribed by the attributes of the edge logic area for each slot. If edge logic belongs to a bus in general and not to a bit in particular, an edge logic area can be edited to cover the desired region associated with the bus. One of three placement algorithms is associated with each edge logic area. The first placement algorithm is a placement region where the edge logic is placed in the area by a timing driven placer. This will place edge logic near the I/O cell in a timing driven manner. The second placement algorithm for edge logic placement is to use a deterministic placer. This placer will guarantee consistent placement for each edge logic area. Since the deterministic placer controls only the placement, there can still be variability in the routing. For cases where the routing in the edge logic area is to be controlled also, the third placement algorithm is used. Here, a macro is constructed (such that the edge logic is placed and routed) and placed in each edge logic area to guarantee absolute consistency between related edge logic areas.
At Block 350, a final customization of the padring layout design is performed. This final customization can include, for example, laying down special escape pattern cover cells and adding prerouted wires near the edge logic areas to provide a bus with shielding for low skew balanced buses. This is useful for source-synchronous buses where consistent loading on the data and clock lines is important to achieve a low skew specification. Another final customization is to add repeaters on long nets.
At Block 355, the padring layout design is reviewed. Since automation is utilized, the padring layout design can be reviewed, changed, and regenerated multiple times until a satisfactory padring layout design is achieved. The padring layout design can be visually inspected, plots can be made, and the initial and final versions of maps (e.g., I/O map) can be compared. This short edit-run-evaluate cycle facilitates generating multiple iterations of the padring layout design in an efficient manner.
In summary, a given padring layout design is comprised of several zones which exhibit some regularity. This regularity can be exploited by finding the pattern in each zone and capturing it. The pattern is used to create areas where bump/bond pad, I/O, and edge logic cells are placed. Edge logic is pulled from the core (repartitioning) and placed near each I/O cell (placement). The areas can be edited to accommodate deviations from the pattern. Maps are used to assign names to these areas and to assign I/O and edge logic cells to specific areas. The content of the maps is designed to promote concurrency between engineers tasked with package design, netlist construction, floorplanning, and partitioning. The maps have a flexible format that can change as the pinout evolves from a prototype to final sign-off. The repeatable placement of edge logic near each I/O cell allows control over timing. Moreover, a flexible approach to customizing layout is provided. In this manner, small and large changes can be made easily and accurately. The short edit-run-evaluate loop allows changes to be made quickly, thus speeding design time. Finally, provisions are made for formal verification and LVS/DRC to check the resulting padring layout design.
Those skilled in the art will recognize that portions of the present invention may be incorporated as computer instructions stored as computer program code on a computer-readable medium such as a magnetic disk, CD-ROM, and other media common in the art or that may yet be developed.
Finally, aspects of the present invention can be implemented as an application, namely, a set of instructions (e.g., program code) which may, for example, be resident in the random access memory of a computer system. Until required by the computer system, the set of instructions may be stored in another computer memory, for example, in a hard drive, or in a removable memory such as an optical disk (for eventual use in a CD-ROM) or floppy disk (for eventual use in a floppy disk drive), or downloaded via the Internet or other computer network. In addition, although the various methods of the present invention described above can be conveniently implemented in a computer system selectively activated or reconfigured by software, one of ordinary skill in the art would also recognize that such methods of the present invention may be carried out in hardware, firmware, or in a more specialized apparatus constructed to perform the required methods of the present invention.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.
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|U.S. Classification||716/122, 716/139, 716/134|
|Cooperative Classification||G06F17/5072, G06F17/5077|
|European Classification||G06F17/50L2, G06F17/50L1|
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