|Publication number||US7120655 B2|
|Application number||US 10/351,591|
|Publication date||Oct 10, 2006|
|Filing date||Jan 27, 2003|
|Priority date||Jan 25, 2002|
|Also published as||US20030200241, WO2003065579A1|
|Publication number||10351591, 351591, US 7120655 B2, US 7120655B2, US-B2-7120655, US7120655 B2, US7120655B2|
|Inventors||Jui Liang, Gonghai Ren|
|Original Assignee||Integrated Device Technology, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (3), Non-Patent Citations (3), Classifications (5), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to U.S. Provisional Patent application No. 60/351,997, filed Jan. 25, 2002 and entitled “DIGITAL FILTER FOR ADC”.
1. Field of the Invention
This invention relates to signal processing.
2. Background Information
Signals carrying perceptual information, such as video and audio signals, are commonly transferred in analog form. Such analog transfer may occur even in cases where the perceptual information was created digitally or obtained from a digital source. For example, personal computers and other video generation devices (e.g. digital versatile disk (DVD) players) typically output analog video signals for display on cathode-ray-tube (CRT) monitors or other devices including CRTs such as television sets.
Unfortunately, the analog signal may become degraded during transfer. For example, environmental electromagnetic interference may produce noise in the signal. Other environmental factors such as temperature may affect timing or other characteristics of circuitry used to process the signal. High frequencies of the signal may also be attenuated by the signal path. Depending upon the particular cause, such degradations may occur in high-frequency and/or in low-frequency regions of the signal, and upon display of the signal they may be manifested by effects such as nonuniformities, random specks, or reductions in resolution or sharpness.
Noise problems may also become worse as the number of pixels in a display grows. For example, a large image display has more pixels than a small one. A phase-locked loop (PLL) may be used to control a clock of an analog-to-digital converter for digitizing the signal for display on a digital display (e.g. a liquid-crystal display). As the number of pixels increases, the PLL must run at a higher speed, which may give rise to increased jitter. Such increased jitter may be visible in the displayed signal as noise.
Noise may also cause the appearance of undesirable artifacts in low-frequency regions of a video signal. Such effects may be visible as variation, as the eye is more sensitive to noise in these regions. Noise of this type may be due to amplitude and/or phase variations in analog signal.
Moreover, the quality of an RGB-out signal may vary greatly. For example, it may be desired to display a signal from a video source whose output signal deviates from the VESA standard.
Automatic gain control may be used to control some noise problems, but at some point such techniques may also adversely affect signal contrast and brightness.
A digital filter according to one embodiment of the invention includes a local frequency state detector (LFSD). The LFSD is configured to indicate a predetermined local frequency state in a sequence of data values. The filter also includes a regional frequency state detector (RFSD), which is configured to detect a predetermined condition in a region of the sequence, based on a plurality of local frequency state indications. The RFSD is also configured to output a select signal based on the detection. A compensator is configured to output a compensated value of a value of the sequence, and a selector is configured to output one of the value and the compensated value, based on the select signal.
Buffer 110 may be implemented as a FIFO (first-in-first-out) buffer.
For an application in which values shifted into buffer 110 have more than one bit, such a buffer may be constructed as a parallel arrangement of 10-bit shift registers. Alternatively, buffer 110 may be implemented in software or firmware as a sequence of instructions.
In an exemplary application, data signal S100 is received as a string of bytes outputted by an analog-to-digital converter (ADC). In a particular such application, buffer 110 stores parallel sets of eight consecutive samples, each sample being of size one byte (i.e. eight bits). For example, buffer 110 may store triples of signal values that represent pixels in an RGB color space. Alternatively, buffer 110 may be used to store n-tuples of values representing pixels in another color space. In another implementation, buffer 110 may receive and store signal values representing two or more audio channels.
For an application in which buffer 110 stores values in parallel, it may be desirable to use different numbers of bits to store each of the various values. For example, more bits may be used to store a value representing luminance information than are used to store a value representing chrominance information (e.g. for values representing pixels in a YUV or YCrCb color space). It may also be desirable for signal S100 to contain (and for filter 100 to process) related strings of values at different resolutions (e.g. more luminance values than chrominance values for the same area of picture space).
Local frequency state detector 200 receives two or more values of the sequence and indicates whether a predetermined condition exists with respect to those values.
ROC calculator 310 calculates a rate of change among values of the sequence.
ROC evaluator 330 evaluates the ROCs calculated by ROC calculator 310 according to one or more predetermined criteria.
Other implementations of ROC evaluator 330 may compare magnitudes using other circuit configurations and/or sequences of instructions. The implementation selected for a particular application may depend on factors such as the numeric format of the rate of change outputted by ROC calculator 310 (e.g. sign/magnitude, one's complement, two's complement, etc.). For example, if the ROC is presented in sign/magnitude form, it may be desirable to implement ROC evaluator 330 as a single comparison between the magnitude portion of the ROC and the magnitude portion of a predetermined threshold.
It may be desirable in some applications to use different upper and lower ROC value thresholds instead of a single ROC magnitude threshold. Likewise, it may be desirable for such threshold or thresholds to be programmable or otherwise capable of being changed (possibly even during operation). For example, in an application of an implementation of filter 100 to video signal processing, it may be desirable to change a threshold value depending on the particular source of the video signal being processed.
Condition detector 420 may be implemented in several different forms. For example, condition detector 420 may be implemented to detect regions in which fewer than eight (e.g. four or six) consecutive indications indicate a particular frequency state, or only regions in which more than eight consecutive indications indicate the particular frequency state. Condition detector 420 may also be implemented to detect regions in which a particular proportion of indications (e.g. six out of eight consecutive indications, or eight out of ten) indicate the particular frequency state. Condition detector 420 may also be implemented such that the detected characteristics may be changed (e.g. from a region of six consecutive indications to a region of eight consecutive indications) during operation of filter 100 (e.g. in real-time).
A form of condition detector 420 may be selected based upon an intended application. One operation to which an implementation of filter 100 may be applied is compensation for attenuation of high frequencies in a digital video signal (e.g. as may arise during transmission of the signal in analog form). In at least some display situations (e.g. on a desktop digital display such as a liquid-crystal panel), such attenuation may not be visible if the extent of the high-frequency region is less than about six or eight pixels. On the other hand, such attenuation may become quite visible if the extent of the high-frequency region is more than eight pixels. Therefore, it may be desirable for such an implementation of filter 100 to include an implementation of condition detector 420 that is configured to detect regions in which a local high-frequency state has been indicated over at least six or eight evaluations.
Detection storage 432 records the results outputted by condition detector 422.
As shown in
It may be desirable for the result outputted by compensator 130 to be restricted within predetermined minimum and maximum bounds. For 8-bit data values, for example, it may be desirable to prevent compensator 130 from decreasing a data value below 0 or increasing a data value above 255. In such a case, adder 146 of compensator 132 may be implemented to be a saturating adder.
As shown in
It may be desirable for buffer 110 to contain more storage states than detection storage 430. To illustrate one reason to implement such a condition,
The left panel of
It may be desirable for selector 150 to output a compensated value only if one or more additional conditions are met.
In order to illustrate an example of an application of such additional conditions,
Operations of selection and compensation as described with respect to implementations of selector 150 and compensator 130 may be performed using several different structures. For example,
It may be desirable for an implementation of filter 100 to perform detection of more than one type of regional frequency state. For example, it may be desired to perform processing operations on high-frequency regions of a signal and also on low-frequency regions of a signal.
Lowpass filter 500 may be implemented as a finite impulse response filter. For example, lowpass filter 500 may be implemented to output a value that is the dot product of a coefficient vector and a string of values from buffer 112. Examples of suitable four-value coefficient vectors include (0.25, 0.25, 0.25, 0.25) and (⅛, ⅜, ⅜, ⅛). An embodiment of filter 100 that includes a lowpass filter may also include a storage unit to store one or more coefficient vectors, which may be selected and/or reprogrammed.
The foregoing presentation of the described embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments are possible, and the generic principles presented herein may be applied to other embodiments as well.
Filter 100 may be implemented on a single chip or in a chipset. Alternatively, different portions of filter 100 may be implemented in different modules and/or may execute on different processors. Operational blocks of filter 100 may be implemented as logic gates and/or as sets of instructions executed by one or more processors. Software or firmware implementations of such blocks may include one or more of a set of SIMD (single-instruction, multiple-data) instructions (e.g. the MMX, SSE, or SSE2 extension sets of Intel Corp., Santa Clara, Calif.; the 3DNow! Extension set of AMD Corp., Sunnyvale, Calif.; the AltiVec extension set of Motorola, Schaumberg, Ill.).
Filter 100 may also include communications capabilities, such as a readback register, through which values of parameters and/or data may be downloaded for purposes of testing or evaluation.
For example, the invention may be implemented in part or in whole as a hard-wired circuit, as a circuit configuration fabricated into an application-specific integrated circuit, or as a firmware program loaded into non-volatile storage or a software program loaded from or into a data storage medium as machine-readable code, such code being instructions executable by an array of logic elements such as a microprocessor or other digital signal processing unit. Thus, the present invention is not intended to be limited to the embodiments shown above but rather is to be accorded the widest scope consistent with the principles and novel features disclosed in any fashion herein.
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|2||PCT Search Report, mailed Jul. 15, 2003 in corresponding PCT/US 03/02200.|
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|International Classification||H03H17/02, G06F17/10|
|Jun 17, 2003||AS||Assignment|
Owner name: MEDIA REALITY TECHNOLOGIES, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIANG, JUI;REN, GONGHAI;REEL/FRAME:014429/0326;SIGNING DATES FROM 20030606 TO 20030609
|Sep 10, 2004||AS||Assignment|
Owner name: INTEGRATED CIRCUIT SYSTEMS PTE LTD., SINGAPORE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MEDIA REALITY TECHNOLOGIES, INC.;REEL/FRAME:015120/0037
Effective date: 20040804
|Oct 12, 2004||AS||Assignment|
Owner name: ICS TECHNOLOGIES, INC., DELAWARE
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTEGRATED CIRCUIT SYSTEMS PTE LTD.;REEL/FRAME:015237/0984
Effective date: 20041008
|Sep 20, 2006||AS||Assignment|
Owner name: INTEGRATED DEVICE TECHNOLOGY, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ICS TECHNOLOGIES, INC.;REEL/FRAME:018279/0284
Effective date: 20060920
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