|Publication number||US7125495 B2|
|Application number||US 11/019,037|
|Publication date||Oct 24, 2006|
|Filing date||Dec 20, 2004|
|Priority date||Dec 20, 2004|
|Also published as||EP1672717A2, EP1672717A3, EP1672717B1, US20060131266|
|Publication number||019037, 11019037, US 7125495 B2, US 7125495B2, US-B2-7125495, US7125495 B2, US7125495B2|
|Inventors||Robert A. Street, William S. Wong, Alberto Salleo, Michael L. Chabinyc|
|Original Assignee||Palo Alto Research Center, Inc.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Non-Patent Citations (1), Referenced by (4), Classifications (10), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates to integrated circuit (IC) fabrication, and more particularly to methods for generating patterned film layers for ICs that can be used in the production of large area electronic devices.
Large area electronic devices, such as flat panel displays, sensor arrays, and space antennas, typically include large area sensor or light-emitting electronic cells that are addressed and/or controlled by thin film transistors (TFTs) and other electrical and electronic devices (e.g., passives and photodiodes). Such large area electronic devices are expensive to make by conventional photolithography techniques due to the relatively large size of the electronic cell arrays (e.g., 1000 cm2 or larger), and the relatively large spacing between adjacent TFTs. Conventional photolithography equipment for fabricating typical (i.e., ˜300 cm2 or smaller) IC devices is typically constructed to receive and process a semiconductor wafer having a predetermined size, and such wafers are typically much smaller than the substrate of a large area electronic device. Therefore, specialized equipment for photolithography on large area substrates must be developed typically at great expense. Moreover, conventional photolithography equipment includes optical and other processing tools that are constructed to facilitate the formation of substantially smaller feature sizes than those required in many elements of large area electronic devices, thereby making the production of large area electronic devices using such photolithography equipment highly inefficient.
Jet-printing is an emerging technology that attempts to reduce the costs associated with IC production by replacing expensive photolithographic processing with simple printing operations in which layer structures are formed using materials ejected from a print head. By printing an IC pattern directly on a device substrate rather than using the delicate and time-consuming lithography processes used in conventional IC manufacturing, an IC printing system can significantly reduce IC production costs. The printed IC pattern can either comprise actual IC features (i.e., elements that will be incorporated into the final IC, such as the gates and source and drain regions of TFTs, signal lines, the semiconductor, opto-electronic components, etc.), or it can be a mask printed onto the substrate that is used for subsequent semiconductor processing steps (e.g., etch, implant, etc.). Such masks are referred to herein as “jet-printed etch masks”.
Typically, jet-printing involves depositing a print solution (generally a material in a solvent or a liquid) by raster bitmap along a single axis (the “print travel axis”) across a solid substrate. Print heads, and in particular, the arrangements of the ejectors incorporated in those print heads, are optimized for printing along this print travel axis. The solid substrate is mounted under the print heads, and either the substrate is moved relative to the fixed print head, or the print head is moved over the fixed substrate. In either case, printing of an IC pattern takes place in a raster fashion, with the print head making “printing passes” across the substrate as the ejector(s) in the print head dispense individual droplets of print solution onto the substrate. At the end of each printing pass, the print head makes a perpendicular shift relative to the print travel axis before beginning a new printing pass. The print head continues making printing passes across the substrate in this manner until the IC pattern has been fully printed. Once dispensed from the ejector(s) of the print head, print solution droplets attach themselves to the substrate through a wetting action and proceed to either dry by evaporation of a carrier solvent or solidify in place if a pure material is deposited.
Because jet-printing of etch masks where the pattern is stored on a computer, which is also referred to as “digital lithography”, is not limited to a particular wafer size, it provides a promising technique for fabricating large area arrays of thin film transistors which are utilized, for example to drive large area displays or sensor arrays. However, at present, jet-printing is limited to producing relatively low resolution features (e.g., 30–50 microns), and therefore cannot meet all of the requirements for large area arrays. That is, much of the large area electronic device can be printed at low resolution (e.g., features) because wide metal lines are needed for interconnects. However, as discussed below, the transistors perform much better if they have very small features (e.g., approximately one micron), and are thus better suited to a high resolution printing process.
A problem with the large feature sizes produced by jet-printing techniques is that it places limitations on the speed and parasitic capacitance of TFTs forming the large area electronic device, and in many cases the high capacitance is the more serious problem. A generic design of the metal contacts to a TFT 1300 is shown in
The operating speed of TFT 1300 is generally limited by RC time-constants, and ultimately by the RC time-constant of the TFT itself. A low resistance (high current) TFT requires a large W/L, but when fabricated with large feature sizes (e.g., a large D), this produces a high parasitic capacitance, which increases power consumption and reduces operating speed. In a simple approximation, the capacitance is proportional to the square of the feature size. As such, producing a large area electronic device using a relatively low resolution processing tool, such as jet-printing, results in relatively slow and inefficient TFTs. In particular, the jet-printing approach typically gives large feature sizes, and presently the size is 20–40 micron for conventional print-heads. The feature size can probably be reduced significantly, but it is doubtful whether it is possible to reach 1–2 micron, thus limiting the ability of jet-printing to produce low capacitance, high speed TFTs. However, jet-printing provides very good registration between different layers, because the accuracy of drop placement is limited only by the random variation in the drop ejection direction, and this can be reduced below 5 microns.
Soft lithography (a.k.a., stamping or microcontact printing) and imprint lithography are relatively high resolution printing techniques that facilitate the production of circuit structures having smaller features sizes (e.g., dimensions well below one micron have been demonstrated), and thus the production of much higher performance TFTs than those produced using jet-printing techniques. Soft lithography involves forming a printing press-like structure from a soft material (e.g., polydimethylsiloxane), which is referred to as a stamp, that prints a resist pattern directly onto a material (e.g., metal) layer deposited over a device substrate. The stamp is positioned (registered) over the desired substrate region using an appropriate X-Y positioning table, and then pressed against the device substrate with a predetermined force, thereby transferring a patterned resist layer onto the substrate. In another variation, a resist layer can be coated onto the substrate and embossed using the stamp in a process referred to as imprint lithography.
A problem with soft lithography is that the registration accuracy of different layers is relatively lower than that provided by jet-printing, and so the benefit of the small feature sizes is not realized in the production of large area electronic devices. Further, the production of large stamps (i.e., suitable for printing an entire critical layer of a large area electronic device) is difficult because of the potential for mechanical distortions in the features of the stamp.
What is needed is a method for producing ICs, and in particular, large area electronic devices, that includes both the cost efficiency of low resolution processing, but also provides the performance advantages associated with high resolution features.
The present invention is directed to a method for producing patterned film layers for electronic devices in which two different processing techniques (tools) are utilized to respectively form high resolution features (structures) and low resolution features in a critical layer (e.g., source/drain metal layer) of the electronic device. In particular, only those features of the critical layer that require high resolution (e.g., on the order of one to five microns), such as the spacing of the source/drain electrodes of thin film transistor (TFT) structures, are produced using suitable high resolution processing techniques, such as soft lithography or imprint lithography. In contrast, features of the critical layer that can be produced using low resolution (e.g., on the order of ten to fifty microns), such as interconnect line structures, are produced using suitable low resolution fabrication processing techniques, such as jet-printing, gravure printing, flexography or screen printing. The low resolution features are formed such that they connect to the high resolution features, thereby providing an electronic device that combines the superior performance of structures produced by high resolution processing techniques with interconnect structures produced using economical low resolution processing techniques.
In accordance with a specific embodiment of the present invention, high resolution features are generated using a soft lithography (stamping) processing technique, and low resolution features are generated using jet-printing, which may also be utilized to “stitch”, if necessary, the high and low resolution features that may be separated by misalignment between the stamping and jet-printing tools. High resolution features (e.g., source/drain structures) are formed on a device substrate by forming a metal layer, patterning the metal layer by forming an etch resist pattern on the metal layer using a soft lithography stamp, and removing (etching) exposed portions of the metal layer to define the high resolution features. Low resolution features are then formed in a way that preserves the high resolution features, and such that the high resolution features are operably interconnected by way of the low resolution features. In one specific embodiment, a print solution containing a conductive material (e.g., metallic nanoparticles) is jet-printed directly onto the device substrate to form the low resolution features. In another specific embodiment, a jet-printed etch mask is used to form the low resolution features, for example, by patterning portions of the metal layer that are retained during formation of the high resolution features. Disconnections between the low resolution features and high resolution features may then be “repaired” (stitched) by jet-printing corrective bridge structures across gaps separating the unintentionally disconnected features. Jet-printing is thus particularly suited for producing the low resolution features because, in addition to forming the low resolution features in a highly efficient manner, the jet-printing equipment is capable of performing the stitching process to significantly increase production yields.
In accordance with another embodiment of the present invention, alignment marks are produced during the formation of the high resolution features, and these alignment marks are utilized during one or more of the low resolution feature formation and the subsequent stitching process. In one embodiment, the alignment marks generated during the soft lithography process are utilized by a process control system to control the subsequent jet printing process such that the low resolution features are adapted to misalignments of the stamped high resolution features. The location of the stamped alignment marks and the position of the print head during jet-printing may be used to determine the need for and location of a subsequent stitching operation. In another embodiment, the low resolution features are formed by jet-printed masks that include an additional set of alignment marks. The stamped and jet-printed alignment marks may then be utilized to automatically measure misalignment between the soft lithography and jet-printing processes, and to control (if necessary) a stitching process to bridge gaps between the high and low resolution features (i.e., to complete the intended connection between these features).
In accordance with another embodiment of the present invention, the present invention is utilized to produce high performance TFT arrays for large area electronic devices. Gate structures are formed by depositing and patterning a gate metal layer using a jet-printed etch mask. A dielectric layer is then formed, and a source/drain metal layer is deposited over the dielectric layer. Source/drain electrodes are then formed on the dielectric layer by stamping and etching the source/drain metal layer. Interconnect structures are then formed using a second jet-printed etch mask, which protects the source/drain electrodes during further etching of the source/drain metal layer to form the interconnect structures. Finally, a semiconductor region is formed over the source/drain electrodes, and stitching is performed (if needed) to close any open circuits. Thus, high performance TFTs for large area electronic devices are produced at a minimal cost due to the use of jet-printing to generate both the gate and interconnect structures, and also to perform the stitching process (when needed). Further, by carefully designing the stamp used to form the source/drain electrodes and the jet-printed etch mask used to form the interconnect structures, the process can be made highly tolerant to misalignment of the stamp and masks, thereby increasing production yields.
In accordance with another embodiment of the present invention, to further improve the tolerance to mis-registration of the stamp to the first metal layer, spaced-apart, substantially identical redundant features are formed during the high resolution processing phase, and one or more of these redundant features is removed during the low resolution processing phase (i.e., a retained one of the redundant features forms the desired high resolution feature). In particular, one or more optimally placed redundant features is identified prior to the low resolution processing phase, and these optimally placed redundant features are protected from removal during the low resolution etching process (i.e., non-optimal redundant features are exposed by resist pattern during the etching process, and are therefore removed). For example, the mask could contain several copies of a TFT source/drain structure at different positions. After the stamping process is completed, the alignment mark(s) formed with the redundant source/drain structures and the alignment mark(s) formed with the gate structure are inspected, and the optimum device location can be selected automatically. The second masking step is then controlled (automatically) to protect the selected source/drain structures during the low resolution etching process (i.e., the non-selected source/drain structures are exposed by the jet-printed etch mask, and therefore removed during the etch). Etch patterns are optimized for the known type and magnitude of the misalignment of a particular printing process.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings, where:
The present invention is described below with reference to certain exemplary embodiments, and primarily with reference to embodiments involving the production of thin film transistors (TFTs) for large area electronic devices. Although described with particular reference to TFTs for large area electronic devices, the present invention may also be utilized to produce other electrical and electronic circuit components utilized on large area electronic devices. In addition, the method described herein is not necessarily limited to the production of large area electronic devices, and may be utilized as a cost effective production method for certain small area electronic devices. Therefore, unless otherwise specified, the appended claims are not limited to the specific embodiments described below.
In a first phase of the production process, high resolution features (e.g., structures having features sizes on the order of one to five microns) are formed on a device substrate using a high resolution processing tool (e.g., soft lithography or imprint lithography; block 110).
In a second phase of the production process, low resolution features (e.g., structures having features sizes on the order of ten to fifty microns) are formed on the device substrate using a low resolution processing tool (e.g., jet-printing or screen printing) such that the low resolution features contact corresponding high resolution features (block 120).
Referring to the upper portion of
Referring again to
In many situations, the stamp pattern utilized to form high resolution features will be much smaller than the device substrate, and multiple stamping operations will be performed to pattern the entire surface of the substrate. These multiple stamping operations may involve the use of a single stamp (e.g., to reproduce critical structures, such as the source and drain structures of a TFT), or may involve the use of several stamps configured to pattern different high resolution features. In contrast to the relatively small stamp, jet-printed masks are developed in the printing software. The only physical constraints on the size of the mask is the size of the printer system and this can, in principle, be made arbitrarily large enabling one to pattern an entire device substrate. In either case, it is important to have a reliable mechanism for coordinating the positioning of the high and low resolution features to avoid open circuit situations.
In accordance with another aspect of the present invention, the control system utilized to position mask 450B determines an optimal position for resist pattern 465B based on the location of alignment marks 218B such that resist pattern 465B covers both source/drain structures 210B and portions of metal layer 410B needed to provide low resolution interconnect structures. As in the embodiments described above, remaining exposed portions 417B of metal layer 410B are removed (etched).
In addition to providing a reliable mechanism for positioning the low resolution features relative to the previously formed high resolution features, the alignment marks generated during the formation of high resolution features may also be utilized to automatically control (position) a print head during a stitching process used to repair unintended gaps (as discussed above), or a scheduled stitching process used to connect separately formed sections of the desired TFT array.
For purposes of this example, the jet-printed mask (not shown) utilized to form the low resolution interconnect structures is assumed to be smaller than the substrate on which pixel array 600 is formed, and thus must be repositioned and utilized in several steps to cover the entire array. For example, the stamp and mask operations used to form TFTs 610-11 and 610-12 is performed at a different time than the stamp and mask operations used to form TFTs 610-21 and 610-22 (which are connected to column conductor segment 220C20 and row conductor segments 200C21 and 220C22, respectively). Accordingly misalignment between the sequentially performed low resolution processes may result in gaps G between column conductor segments 220C10 and 220C20. In this embodiment, the jet-printed mask has been positioned relative to the associated stamped source/drain structures using alignment marks (not shown) in the manner described above, and a resulting misalignment has created gaps G between adjacent column conductor segments. These gaps are detected by the process control system based on the recorded location of the alignment marks printed with the high resolution source/drain features, and based on the known position of the jet-printed etch mask during formation of the low resolution interconnect structures, the jet-printing system is controlled to form conductive bridge structures 620 by ejecting a conductive print solution 255C into gaps G, thus connecting associated column conductor segments (e.g., column segments 220C1 and 220C2).
In yet another embodiment, gaps between adjacent sections of the TFT array may be purposefully generated, with the stitching process included as part of the manufacturing process to close the gaps after the low resolution etching step. For example, sections of pixels may be formed using a stamp that contains n×n pixels. This stamp is rastered over the substrate to form a p×m array of stamped pixels. The stamped pixels are then processed to form interconnect lines, and or each stamped pixel array is then interconnected using a printed “stitch” interconnect. This approach will reduce the amount of “stitch” points for interconnecting pixels and also allow smaller pixel dimensions within the array.
Referring to the upper portion of
High resolution source/drain electrodes and low resolution interconnect structures are then formed in the manner described above. First, the source/drain metal layer is stamped and processed to form the high resolution source/drain electrodes (block 110C). Note that the first alignment marks are utilized to position the stamp such that the source/drain electrodes are formed over associated gate structures. Next, retained portions of the source/drain metal layer are patterned using a jet-printed etch mask in the manner described above to form associated interconnect structures (block 120C). The low resolution process may use one or both sets of alignment marks from the gate metal and the stamped source-drain metal to correct for any misalignment of the stamping process. The positions of the two sets of alignment marks is measured, for example by a camera, and the exact position of the two layers can be calculated from which the misalignment is reduced (a software routine may be used to perform this function automatically). The printed etch mask will cover the fine features of the stamp, and provide a low resolution pattern connecting the TFT to the rest of the circuit. Semiconductor structures are then formed over each source/drain electrode pair to facilitate transistor operation (block 740), and then misalignment gaps are stitched according to the method described above (block 750).
To further improve the tolerance to misalignment of the stamp to the first metal layer, it is possible to stamp redundant features in the high resolution process and use the second masking step to choose the features that are best aligned and remove the others. For example, the mask could contain several copies of the source-drain contact structure at different positions, as illustrated in FIGS. 10(A) and 10(B). Note that
The redundancy of the high resolution stamp also allows fabrication of a generic masking layer for the via holes for the pixel pads. The via connects to a metal contact layer above the plane of the TFT. The idea is to allow for a via hole on either side of the gate line. Regardless of which transistor contact is chosen to be the pixel contact, one of the two via holes will contact the transistor. This via layer is simply aligned to the masking layer used to choose the transistor, and is independent of which transistor and contact were chosen from the high-resolution pattern.
Although the present invention has been described with respect to certain specific embodiments, it will be clear to those skilled in the art that the inventive features of the present invention are applicable to other embodiments as well, all of which are intended to fall within the scope of the present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5900160||Jul 9, 1996||May 4, 1999||President And Fellows Of Harvard College||Methods of etching articles via microcontact printing|
|US6334960||Mar 11, 1999||Jan 1, 2002||Board Of Regents, The University Of Texas System||Step and flash imprint lithography|
|US6413790 *||Jul 21, 2000||Jul 2, 2002||E Ink Corporation||Preferred methods for producing electrical circuit elements used to control an electronic display|
|US6655286||Sep 29, 2001||Dec 2, 2003||Lucent Technologies Inc.||Method for preventing distortions in a flexibly transferred feature pattern|
|US20040219246||Apr 29, 2003||Nov 4, 2004||Jeans Albert H.||Apparatus for embossing a flexible substrate with a pattern carried by an optically transparent compliant media|
|1||Michael D. Austin and Stephen Y. Chou "Fabrication of 70nm channel length polymer organic thin-film transistors using nanoimprint lithography", Applied Physics Letters, vol. 81, No. 23, Dec. 2, 2002.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7811638||Dec 22, 2005||Oct 12, 2010||Palo Alto Research Center Incorporated||Multi-printed etch mask process to pattern features|
|US8206895||Jul 24, 2008||Jun 26, 2012||Kabushiki Kaisha Toshiba||Method for forming pattern and method for manufacturing semiconductor device|
|US20070145002 *||Dec 22, 2005||Jun 28, 2007||Palo Alto Research Center Incorporated||Multi-printed etch mask process to pattern features|
|US20100021848 *||Jul 24, 2008||Jan 28, 2010||Ikuo Yoneda||Method for forming pattern and method for manufacturing semiconductor device|
|U.S. Classification||216/27, 430/311, 438/745|
|Cooperative Classification||H01L51/0004, H01L51/0011, H01L51/0021|
|European Classification||H01L51/00A2D6, H01L51/00A2B2, H01L51/00A8|
|Dec 20, 2004||AS||Assignment|
Owner name: PALO ALTO RESEARCH CENTER INCORPORATED, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:STREET, ROBERT A.;WONG, WILLIAM S.;SALLEO, ALBERTO;AND OTHERS;REEL/FRAME:016112/0440;SIGNING DATES FROM 20041217 TO 20041220
|Feb 18, 2010||FPAY||Fee payment|
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|Mar 21, 2014||FPAY||Fee payment|
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