|Publication number||US7126387 B2|
|Application number||US 10/794,625|
|Publication date||Oct 24, 2006|
|Filing date||Mar 8, 2004|
|Priority date||Apr 7, 2003|
|Also published as||US20040196075|
|Publication number||10794625, 794625, US 7126387 B2, US 7126387B2, US-B2-7126387, US7126387 B2, US7126387B2|
|Original Assignee||Rajendran Nair|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (5), Referenced by (20), Classifications (8), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
Embodiments of the invention relate to electronic circuitry commonly employed to provide regulated voltages to other electronic, electromechanical or electro-optic devices and systems. Such circuitry falls under the broad category of power management electronics.
PN (p-type abutting n-type) semiconductor junctions are ubiquitous in the industry and play a principal role in electronic devices such as Diodes, Silicon-Controlled Rectifiers, Thyristors, Bipolar Junction Transistors (BJTs), Junction Field Effect Transistors (JFETs), and in optoelectronic devices such as Light-Emitting Diodes (LEDs) and Vertical Cavity Surface-Emitting Lasers (VCSELs). Electronic circuits that activate (‘drive’) the PN junctions are also common in the art and vary from resistor-divider circuits employed for BJT-based circuits to current-pulse circuits employed where only a transient activation of the junction is required. PN junctions display a ‘rectifying’ property, conducting electric current in one direction and blocking it in the opposite direction. In transistors, the PN junction labeled the ‘base’ in BJTs or the ‘gate’ in JFETs functions as the control location that regulates current flow through the device.
Activating the PN junction that functions as the control input for BJT's or JFETs often requires the flow of static current through the junction. For example, a BJT device employed to regulate the current flow through an electronic circuit will allow a current to pass through it that is a multiple of the device current gain, β and the current flowing into the base PN junction. Another example is that of an ‘enhancement-mode’, normally-off JFET device wherein a conduction channel is formed by the injection of a current into it's gate PN junction.
Other types of transistor devices exist wherein a static current flow into the control-input is not required for the operation of the devices. Examples of such devices are MOSFET and ‘depletion-mode’ JFET devices. Static current flow into the control input of a transistor device is, in some applications, an undesirable characteristic of the circuit and an unwanted expenditure of energy. Nevertheless, the principal characteristics of devices requiring control-input current, such as current-gain, low output resistance, speed of operation, simplicity and low-cost nature of manufacture etc., may prove to be attractive enough for their use despite the burden of the control-input current. It is desired in such cases that the energy expended due to the control-input current (in PN junction base or gate drive) be minimized in order to improve overall operational efficiencies and to minimize cost. Alternately, it may be desired that a facility to vary the control-input current is made available, that incurs minimal additional energy expenditure, and that does not depend upon external components.
In certain applications, minimizing the energy loss due to the gate drive current is critical to the quality of the solution. An example is the use of enhancement-mode or depletion-mode JFET switches in DC-to-DC conversion applications, a technology currently in the commercialization phase . Of specific relevance is a class of converters called ‘buck’ DC-to-DC converters. These converters transform an input voltage into a lower output voltage through the use of switches that convey the input voltage, pulse-width modulated, into an energy-storing output filter. Common examples of the use of such converters are microprocessor power supplies. Maintaining high efficiencies in power supply voltage conversion is critical in such applications due to the costs associated with managing thermal dissipation within the system. The use of enhancement-mode JFET switches in buck conversion results in additional energy expense (as compared with MOSFET switches) due to the static drive current requirement. Certain JFET devices  may require as much as 40 mA of gate drive to cause the ON resistance of the device to reduce to 4.5 milliohms with the device conducting 10 A of current. With the control input driver circuit operating from a 5V supply, the static power consumption is 200 milliwatts, while the power consumption in the device channel due to current flow is 450 milliwatts. Assuming a 1V output from the buck converter, and a 20% 5V input duty cycle (or an 80% duty cycle for a switch device on the ground-side of the converter) in a 5V to 1V conversion, this drive power into the switch device alone is seen to contribute to a reduction in efficiency of 1.6%. In systems requiring extremely high conversion efficiency, such as battery operated computing devices, or thermally constrained systems, this loss in efficiency makes the JFET-based solution unattractive.
The invention specifies an innovative circuit architecture that successfully addresses the problems discussed above.
The invention is a novel drive circuit and system architecture that minimizes the additional energy expense in driving power switch devices that require control-input currents and facilitates variation in the drive current for improved switch and system performance.
In one embodiment of the invention, a current source output replaces the prior art voltage drive circuits and associated external current-limiting resistor. The current-source drive circuit provides both a high impedance as well as variability. The high impedance of the current-source drive circuit enables a reduction in the value of the resistance-bypass capacitor employed in the prior art. The variability in the output current provided by the current-source circuit allows the drive circuits to optimize the control current flowing into the switch device as the characteristics of the switch device change with operating temperature. The drive circuit is capable of providing as output either a desired current, at a high output impedance, or a desired voltage, at a low output impedance, employing a shared amplifier and output transistor. The drive circuit also derives current from the much lower output voltage of the buck conversion system that the invention is used in. This minimizes the static power dissipated in driving the switch, and also minimizes the energy expenditure incurred in increasing the output current to modulate the power switch resistance that increases with increasing temperature.
In another embodiment of the invention, multiple current sources are employed in parallel to drive the power switch control input, eliminating the need for the external capacitor as well. As in the first embodiment, a current source maintains the power switch in it's ‘ON’ condition by means of a variable current drive, a current source to a voltage reference of the opposite polarity is employed to maintain the device in it's ‘OFF’ state and transient current sources are employed to rapidly transition the power switch device between it's binary states of operation. In this embodiment, the output voltage of the buck conversion system, by definition lower than the input voltage to the system, is employed for the turn-on action of the switch, and an external reference or an internally generated voltage of the opposite polarity is employed to transition to a turn-off mode. Available low-impedance voltage references such as the input power supply to the system and the system ground are employed for the transient drive actions that facilitate rapid transition between the modes.
For purposes of illustration, unless explicitly specified, the description herein will assume that N-type JFET power switches are used, where the channel is formed by electron-donor or n-type semiconductor material and the gate junction is formed by the deposition of p-type material.
Where Cj is an approximation for the capacitance of the PN junction in reverse bias, and the incremental voltages correspond, as differentiated by the presence of a junction-label, to the voltage variation across the junction and the voltage change at the drive node. Additionally, this negative voltage developed at the control input of the switch, that maintains the switch in it's ‘OFF’ state, decays into the drive node that is now at the low output potential of the driver circuits through resistor R. It will be clear to one skilled in the art that due to the presence of resistor R, that decays the turn-off potential developed as described herein, it is necessary in the prior art architecture to maximize the value of capacitor C, thereby maximizing the negative voltage developed across the PN junction control input in order to provide good margins for maintaining the turn-off condition of the power switch. Yet, in order to minimize switching losses proportional to the square of the voltage transition across a capacitor, associated with the input capacitance of device LS, as well as to facilitate external component integration, it is desirable that the value of capacitance C be substantially reduced, which, as may be shown by equation 1 above, will reduce the voltage swing at the gate junction input.
The invention drive architecture, an embodiment of which is illustrated in
Additionally, the invention embodiment shown in
While providing a constant current as the output signal of the ‘static drive’ path eliminates uncertainties due to input power supply and external resistor value variation, addressing the variation in JFET power switch device characteristics with temperature is also important. JFET devices operate by means of the modulation of a conducting channel by expanding or contracting depletion fields induced by the potential difference across the control gate junction. It is well known in the literature that the forward voltage across a PN junction diode diminishes by a few mV for every degree centigrade rise in temperature. In JFET power switches, this effect combined with the reduced mobility of charges in the channel results in a higher rate of increase of channel resistance with temperature, since a reducing forward potential expands the depletion field, constricting the conducting channel. The invention addresses this by providing a single circuit architecture that is capable of driving either a desired constant current or a desired constant voltage at its output. Driving an appropriate voltage value instead of a current value provides the benefit of maintaining a constant electric field across the PN junction control gate of the power switch device LS of the invention, thereby ensuring a measure of temperature independence in the value of the resistance of the power switch device channel.
An alternate embodiment of the drive circuits is shown in
The invention also provides a unique ability to adapt the drive action into switch device LS to operating conditions. The driver circuits of the invention obtain information about the operating condition of the switch device through the voltages sensed at all the terminals of the switch device and through the current flowing into it's control gate. With reference to
The embodiment illustrated in
Through a pairing of a specific embodiment of the invention and a low-side (or low-side and high-side) JFET power transistors, and because of the unique ability of the invention to adapt to conditions of increased temperature in the switches, a system employing the invention can sense the average current flow through the switches as well as the voltages at all nodes of the switches. For example, in matching an embodiment to a JFET switch, information about the effective ‘on-resistance’ of the switch at a given input gate current and gate-to-source voltage may be stored in the embodiment in non-volatile memory. The variation in this resistance value with temperature, expected absolute values of the gate-to-source voltage for a fixed gate input current as well as the variation of this voltage with temperature may also be stored. This stored information combined with the operating conditions sensed during the operation of the embodiment and the switch in a voltage conversion system could provide an accurate estimate of the switch in-situ ‘on-resistance’ and thereby the average or RMS current flowing through it. One skilled in the art will recognize that the full knowledge of the operating conditions of the switches thus derived in a system employing the invention will enable the system to automatically adapt the drive currents into the switches so as to achieve maximum operating efficiency under any load or voltage conversion configuration. A sophisticated embodiment may co-package the driver and the switches in order to facilitate self-calibration as well as to estimate operating temperature with greater accuracy and to minimize parasitic element values that inhibit performance. Additionally, since the invention conceives of the use of the voltage at the output of the LC filter, it possesses knowledge of the conversion output voltage and may therefore act on it's own, varying even the frequency of the pulse-width modulated switch-actuation signals in accomplishing accurate voltage conversion at maximum efficiency without the need for any additional supervisory integrated circuit as is common in the prior art. A serial communication channel that communicates the output voltage requirements of the conversion system may in this instance replace the prior art PWM input to this sophisticated embodiment of the invention.
Although specific embodiments are illustrated and described herein, any circuit arrangement configured to achieve the same purposes and advantages may be substituted in place of the specific embodiments disclosed. This disclosure is intended to cover any and all adaptations or variations of the embodiments of the invention provided herein. All the descriptions provided in the specification have been made in an illustrative sense and should in no manner be interpreted in any restrictive sense. The scope, of various embodiments of the invention whether described or not, includes any other applications in which the structures, concepts and methods of the invention may be applied. The scope of the various embodiments of the invention should therefore be determined with reference to the appended claims, along with the full range of equivalents to which such claims are entitled. Similarly, the abstract of this disclosure, provided in compliance with 37 CFR §1.72(b), is submitted with the understanding that it will not be interpreted to be limiting the scope or meaning of the claims made herein. While various concepts and methods of the invention are grouped together into a single ‘best-mode’ implementation in the detailed description, it should be appreciated that inventive subject matter lies in less than all features of any disclosed embodiment, and as the claims incorporated herein indicate, each claim is to viewed as standing on it's own as a preferred embodiment of the invention.
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|U.S. Classification||327/108, 323/282|
|International Classification||H02M3/158, H03K3/00, H03B1/00|
|Cooperative Classification||H02M3/1588, Y02B70/1466|
|Apr 14, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Jun 6, 2014||REMI||Maintenance fee reminder mailed|
|Oct 24, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Dec 16, 2014||FP||Expired due to failure to pay maintenance fee|
Effective date: 20141024