|Publication number||US7135375 B2|
|Application number||US 11/053,721|
|Publication date||Nov 14, 2006|
|Filing date||Feb 8, 2005|
|Priority date||Dec 13, 2001|
|Also published as||US6521506, US6891251, US20030122128, US20050245038|
|Publication number||053721, 11053721, US 7135375 B2, US 7135375B2, US-B2-7135375, US7135375 B2, US7135375B2|
|Inventors||Douglas D. Coolbaugh, James S. Dunn, Michael D. Gordon, Mohamed Y. Hammad, Jeffrey B. Johnson, David C. Sheridan|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (17), Referenced by (4), Classifications (17), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. application Ser. No. 10/323,022, filed Dec. 18, 2002 now U.S. Pat. No. 6,891,251, which application is a divisional application of U.S. application Ser. No. 10/016,539, filed Dec. 13, 2001, now U.S. Pat. No. 6,521,506.
1. Field of the Invention
The present invention relates to complementary metal oxide semiconductor (CMOS) and bipolar/CMOS (BiCMOS) devices which include a varactor that has improved tunability associated therewith as well as processes for fabricating such devices. The inventive electronic devices, which include the varactor, are highly suitable for use in mobile or cellular phones, personnel digital assistances (PDAs) and other high RF (radio frequency) electronic devices.
2. Background of the Invention
Varactors are electronic devices which have a capacitance that is controlled by a suitable voltage or current bias. Varactors are typically employed, for example, in so-called voltage controlled oscillators (VCOs) where a frequency of an oscillator is controlled by an applied current or voltage. In such instances, the VCOs are used when a variable frequency is required, or when a signal needs to be synchronized to a reference signal.
In radio communication devices such as mobile/cellular phones, VCOs are typically employed in phase locked loop circuits to generate suitable signals including: generation of a reference signal that is synchronized with a signal received by a radio receiver; modulation/demodulation operations and frequency synthesis.
Numerous varactors have been developed and are successfully employed in integrated circuit technologies. For example, it is known to employ pn-diodes, Schottky diodes or MOS-diodes as a varactor in bipolar, CMOS and BiCMOS technologies. In the article to R. A. Moline, et al., entitled “Ion-Implanted Hyperabrupt Junction Voltage Variable Capacitors” IEEE Trans. Electron. Device, ED-19, pp267f, 1972, varactors comprising pn-diodes are described. U.S. Pat. No. 3,638,300 to Foxhall, et al.; U.S. Pat. No.4,226,648 to Goodwin, et al.; U.S. Pat. No. 4,827,319 to Pavlidis, et al, and U.S. Pat. No. 5,557,140 to Nguyen, et al. describe other types of variable capacitor (i.e., varactor) diodes that include hyper-abrupt ion-implanted junctions. The term ‘hyper-abrupt’ denotes that the implant has a doping profile that is in contact with the wall of the adjacent extrinsic base region. U.S. Pat. No. 4,973,922 to Embree, et al.; U.S. Pat. No. 5,965,912 to Stolfa, et al; and U.S. Pat. No. 6,100,770 to Litwin, et al., on the other hand, describe MOS-diodes which are employed as varactors.
The integration of varactors depends on the capability of the integrated circuit technology. An overview of integrated circuit devices for high RF applications in BiCMOS technology is described, for example, in J. N. Burghartz, et al. “Integrated RF and Microwave Components in BiCMOS Technology”, IEEE Trans. Electron Devices, Col. 43, pp 1559, September 1996. As is stated therein, varactors are not a part of the standard BiCMOS device set. Instead, it is proposed to employ a collector-base junction of a bipolar transistor as a varactor.
In order to use a device as a varactor, the device must satisfy one or more, preferably two or more, of the following criteria: (1) tunability must be high (on the order of about 3 or greater); (2) Quality factor, Q, must be high (on the order of about 20 or greater); and (3) the device must exhibit linearity.
Many of the known prior art varactors do not meet the above criteria. For example, traditional base-collector junction varactors rely on the NPN base-collector profile, which is not optimized for varactor tunability. In the case of hyper-abrupt base-collector junction varactors, where the doping profile of the implant is located at the “wall” of the extrinsic base region, the device lacks linearity. With traditional MOS varactors, the tunability is high; however, an even higher tunability is often required.
In view of the above-mentioned drawbacks with prior art varactors, there is a continued need for providing new and improved varactors which satisfy the above criteria and that can be integrated with CMOS and BiCMOS devices.
One object of the present invention is to provide a highly tunable varactor for use in CMOS and BiCMOS applications.
Another object of the present invention is to provide a highly tunable varactor which is also highly linear.
A yet further object of the present invention is to provide varactors which can be easily implemented in existing CMOS and BiCMOS technologies.
An even further object of the present invention is to provide methods of fabricating varactors which are highly tunable, highly linear and have the highest possible quality factor associated therewith.
These and other objects and advantages are achieved by providing either a quasi-hyper-abrupt base-collector junction varactor having an Sb (antimony) spike located between the extrinsic base and the subcollector region of a bipolar device; or alternatively, an MOS varactor having a polySi gate and a well region of opposite doping types, i.e., polarity, as well as a subcollector reach-through region to reduce well resistance.
Specifically, the quasi hyper-abrupt base-collector junction varactor of the present invention comprises:
a substrate having a collector region of a first conductivity type atop a subcollector region, said collector region has a plurality of isolation regions present therein;
reach-through implant regions located between at least a pair of said isolation regions;
a SiGe layer atop a portion of said substrate not containing a reach-through implant region, said SiGe layer having an extrinsic base region of a second conductivity type which is different from said first conductivity type; and
an antimony implant region located between said extrinsic base region and said subcollector region.
The present invention also provides a method for fabricating the above-mentioned quasi hyper-abrupt base-collector junction varactor. Specifically, the quasi hyper-abrupt base-collector junction varactor is fabricated utilizing the following processing steps which comprise:
forming a subcollector region in a lower portion of a substrate;
forming a plurality of isolation regions in an upper portion of said substrate;
forming, in any order, a collector region of a first conductivity type and an antimony implant region in said upper portion of said substrate;
forming reach-through implant regions between at least a pair of said isolation regions; and
forming an SiGe layer atop a portion of said collector region which does not include a reach-through implant region, said SiGe layer having an extrinsic base region of a second conductivity type which is different than the first conductivity type and said antimony implant region is not in contact with said extrinsic base region.
Another aspect of the present invention relates to an MOS varactor which has a well region and a poly gate region of different conductivity. Specifically, the inventive MOS varactor comprises:
a substrate having a well region of a first conductivity type atop a subcollector region, said well region has a plurality of isolation regions present therein;
reach-though implant regions located between at least a pair of isolation regions; and
a poly gate region of a second conductivity type that is different from said well region atop a portion of said well region which does not include a reach-through implant region.
The present invention also provides a method for fabricating the above-mentioned MOS varactor. Specifically, the MOS varactor of the present invention is fabricated utilizing the following processing steps which comprise:
providing a substrate having a well region of a first conductivity type atop a subcollector region, said well region including a plurality of isolation regions formed in an upper region thereof and at least a pair of said isolation regions include a reach-through implant region formed therebetween; and
forming a poly gate region on a portion of said well region not containing a reach-through implant region, said poly gate region is of a second conductivity type which is different from said first conductivity type.
The present invention, which provides novel varactors for CMOS and BiCMOS technologies as well as methods for fabricating the same, will now be described in more detail by referring to the drawings that accompany the present application.
Reference is first made to the embodiment illustrated in
Subcollector region 12 is formed by implanting dopant (n+ or p+, preferably n+) ions 14 into substrate 10 using a conventional implantation process and conditions well known to those skilled in the art. One possible dopant that may be utilized at this point of the present invention is As which can be implanted at a doping dosage of about 1.4E16 atoms/cm2 and at an energy of about 40 keV. Other dopant ions and implant conditions besides the above-mentioned can also be employed in the present invention. In a highly preferred embodiment of the present invention, subcollector region 12 is n+ doped.
After forming the subcollector region in substrate 10, an optional epi Si layer, not shown, is formed atop the surface of substrate 10 utilizing a conventional epitaxial growing process well known to those skilled in the art.
Next, and as shown in
Next, and as shown in
The Sb implant region is formed by utilizing a low dose, low energy masked ion implantation process which is capable of forming a shallow implant profile in the structure. Specifically, the Sb implant region is formed utilizing an Sb dosage of about 5E12 atoms/cm2 and at an energy of about 40 keV. It is also possible that the Sb implant region 20 is formed by utilizing an ion implantation process wherein the implant energy is from about 40 to about 70 keV. The Sb implant may be carried out using a substantially vertical ion implantation process, or, more preferably, an angle implantation process wherein the tilt angle is from about 5° to about 7° is employed.
Following formation of collector region 18 and Sb implant region 20, reach-through implant regions 22, which extend from the upper surface of substrate 10 to subcollector region 12, are formed between at least a pair of abutting isolation regions. Note that the reach-through implant regions are not formed in areas of the substrate which include the Sb implant region. The reach-through implant regions are formed by lithography, etching and ion implantation where the same dopant ion as subcollector region 12 is implanted into the substrate utilizing conventional ion implantation conditions well known to those skilled in the art. Illustrative examples of representative reach-through implant conditions that can be employed in the present invention include, but are not limited to: Sb dosage of about 1.4E14 atoms/cm2 and an energy of about 200 keV or P dosage of about 4E15 atoms/cm2 and an energy of about 70 keV. The resultant structure, including reach-through implant regions 22, is shown, for example, in
Following formation of reach-through implant regions 22, a SiGe layer is formed on the surface of the substrate utilizing a conventional epitaxial growing process and thereafter the SiGe layer is patterned so as to form a patterned SiGe layer 24 over a portion of substrate 10 (i.e., atop collector region 18) which does not include a reach-through implant region. Note that a portion of SiGe layer may lie atop the isolation regions as well as atop collector region 18. As stated above, the SiGe layer is formed utilizing a conventional epitaxial growing process which includes, but is not limited to: ultra-high vacuum chemical vapor deposition (UHVCVD), molecular beam epitaxy (MBE), rapid thermal chemical vapor deposition (RTCVD) and plasma-enhanced chemical vapor deposition (PECVD). The conditions used in forming the SiGe layer are conventional, well known in the art and may vary depending on the desired epitaxial process used in forming the same.
It is noted that the SiGe layer includes polycrystalline SiGe regions which are predominately formed atop the isolation regions as well as single crystalline SiGe regions which are formed atop the surface of exposed substrate 10. For clarity, these regions are not shown in the drawings but are meant to be included within the SiGe layer. Following formation of SiGe layer 24, extrinsic base region 26 of a second conductivity type which is different, i.e., opposite polarity, than the first conductivity type is formed in the patterned SiGe layer utilizing a conventional ion implantation process and implant conditions well known to those skilled in the art. For example, a Ge implant followed by a B implant may be employed in the present invention, when Ge is employed, a Ge dosage of about 7E14 atoms/cm2 and an energy of about 140 keV is employed. When B is employed in forming the extrinsic base, the following implant conditions may be employed: dopant dosage of about 3.4E15 atoms/cm2 and energy of about 30 keV. In a highly preferred embodiment of the present invention, the extrinsic base is p+ doped. The resultant structure formed after SiGe deposition, patterning, and extrinsic base formation is shown, for example, in
It is noted in
Reference is now made to the second embodiment of the present invention (which is depicted in
Next, reach-through implant regions 22 are formed in portions of substrate 10 utilizing the ion implantation conditions mentioned above in connection with the hyper-abrupt base-collector varactor embodiment. The resultant structure is shown in
After formation of reach-through implant regions 22 in portions of the well region, poly gate region 50, which has opposite dopant polarity than the well region, is formed utilizing conventional processing techniques that are employed in forming an MOS structure. It is noted that the term “poly gate region” is used herein to denote a gate dielectric as well as a polySi gate conductor which is formed atop the gate dielectric. The poly gate region is fabricated by first forming gate dielectric 52, such as an oxide, nitride, oxynitride or any combination thereof including a stack of two or more gate dielectrics, atop the surface of substrate 10. Gate dielectric 52 is formed by a conventional deposition process such as CVD, plasma-assisted CVD, or chemical solution deposition, or alternatively, the gate dielectric may be formed by a conventional thermal oxidation, nitridation or oxynitridation process. Following the formation of gate dielectric 52, a layer of polySi 54 is formed atop the surface of the gate dielectric utilizing a conventional deposition process. Next, the gate dielectric and polySi layer are patterned by lithography and etching providing the structure shown, for example, in
After patterning of the poly gate region, photoresist mask 56 is formed utilizing a conventional deposition process over selective portions of the structure shown in
Following doping of the polySi gate layer, photoresist 56 is removed from the structure utilizing a conventional stripping process well known in the art so as to provide the MOS varactor structure shown in
In a conventional CMOS process, it is impossible to build a MOS varactor where the gate has an opposite doping type to the underlying well region. The inventive device utilizes the reach-through regions to build a MOS varactor where the gate and the well region are opposite dopant type. The opposite polarity of the gate and well region results in a much higher tunability at the expense of series resistance. As mentioned previously, however, the inventive device controls series resistance by utilizing the reach-through/ subcollector feature.
While this invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention is not limited to the exact forms and details described and illustrated, but fall within the spirit and scope of the appended claims.
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|U.S. Classification||438/379, 438/329, 257/E27.05, 438/309|
|International Classification||H01L29/94, H01L29/93, H01L21/8222, H01L27/08, H01L21/20|
|Cooperative Classification||H01L27/0808, H01L29/94, H01L29/93, H01L27/0811|
|European Classification||H01L29/94, H01L29/93, H01L27/08C2, H01L27/08C3|
|Apr 16, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Jun 27, 2014||REMI||Maintenance fee reminder mailed|
|Nov 14, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Jan 6, 2015||FP||Expired due to failure to pay maintenance fee|
Effective date: 20141114