|Publication number||US7144772 B2|
|Application number||US 10/650,344|
|Publication date||Dec 5, 2006|
|Filing date||Aug 28, 2003|
|Priority date||Oct 30, 2002|
|Also published as||US20040108536|
|Publication number||10650344, 650344, US 7144772 B2, US 7144772B2, US-B2-7144772, US7144772 B2, US7144772B2|
|Inventors||Sung-Yung Lee, Nak-Won Jang, Heung-jin Joo|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (12), Referenced by (3), Classifications (40), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application claims priority to Korean Patent Application 2002-66520, filed on Oct. 30, 2002, the content of which is incorporated by reference herein in its entirety.
The present invention relates to a semiconductor device and a method of forming the same. More particularly, the present invention is directed to a semiconductor device having capacitors of a metal-insulator-metal structure and a method of forming the same.
A typical capacitor includes a lower electrode, an upper electrode and a dielectric film interposed therebetween. Since the capacitor accumulates charges, it has been used for data storage in semiconductor memory devices. One type of semiconductor memory device is DRAM (“dynamic random access memory”) which can form a unit cell having one transistor for inputting/outputting data and one capacitor for storing the data.
Unfortunately, with present trends toward high integration of semiconductor devices, the capacitance of semiconductor capacitors may continue to decrease. One technique which has been proposed to solve this problem is to use a dielectric film of a capacitor that has a higher dielectric value than oxide-nitride-oxide (ONO). However, the dielectric film can undesirably react on the lower electrode to deteriorate a capacitor characteristic (e.g., leakage current). In order to overcome the potential deterioration of the capacitor characteristic, a capacitor having a metal-insulator-metal (MIM) structure (hereinafter referred to as “MIM capacitor”) has been proposed. The MIM capacitor includes a lower electrode, an upper electrode, and a metal layer (particularly, noble metal layer) to reduce the capacitor leakage current. Further, the MIM capacitor may constitute the unit cell of a ferroelectric memory device. Similar to a DRAM unit cell, the unit cell of the ferroelectric memory includes one transistor and one capacitor. A difference therebetween is that the capacitor of the ferroelectric memory device has a dielectric film made of ferroelectric. Since the ferroelectric film has a polarization hysteresis characteristic, a capacitor using the ferroelectric film can retain its stored data even when its power supply is interrupted.
When fabricating a semiconductor device having the MIM capacitor, an oxidation barrier pattern is conventionally formed between a lower electrode and an underlying contact plug. During an annealing process for crystallizing a high-k dielectric film or a ferroelectric film, the lower electrode or the contact plug may be oxidized to increase contact resistance. The oxidation barrier pattern can reduce the increase of the annealing-induced contact resistance.
A first conventional method for forming a lower electrode of a conventional MIM capacitor is described below with reference to
In view of a design constraint, the oxidation barrier pattern 4 is minimally spaced apart from an adjacent oxidation barrier pattern 4. The lower electrode recess 6 may not entirely expose the top surface of the oxidation barrier pattern 4 because of an alignment margin 10 between the lower electrode recess 6 and the oxidation barrier pattern 4. That is, the top surface of the oxidation barrier pattern 4 has an area which is obtained by adding an area corresponding to the bottom surface of the lower electrode 7 a to the area corresponding to the alignment margin(s) 10 of the oxidation barrier pattern 4. Accordingly, the surface area of the lower electrode 7 a may be smaller than that of a lower electrode formed without the oxidation barrier pattern 4.
The oxidation barrier pattern 4 a is also formed on a bottom side and sidewalls of the lower electrode 7 a. In this case, a surface area of the lower electrode 7 a is smaller than that of a lower electrode without the oxidation barrier pattern 4 b. This is because the oxidation barrier layer 4 a is formed on the sidewalls of the lower electrode 7 a to thereby reduce the size of the lower electrode 7 a.
In certain embodiments, the present invention provides semiconductor devices that include an interlayer dielectric formed on a semiconductor substrate. A buried contact plug is disposed through the interlayer dielectric to be connected to a predetermined region of the semiconductor substrate. An oxidation barrier pattern is disposed on a top surface of the buried contact plug. A portion of a lower electrode is disposed on the oxidation barrier pattern. A top surface area of the oxidation barrier pattern is substantially equal to a bottom surface area of the lower electrode.
In particular embodiments, an external sidewall of the lower electrode and a sidewall of the oxidation barrier pattern are disposed in a beeline (i.e., in a substantially straight line). An upper electrode can be disposed over the lower electrode with a dielectric film therebetween. The dielectric film may be made of a high-k (dielectric coefficient) value dielectric substance that has a higher dielectric constant value than oxide-nitride-oxide (ONO). The dielectric film may be made of a ferroelectric material.
Other embodiments are directed to a method of fabricating a semiconductor device. The method includes forming an oxidation barrier pattern and a capping layer pattern which are sequentially stacked on a semiconductor substrate. A mold insulating layer having an etch selectivity with respect to the capping layer pattern is formed on a semiconductor substrate including the capping layer pattern. The mold insulating layer can be removed and/or planarized down to a top surface of the capping layer pattern. The exposed capping layer pattern is etched to form a lower electrode recess exposing an entire top surface of the oxidation barrier pattern to form a lower electrode in the lower electrode recess. In this case, the capping layer pattern is made of a material having an etch selectivity with respect to the oxidation barrier pattern.
In certain embodiments, the capping layer pattern can be made of silicon nitride. Following formation of the lower electrode, the method can further include etching the mold insulating layer to be removed and sequentially stacking a dielectric film and an upper electrode on the lower electrode. The dielectric film may be made of a dielectric substance having a higher dielectric constant than oxide-nitride-oxide (ONO). The dielectric film may be made of a ferroelectric material.
Certain embodiments are directed to a MIM capacitor including: (a) semiconductor substrate; (b) an oxidation barrier pattern residing above and in electrical communication with the semiconductor substrate, wherein the oxidation barrier pattern defines a lower electrode platform with a top surface; (c) a lower electrode having a bottom and at least one sidewall, the bottom being disposed on the oxidation barrier pattern lower electrode platform; (d) an upper electrode in spaced apart alignment with the lower electrode; and (e) a dielectric layer interposed between the upper and lower electrodes. The lower electrode bottom has a surface area that is substantially coextensive with the surface area of the top surface of the oxidation barrier pattern lower electrode platform.
Additional embodiments are directed toward a semiconductor device having a plurality of capacitors of a metal-insulator-metal structure. The capacitors each include upper electrodes, lower electrodes and a dielectric layer interposed therebetween. The capacitors reside above a semiconductor substrate with each capacitor having a corresponding oxidation barrier pattern in electrical communication with respective regions of the semiconductor substrate. The device is configured so that the lower electrodes have a bottom surface area that is substantially equal to the surface area of the upper surface of the underlying oxidation barrier pattern.
In certain embodiments, the lower electrode is substantially cylindrical with a closed continuous surface bottom. The device may be suitable to define a portion of an integrated circuit, such as the unit cell of a DRAM memory device and/or a unit cell of a ferroelectric memory device.
Other embodiments are directed to methods for fabricating a semiconductor device with a plurality of MIM capacitors in unit cells of an integrated circuit memory device. The method includes forming an oxidation barrier pattern on a semiconductor substrate; and forming a lower electrode disposed on the oxidation barrier pattern so that a top surface area of the oxidation barrier pattern is substantially equal to a bottom surface area of the lower electrode.
In particular embodiments, the lower electrode forming step may include: (a) forming a layer on the oxidation barrier pattern, the layer having a recess with a bottom that is sized to be substantially coextensive with a top surface of the oxidation barrier pattern; and (b) applying a conductive layer in the recess to thereby form the lower electrode.
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers, films, coatings and the like may also be present unless the word “directly” is used which indicates that the feature or layer directly contacts the feature or layer. Like numbers refer to like elements throughout. In addition, spatially relative terms, such as “beneath”, “below”, “lower”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
A semiconductor device including a MIM capacitor 100 according to embodiments of the present invention is now described below with reference to
Still referring to
In certain embodiments, as shown in
In certain embodiments, the oxidation barrier pattern 110 a comprises a material resistant to an oxidation process, e.g., conductive metal nitride such as TiN, TaN, TiAIN, WN, and so forth. The lower electrode 117 a may comprise a suitable conductive material, such as, for example, noble metals and/or conductive compounds containing noble materials. The noble metals include, for example, palladium (Pd), ruthenium (Ru), platinum (Pt), and iridium (Ir). An exemplary conductive compound containing a noble metal is iridium dioxide (IrO2).
Still referring to
In certain embodiments, the upper electrode 122 can comprise a suitable conductive material(s) such as noble metals and/or conductive compounds containing the noble metals. The noble metals include, for example, palladium (Pd), ruthenium (Ru), platinum (Pt), and iridium (Ir). An exemplary conductive compound containing a noble metal is iridium dioxide (IrO2).
The dielectric film 120 may comprise a high dielectric constant (“high-k”) dielectric material or substance having a higher dielectric constant that is greater than that of ONO (oxide-nitride-oxide). In certain embodiments, the dielectric film 120 is made of, for example, aluminum oxide (Al2O3) or hafnium oxide (HfO2). In certain embodiments, the capacitor 100, typically having the high-k dielectric film 120, can be used as a capacitor constituting a unit cell of a DRAM memory device. Unlike conventional unit cell capacitors of a DRAM device, the dielectric film 120 can comprise a ferroelectric substance such as PZT, SBT, BLT or combinations thereof. In particular embodiments, the capacitor 100 which may have the ferroelectric dielectric film 120, is used as a capacitor constituting a unit cell of a ferroelectric memory device. As such, the unit memory cell may include a transistor in communication with the capacitor.
A method of fabricating a semiconductor device including a MIM capacitor according to embodiments of the present invention is now described below with reference to
A mold insulating layer 114 is formed over the surface of the stacked semiconductor substrate 101 including the capping layer pattern 112 a and the oxidation barrier layer pattern 110 a. The mold insulating layer 114 can be made of an insulating material having an etch selectivity with respect to the material forming the capping layer pattern 112 a. In addition, the mold insulating layer 114 can have an etch selectivity with respect to the material forming the oxidation barrier layer pattern 110 a and the material forming the etch-stop layer 105. The mold insulating layer 114 may be made of, for example, silicon oxide.
By means of a suitable material removal process, such as, but not limited to, an etch-back or chemical mechanical polishing (CMP) technique, the mold insulating layer 114 can be planarized down to a top surface of the capping layer pattern 112 a as shown in
A dielectric film 120 can then be conformably formed over the exposed surface (typically the entire surface) of the stacked configuration overlying and/or the semiconductor substrate 101 where the etch-stop layer 105 is exposed. The upper electrode 122 is formed on and/or over the dielectric film 120 above the lower electrode 117 a. The capacitor 100 includes the lower electrode 117 a, the dielectric film 120, and the upper electrode 122.
As described above, the dielectric film 120 may comprise a high-k dielectric material that has a higher dielectric constant than ONO (oxide-nitride-oxide). For example, the high-k dielectric material can be aluminum oxide (Al2O3) and/or hafnium oxide (HfO2). As also described above, in certain embodiments, a capacitor having the high-k dielectric film may be used as a capacitor constituting a unit cell of a DRAM memory device. Unlike prior unit cells of DRAM memory devices, the dielectric film 120 may be made of and/or comprise a ferroelectric material such as PZT, SBT, BLT or combinations thereof. In addition, in certain embodiments, a capacitor having the ferroelectric dielectric film 120 may be used as a capacitor constituting a unit cell of a ferroelectric memory device.
In certain embodiments and as also discussed above, the upper electrode 122 is made of one or more conductive materials such as noble metals and/or conductive compounds containing the noble metals. The noble metals include, for example, palladium (Pd), ruthenium (Ru), platinum (Pt), and iridium (Ir). An exemplary conductive compound containing a noble metal is, for example, iridium dioxide (IrO2).
In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims. Thus, the foregoing is illustrative of the present invention and is not to be construed as limiting thereof. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. In the claims, means-plus-function clauses, where used, are intended to cover the structures described herein as performing the recited function and not only structural equivalents but also equivalent structures. Therefore, it is to be understood that the foregoing is illustrative of the present invention and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.
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|U.S. Classification||438/244, 257/E21.274, 438/239, 257/E21.021, 257/E21.59, 257/E27.104, 438/238, 257/E21.396, 438/197, 438/243, 257/E27.089, 257/E21.009, 257/E21.664, 438/142, 257/E21.018, 257/E21.648, 257/303, 257/301|
|International Classification||H01L27/108, H01L27/115, H01L21/8246, H01L21/8242, H01L21/316, H01L21/02, H01L21/768, H01L27/04|
|Cooperative Classification||H01L27/11507, H01L21/76895, H01L21/31604, H01L28/90, H01L27/10817, H01L28/75, H01L28/55, H01L27/10852, H01L27/11502|
|European Classification||H01L27/108M4B2, H01L28/75, H01L27/108F2M, H01L27/115C, H01L27/115C4|
|Aug 29, 2003||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, SYNG-YUNG;JANG, NAK-WON;JOO, HEUNG-JIN;REEL/FRAME:014454/0743
Effective date: 20030818
|May 26, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Jul 18, 2014||REMI||Maintenance fee reminder mailed|
|Dec 5, 2014||LAPS||Lapse for failure to pay maintenance fees|
|Jan 27, 2015||FP||Expired due to failure to pay maintenance fee|
Effective date: 20141205