|Publication number||US7148143 B2|
|Application number||US 10/808,168|
|Publication date||Dec 12, 2006|
|Filing date||Mar 24, 2004|
|Priority date||Mar 24, 2004|
|Also published as||US20050215055, US20070063294, WO2005094534A2, WO2005094534A3|
|Publication number||10808168, 808168, US 7148143 B2, US 7148143B2, US-B2-7148143, US7148143 B2, US7148143B2|
|Inventors||Haowen Bu, Jiong-Ping Lu, Shaofeng Yu, Ping Jiang, Clint Montgomery|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (6), Referenced by (15), Classifications (41), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention is directed, in general, to a semiconductor device and, more specifically, to a semiconductor device having a fully silicided gate electrode, a method of manufacture therefor, and an integrated circuit including the same.
Metal gate electrodes are currently being investigated to replace polysilicon gate electrodes in today's ever shrinking and changing transistor devices. One of the principle reasons the industry is investigating replacing the polysilicon gate electrodes with metal gate electrodes is in order to solve problems of poly-depletion effects and boron penetration for future CMOS devices. Traditionally, a polysilicon gate electrode with an overlying silicide was used for the gate electrodes in CMOS devices. However, as device feature size continues to shrink, poly depletion becomes a serious issue when using polysilicon gate electrodes.
Accordingly, metal gates have been proposed. However, in order to optimize the threshold voltage (Vt) in CMOS devices, the metal gates need dual tunable work functions. For instance, the metal gates need tunable work functions for NMOS and PMOS devices similar to present polysilicon gate technology, requiring the work functions of metal gates to range from 4.1˜4.4 eV for NMOS and 4.8˜5.1 eV for PMOS (see, B. Cheng, B. Maiti, S. Samayedam, J. Grant, B. Taylor, P. Tobin, J. Mogab, IEEE Intl. SOI Conf. Proc., pp. 91–92, 2001).
Recently, silicided metal gates have been investigated based on the extension of existing self-aligned silicide (SALICIDE) technology. In this approach, polysilicon is deposited over the gate dielectric. A metal is deposited over the polysilicon and reacted to completely consume the polysilicon resulting in a fully silicided metal gate, rather than a deposited metal gate. The silicided metal gate provides a metal gate with the least perturbation to the conventional process and avoids contamination issues. Furthermore, poly doping has been shown to affect the work function of the silicided metal gates.
The silicided metal gates are not without their problems. One of the more significant problems associated with the silicided metal gates is attributed to the simultaneous formation of the silicided metal gate and the silicided source/drain regions. When formed simultaneously, the depth of the silicided source/drain regions is directly proportional to the thickness of the polysilicon gate electrode. As the polysilicon gate electrodes currently range in thickness from about 60 nm to about 120 nm, the silicided source/drain regions ultimately extend into the silicon substrate by up to about 60 nm to about 120 nm, respectively. Deep silicided source/drain regions are nonetheless undesireable.
Various companies in the industry have attempted to separate the silicidation of the polysilicon gate and the silicidation of the source/drain regions. Those companies employ chemical mechanical polishing (CMP) technology to separate the steps. In such integration schemes, the gate electrode is masked by a silicon oxide layer and a silicide is then formed on the source/drain regions. Next, a blanket dielectric layer is deposited over the gate stack and silicided source/drain regions. The CMP process is then employed to expose the gate electrode for silicidation, while the source/drain regions are covered by the protective dielectric layer. The main drawback of this approach originates from the across-wafer non-uniformity inherently associated with polishing (such as dishing, etc.). In addition, the poly height on the active area may be different from the designed poly height. As a result, the height of the poly gate after polishing may suffer significant variation. Therefore, the silicidation may be inconsistent across-wafer, and/or wafer-to-wafer due to the thickness variation in poly-gate.
Accordingly, what is needed is a method for manufacturing silicided metal gate structures separate from the silicided source/drain regions that does not experience the drawbacks of the prior art methods.
To address the above-discussed deficiencies of the prior art, the present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device, among other possible elements, includes a silicided gate electrode located over a substrate, the silicided gate electrode having gate sidewall spacers located on sidewalls thereof. The semiconductor device further includes source/drain regions located in the substrate proximate the silicided gate electrode, and silicided source/drain regions located in the source/drain regions and at least partially under the gate sidewall spacers.
The present invention further includes a method for manufacturing a semiconductor device. The method includes forming a protective layer over a polysilicon gate electrode located over a substrate to provide a capped polysilicon gate electrode and then forming source/drain regions in the substrate proximate the capped polysilicon gate electrode. The method further includes removing the protective layer using an etchant, siliciding the polysilicon gate electrode to form a silicided gate electrode, and siliciding the source/drain regions.
The foregoing has outlined preferred and alternative features of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiment as a basis for designing or modifying other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention.
The invention is best understood from the following detailed description when read with the accompanying FIGUREs. It is emphasized that in accordance with the standard practice in the semiconductor industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
Referring initially to
The gate structure 130 illustrated in
The silicided gate electrode 150 may also include a dopant or combination of several types of dopants therein. The dopant, such as boron, phosphorous, arsenic or another similar dopant based on whether the semiconductor device 100 is operating as a PMOS device or an NMOS device, is configured to tune the minimum energy required to bring an electron from the Fermi level to the vacuum level, or the so called work function.
The gate structure 130 further contains gate sidewall spacers 160 flanking both sides of the silicided gate electrode 150 and gate oxide 140. The gate sidewall spacers 160 in the embodiment of
The semiconductor device 100 illustrated in
Turning now to
Located within the substrate 210 in the embodiment shown in
Located over the substrate 210 in the embodiment of
Any one of a plurality of manufacturing techniques could be used to form the gate oxide 240. For example, the gate oxide 240 may be either grown or deposited. Additionally, the growth or deposition steps may require a significant number of different temperatures, pressures, gasses, flow rates, etc.
While the advantageous embodiment of
The deposition conditions for the polysilicon gate electrode 250 may vary, however, if the polysilicon gate electrode 250 were to comprise standard polysilicon, such as the instance in
The partially completed semiconductor device 200 illustrated in
Optionally located over the protective layer 260 is a silicon dioxide layer 270. The optional silicon dioxide layer 270 is designed to help pattern the gate oxide 240, polysilicon gate electrode 250 and protective layer 260. With that said, those skilled in the art understand that the gate oxide 240, polysilicon gate electrode 250, protective layer 260 and optional silicon dioxide layer 270 were originally blanket deposited. Those blanket layers were subsequently patterned resulting in the gate oxide 240, polysilicon gate electrode 250, protective layer 260 and optional silicon dioxide layer 270 illustrated in
Turning briefly to
The offset nitride spacer 330 may comprise a standard silicon nitride spacer or a silicon nitride layer having carbon therein. If the offset nitride spacer 330 were to contain the carbon, the carbon might form from about 5% to about 10% of the layer. While the oxide layer 320 and the offset nitride spacer 330 are shown located only along the sides of the gate structure 230, those skilled in the art are aware that the layers were previously blanket formed and subsequently anisotropically etched to form the oxide layer 320 and the offset nitride spacer 330.
Turning now to
Turning now to
The L-shaped nitride spacers 520 may comprise any type of nitride, however, in an exemplary embodiment the L-shaped nitride spacers 520 comprise a nitride material that includes carbon. The carbon content, which may range from about 5% to about 10% of the L-shaped nitride spacers 520, is included within the L-shaped nitride spacers 520 to change the rate at which they etch. In the embodiment where the L-shaped nitride spacers 520 include carbon, the L-shaped nitride spacers 520 may be deposited using bis t-butylaminosilane (BTBAS) and ammonia (NH3) precursors in a CVD reactor. Advantageously, the carbon causes the L-shaped nitride spacers 520 to etch at a slower rate than a traditional nitride layer. In an exemplary situation, after having been annealed using a temperature ranging from about 1000° C. to about 1100° C., the carbon causes the L-shaped nitride spacers 520 to have an etch selectivity of about 50:1 when compared to the traditional nitride layer.
The sidewall oxides 530 that are located over the L-shaped nitride spacers 520 are conventional. In the given embodiment of
Turning now to
The formation of the highly doped source/drain implants 610 is also conventional. Generally the highly doped source/drain implants 610 have a peak dopant concentration ranging from about 1E18 atoms/cm3 to about 1E21 atoms/cm3. Also, the highly doped source/drain implants 610 should typically have a dopant type opposite to that of the well region 220 they are located within. Accordingly, in the illustrative embodiment shown in
Turning now to
Additionally illustrated in
A number of different manufacturing techniques could be used to manufacture the silicide blocking layers 720. While both techniques include one form or another of a dry oxidation, one technique is a high temperature oxidation and the other is a low temperature oxidation (e.g., a plasma oxidation process). As one would expect, each technique has its benefits and drawbacks. For instance, the low temperature oxidation technique may be conducted at a temperature ranging from about 200° C. to about 600° C. and has the benefit of not changing the doping profile of the source/drain regions 710. Unfortunately, the low temperature oxidation technique often involves oxygen radicals or energetic ions that form a thin oxide layer on the protective layer 260. Although the thickness of the oxide grown on the protective layer 260 should be less than the thickness grown on the source/drain regions 710, it must nonetheless subsequently be removed. At the same time a portion of the silicide blocking layer 720 must remain on the source/drain regions 710.
Alternatively, the higher temperature oxidation technique may be conducted with a rapid thermal oxidation (RTO) technique at a temperature ranging from about 900° C. to about 1000° C. and has the benefit of not forming the thin layer of oxide on the protective layer 260. Unfortunately, the higher temperature oxidation technique causes the doping profiles of the source/drain regions 710 to move. This can be accommodated in the transistor design, but it must be addressed at some point. Nonetheless, while the low and high oxidation techniques each have specific but different benefits, it is currently believed that the low temperature oxidation technique provides better results.
Turning now to
Turning now to
The first RTA is designed to convert the polysilicon gate electrode 250 to the silicided gate electrode 910. The annealing temperature depends on the silicide metal being used. For example, it is believed that the first RTA may be conducted at a temperature ranging from about 400° C. to about 600° C. and a time period ranging from about 10 second to about 100 seconds to accomplish the silicidation when nickel is used. It should be noted that other temperatures, times, and processes could be used.
In a preferred embodiment, the blanket layer of nickel fully silicidizes the polysilicon gate electrode 250. As it takes approximately 1 nm of nickel to fully silicidize approximately 1.8 nm of polysilicon, the thickness of the blanket layer of nickel should be at least 56% of the thickness of the polysilicon gate electrode 250. To be comfortable, however, it is suggested that the thickness of the layer of nickel should be at least 60% of the thickness of the polysilicon gate electrode 250. Thus, where the thickness of the polysilicon gate electrode 250 ranges from about 50 nm to about 150 nm, as described above, the thickness of the blanket layer of nickel should range from approximately 30 nm to about 90 nm. It should also be noted that the blanket layer of silicidation material may comprise a number of different metals or combinations of metals while staying within the scope of the present invention. After fully silicidizing the polysilicon gate electrode 250, any remaining unreacted metal materials, which happens to be nickel in this embodiment, may be removed. The silicide does not form on the source/drain region 710 at this time because of the silicide blocking layer 720.
Turning now to
Turning now to
Turning now to
The second RTA process may be conducted using a variety of different temperatures and times. Nonetheless, it is believed that the second RTA process, in an exemplary embodiment, should be conducted in a rapid thermal processing tool at a temperature ranging from about 400° C. to about 600° C. for a time period ranging from about 5 seconds to about 60 seconds. The specific temperature and time period are typically based, however, on the ability to form the silicided source/drain contact regions 1210 to a desired depth, as well as the silicide materials selected.
After completing the silicided source/drain contact regions 1210, the partially completed semiconductor device 200 is subjected to a selective removal process. For instance, in one embodiment of the invention the device could be subjected to an etch recipe consisting of sulfuric acid (H2SO4), hydrogen peroxide (H2O2) and water (H2O). This specific etch recipe has a high degree of selectivity and could easily remove any remaining portions of the source/drain silicidation layer 1110. Thereafter the manufacture of the partially completed semiconductor device 200 would continue in a conventional manner, optimally resulting in a device similar to the semiconductor device 100 illustrated in
It should be noted that the exact order of the steps illustrated with respect to
The method of manufacturing the semiconductor device as discussed with respect to
Turning briefly to
Referring finally to
Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.
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|U.S. Classification||438/682, 438/791, 438/300, 438/744, 438/618, 438/669, 438/655, 438/664, 257/E21.166, 257/536, 257/E21.636, 438/721, 438/649, 438/230, 438/199, 438/583, 257/E21.203, 257/E29.161, 257/E21.439, 257/E21.64, 257/E29.266|
|International Classification||H01L21/336, H01L29/78, H01L29/49, H01L21/461, H01L21/4763, H01L21/44, H01L21/8238, H01L21/28, H01L21/302|
|Cooperative Classification||H01L21/823835, H01L21/823864, H01L29/7833, H01L21/28097, H01L29/4975, H01L29/6656, H01L29/6659, H01L29/66507|
|European Classification||H01L29/66M6T6F10, H01L29/66M6T6F3B, H01L21/28E2B7|
|Oct 8, 2004||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BU, HAOWEN;LU, JIONG-PING;YU, SHAOFENG;AND OTHERS;REEL/FRAME:015233/0534
Effective date: 20040324
|May 21, 2010||FPAY||Fee payment|
Year of fee payment: 4
|May 28, 2014||FPAY||Fee payment|
Year of fee payment: 8