|Publication number||US7154805 B2|
|Application number||US 11/085,507|
|Publication date||Dec 26, 2006|
|Filing date||Mar 22, 2005|
|Priority date||Nov 26, 1991|
|Also published as||US6347051, US6567334, US6788609, US6925012, US7002851, US7006386, US7064995, US7082510, US7123519, US7184320, US7327624, US7379379, US7447072, US7715243, US8031536, US20010030890, US20020085416, US20030210587, US20040208060, US20050162899, US20050162900, US20050162901, US20050162902, US20050166088, US20050169045, US20050289389, US20070058475, US20070070694, US20070076507, US20080106939, US20100191902|
|Publication number||085507, 11085507, US 7154805 B2, US 7154805B2, US-B2-7154805, US7154805 B2, US7154805B2|
|Inventors||Hajime Yamagami, Kouichi Terada, Yoshihiro Hayashi, Takashi Tsunehiro, Kunihiro Katayama, Kenichi Kaki, Takeshi Furuno|
|Original Assignee||Renesas Technology Corp.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (104), Non-Patent Citations (3), Referenced by (6), Classifications (34), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a continuation of U.S. application Ser. No. 10/847,917, filed May 19, 2004, now U.S. Pat. No. 6,925,012 which in turn, is a continuation of U.S. application Ser. No. 10/409,080, filed Apr. 9, 2003, now U.S. Pat. No. 6,788,609, which, in turn, is a continuation of U.S. application Ser. No. 10/046,416, filed Oct. 10, 2001, now U.S. Pat. No. 6,990,264, which, in turn, is a continuation of U.S. application Ser. No. 09/866,622 filed May 30, 2001, now U.S. Pat. No. 6,347,051, which, in turn, is a continuation of U.S. application Ser. No. 09/660,648, filed Sep. 12, 2000, now U.S. Pat. No. 6,341,085, which, in turn, is a continuation of U.S. application Ser. No. 08/782,344, filed Jan. 13, 1997, now U.S. Pat. No. 6,130,837, and which, in turn, is a continuation of U.S. application Ser. No. 07/981,438, filed Nov. 25, 1992, now U.S. Pat. No. 5,644,539; and the entire disclosures of which are incorporated herein by reference.
The present invention relates to a storage device employing a flash memory. More particularly, it relates to a method of extending the service life of such a storage device.
A magnetic storage device is the most commonly used prior-art auxiliary storage for information equipment. With the magnetic storage device, a file to be written thereinto is divided into a data storing unit called a “sector”, and it is stored in correspondence with the physical position of a storage medium. That is, in rewriting a certain file, the data of the file are written into basically the same position. Herein, when the quantity of data to be written has increased, new sectors are used for the increased data. Also, an optical disk storage device is mentioned as another auxiliary storage. The optical disk storage device which is conventional in the art at present can write data thereinto only once, and cannot erase data therefrom. In rewriting a file written once, accordingly, an actual rewriting operation is not performed, but the data of the file are written into a different part of the storage area. The data of the file written before are invalidated so as not to be read out thenceforth. That is, unlike the magnetic disk storage device, the optical disk storage device fulfills the function of the auxiliary storage in accordance with the scheme that the rewritten data and the locations thereof are not correlated at all.
In recent years, a semiconductor file storage device has been designated for use as an auxiliary storage, which employs a semiconductor memory in contrast to the above storage devices in each of which a disk is rotated to access the data of large capacity at high speed. In particular, a device employing a nonvolatile memory which is electrically rewritable (hereinbelow, expressed as the “EEPROM” short for electrically erasable and programmable read-only memory) will form the mainstream of the semiconductor file storage device in the future.
A technique which concerns the storage device employing the EEPROM is disclosed in the official gazette of Japanese Patent Application Laid-open No. 25798/1991. This technique is intended to realize a practical storage device by the use of the EEPROM in spite of the drawback of the EEPROM which limits the number of rewriting erase operations. To sum up, a plurality of memory elements (EEPROM elements) are prepared, and the number of rewriting erase operations of the individual elements are recorded and managed. When one of the memory elements has reached a prescribed number of operations below the guaranteed number of rewrite operations of the EEPROM, it is changed-over to another memory element, which is then used for storing data. Thus, the stored data are protected.
The prior-art storage devices mentioned above will be discussed further.
According to the scheme of the optical disk storage device, each time the file is rewritten, the part of the storage area corresponding thereto is ruined. This incurs the problem that a satisfactory storage area cannot be secured without a storage medium having a very large capacity. Especially in the case of the storage device of the information equipment in which the files are frequently rewritten, the required storage area increases even when the actual capacity for storing the data of the files is not very large.
On the other hand, with the magnetic disk storage device which is the most commonly used as the auxiliary storage, when the file written once is to be rewritten, advantageously the new data are written into the same part of a storage area. In the application of such a rewriting operation to the EEPROM, however, a file (usually called “directory file”) for listing the stored data files, a file (“file allocation table”) for referring to the locations of the data files, etc. need to be rerecorded at each access for writing data, so that the rewriting operations concentrate locally. As a result, the EEPROM which has a limited number of writing erase operations has its service life shortened drastically.
The technique utilizing the EEPROM as disclosed in the official gazette of Japanese Patent Application Laid-open No. 25798/1991, consists of the scheme whereby the deteriorated state of the memory element is grasped in terms of the number of erase operations, whereupon the memory element is changed-over to the substitutive memory element before being ruined. This scheme necessitates a memory capacity which is, at least, double the actual capacity for storing the data of files. That is, the substitutive memory element is not used at all until the memory element used first is ruined. Besides, the ruined memory element is then quite unnecessary. These conditions render the physical volume and weight of the storage device very wasteful. Moreover, since all the data of the memory element are not usually rewritten, it is uneconomical that the memory chip having been only partly deteriorated is entirely brought into the state of nonuse.
It is accordingly desired to realize a semiconductor file storage device which has a longer service life and which is smaller in size and more economical.
Meanwhile, a DRAM (dynamic random access memory) or an SRAM (static random access-memory) has been employed as the storage medium of a semiconductor disk storage device. Also, a flash memory has been known as one sort of EEPROM.
With the flash memory, data can be read therefrom in small data units, such as in bytes or word units, as in the case of the DRAM or the SRAM. Since, however, the flash memory is limited in the number of rewrite operations, data are written thereinto by reducing the number of rewrite operations in such a way that a rewriting unit is set at a block unit such as of 512 bytes.
Also, it is structurally required of the flash memory to erase data before the rewriting operation. Therefore, some flash memory devices are endowed with the command process functions of “erase” etc.
Anyway, the limited number of rewrite operations is the most serious problem in the case where the flash memory is employed as the storage medium of a semiconductor disk storage device. Since a directory area and an FAT (file allocation table) area, for example, are rewritten more frequently than the other areas, only the specified blocks of the flash memory for the directory and FAT areas are more liable to exceed the limit of rewrite operations of the flash memory. Consequently, the whole semiconductor disk becomes unusable due to the abnormalities of only the specified blocks, and the semiconductor disk is of low reliability on account of the short service life thereof.
It is accordingly desired to realize a semiconductor disk storage device which has a longer service life.
An object of the present invention is to provide a storage device employing a flash memory, which has a longer service life and which is smaller in size and more economical then conventional storage devices.
Another object of the present invention is to extend the service life of a semiconductor disk storage device employing a flash memory.
In one aspect of performance of the present invention, a storage device employing a flash memory comprises a storage area which is divided into physical areas that are identified by physical area identification information; logical area conversion means supplied with logical area identification information being virtual identification information in an operation of writing data, for converting the logical area identification information into the physical area identification information corresponding thereto in the case of writing the data into a logical area; and a memory controller which receives the physical area identification information resulting from the conversion, and which writes the data into the physical area; the logical area conversion means being capable of converting the identical logical area identification information into the plurality of items of physical area identification information.
In operation, when the physical area into which the data is to be written is normal, the memory controller writes the data into this physical area. On the other hand, when the physical area is abnormal, the memory controller writes the data into another of the physical areas based on the logical area identification information.
Now, the operation of the semiconductor disk storage device 1 in this embodiment will be explained. It is first assumed that an instruction for reading out file data has been received from the host bus 3. In this case, the microcomputer 4 processes the instruction, but the control contents thereof differ depending upon the ways in which the instruction is given. For example, in a case where the allocation information of the file data to be read out is afforded in terms of a sector number or a track number as in a magnetic disk storage device etc., the sector or track number needs to be converted into the physical address of the data memory 8. In this embodiment, for the sake of brevity, the allocation information from the host bus 3 is assumed to be the block number of the data memory 8. The block number corresponds to the upper bits of the physical address.
Next, let's consider a case where an instruction for writing file data has been received from the host bus 3.
In the exemplified processing of this embodiment, only the check of the write operation is performed at the step 207 in
Although the substitutive memory area 73 and the error information area 71 are provided in the error memory 7 in this embodiment, they may well be formed by separate memory chips. On the contrary; an error information area and a substitutive memory area may well be provided in the data memory 8.
An architectural diagram in the latter case is illustrated in
Now, the operation of this embodiment will be explained. First,
Next, there will be explained a case where the semiconductor disk storage device 1 has received a write instruction from the host bus 3.
Although each of the substitutive memory area 83 and the data area 84 is formed of only one area in this example, a plurality of substitutive memory areas 83 and a plurality of data areas 84 may well be provided by setting other address information and storage capacities anew in the initialize information area 81.
As thus far described, in the semiconductor disk storage device which employs the flash memory as its storage medium, the errors attributable to the limited number of rewrite operations of the flash memory can be remedied, so that the service life of the semiconductor disk storage device can be extended.
Now, there will be explained methods of determining the storage capacities of the substitutive memory areas 73, 83 and the error information areas 71, 82 in the embodiments of
First, the storage capacity of the substitutive memory area 73 or 83 depends upon the number of those blocks in the data memory 8 which the host system 2 uses as areas to be rewritten most frequently, for example, as FAT and directory areas. Here in this example, it is assumed that a storage capacity of 128 kB is used as the FAT and directory areas in the data memory 8 of 32 MB. Herein, a storage capacity of 384 kB, triple the value 128 kB, is set for the substitutive memory area 73 or 83, even the errors of the entire FAT and directory areas can be replaced three times. Therefore, the service life of the semiconductor disk storage device 1 is quadrupled.
Thus, when the service life of the semiconductor disk storage device 1 is to be prolonged n times, the substitutive memory area 73 or 83 may be endowed with a storage capacity which is (n−1) times as large as the total storage capacity of the areas that are frequently rewritten in the data memory 8. In the case of the embodiment in
Next, the storage capacity of the error information area 71 or 82 will be studied. In the case of the embodiment in
On the other hand, in the case of the embodiment in
The remaining storage capacity is assigned to the usage information area 72 or the initialize information area 81.
In dividing the error memory 7 or the data memory 8 into the areas as stated above, it is conveniently partitioned into block units Which are the rewriting units of the flash memory.
In this manner, according to the present invention, a storage capacity of 2% or less with respect to the full storage capacity of the flash memory is used for the error information area 71 or 82 and the substitutive memory area 73 or 83, whereby the service life of the semiconductor disk storage device 1 can be doubled or increased even more. Besides, when the service life is to be extended still more, the storage capacity of the substitutive memory area 73 or 83 may be increased, whereby the service life is prolonged to that extent.
Now, there will be explained the interface between the host system 2 and the semiconductor disk storage device 1 in the first or second embodiment. The host system 2 is an information processing equipment such as personal computer or word processor. The host bus 3 is a bus to which the host system 2 usually connects a file device such as magnetic disk storage device. In general, the host bus 3 for connecting the magnetic disk storage device is a SCSI (small computer system interface) or an IDE (Integrated drive engineering) interface. When the semiconductor disk storage device 1 of the present invention is connected to the host bus 3 of the SCSI, the IDE interface or the like similarly to the magnetic disk storage device, the conversion of the magnetic disk storage device to the semiconductor disk storage device 1 is facilitated.
In order to connect the semiconductor disk storage device 1 to the SCSI or the IDE interface, the interface thereof needs to be made the same as that of the magnetic disk storage device. To this end, first of all, the size of each block of the flash memory must be brought into correspondence with that of each sector of the magnetic disk storage device. In the foregoing embodiments, the block size is set at 512 bytes, which conforms to the sector size of the magnetic disk storage device. In a case where the block size is smaller than the sector size of the magnetic disk storage device, no problem is posed using a plurality of blocks as one sector. On the other hand, in a case where the block size is larger, one block needs to be divided into two or more sectors. In addition, regarding the tracks and headers of the magnetic disk storage device, the flash memory may be logically allotted to such tracks and headers. Besides, the interface items of the semiconductor disk storage device 1, such as control registers and interrupts, are made the same as those of the magnetic disk storage device, so as to control the semiconductor disk storage device 1 by the input/output instructions of the magnetic disk storage device delivered from the host bus 3. However, instructions peculiar to the magnetic disk storage device, for example, a process for the control of a motor, must be converted into different processes.
Table 1 below exemplifies instructions for the magnetic disk storage device, the processes of the magnetic disk storage device responsive to the instructions, and the processes of the semiconductor disk storage device 1 in the case where the instructions of the magnetic disk storage device are applied to the semiconductor disk storage device 1 as they are. In the table, a column “Semiconductor disk process” indicates the processes which are executed when the microcomputer 4 functions as the acceptance means for accepting the instructions for the semiconductor disk storage device 1 and the conversion means for converting the instructions.
CONVERSION OF MAGNETIC DISK INSTRUCTIONS
INTO SEMICONDUCTOR DISK INSTRUCTIONS
A head is moved to
Data are read from
A designated sector
is converted into a
from which data are
Data are written
A designated sector
into a designated
is converted into a
into which data are
The ECC check for a
Headers and data
A flash memory is divided
fields are generated
into a data memory area,
in a track, and
a substitutive memory
defective sectors are
area and an error memory
area, and initial values
are set in the error
A head is moved to a
A drive is
The capacities etc.
of the flash memory
internal counters are
Data are read from
Data are read from a
a plurality of
plurality of sectors.
Data are written
Data are written into
into a plurality
a plurality of
The examples of Table 1 are of the IDE interface. In the table, the instructions No. 1 and No. 6 are for moving the head. Herein, since the semiconductor disk storage device 1 has no head, no process is executed in response to the instruction No. 1 or No. 6. Moreover, the flash memory need not have any ECC (error correction code) set because the error rate thereof is much lower than that of the magnetic disk storage device. Therefore, the semiconductor disk storage device 1 executes no process in response to the instruction “Read Verify Sector”. The other instructions are as listed in Table 1.
Incidentally, even in the case of no process indicated in Table 1, when an interrupt or the like is issued in the magnetic disk storage device, an interrupt is similarly issued in the semiconductor disk storage device 1. That is, the interface is established so that the magnetic disk storage device and the semiconductor disk storage device 1 may not be distinguished as viewed from the host bus 3.
As thus far described, the interface of the semiconductor disk storage device 1 is made the same as that of the magnetic disk storage device, whereby the replacement of the magnetic disk storage device with the semiconductor disk storage device 1 is facilitated
Regarding the SCSI interface of the semiconductor disk storage device 1, the replacement can be easily done by establishing the same interface as that of the magnetic disk storage device as in the case-of the IDE interface. Since, however, devices other than the magnetic disk storage device, such as a magnetooptic disk storage device, can be connected to the SCSI interface, the file device has an individual instruction system, Accordingly, the semiconductor disk storage device 1 can also eliminate useless processes and raise its operating speed when a dedicated instruction system is set therefor. Basically, however, the instruction system of the semiconductor disk storage device 1 is the same as that of the magnetic disk storage device, without a motor control command etc. In this case, the block size of the flash memory may be as desired, and one block of the flash memory may be processed as one sector. Besides, the processes of the microcomputer 4 and the processes of the flow charts of
Meanwhile, the specifications of JEIDA (Japan Electronic Industry Development Association) and PCMCIA. (Personal Computer Memory Card International Association) are known as the standard specifications of IC card interfaces. The semiconductor disk storage device 1 of the present invention may well be constructed in the form of an IC card with its interface conformed to the JEIDA or PCMCIA specifications. In this case, the semiconductor disk storage device 1 is dealt with as an I/O device.
The advantages of the semiconductor disk storage device 1 over the magnetic disk storage device are as follows: Since the semiconductor disk storage device 1 suffices with a smaller number of processes than the magnetic disk storage device as indicated in Table 1, it can be operated at a higher speed. In addition, since the semiconductor disk storage device 1 does not include mechanical parts such as a motor, the power consumption thereof is lower. Besides, the semiconductor disk storage device 1 exhibits a resistance to impacts concerning vibrations etc. Moreover, owing to a high reliability, the semiconductor disk storage device 1 does not require any ECC.
The use of the flash memory as the storage medium is based on the following advantages: Since the flash memory is nonvolatile, it holds data even when the power supply is turned off, and it need not be backed up by a battery unlike an SRAM or DRAM. Further, since the flash memory is structurally simple compared with an EEPROM, it can have its storage capacity easily enlarged, and it is suited to mass production and can be fabricated inexpensively.
In the present invention, the flash memory of a storage device may well be divided into a plurality of areas including a plurality of data memory areas which store data therein and which are provided in correspondence with the divisional areas, a plurality of substitutive memory areas which substitute for the data memory areas having undergone errors and which are provided in correspondence with the divisional areas, a plurality of error memory areas which store the error information of the data memory areas therein and which are provided in correspondence with the divisional areas, and an initialize information area which stores the start addresses and storage capacities of the three sorts of memory areas therein. According to this expedient, in a case where the data storing capacity of the storage device is to be enlarged by additionally providing one or more flash memory elements, it can be enlarged by adding the three sorts of memory areas anew, without altering the contents of the error memory areas and the data memory areas stored before. The information of the added flash memory element or elements may be stored in the initialize information area.
Besides, in the present invention, the error memory areas may well also retain the error information of the substitutive memory areas having undergone errors. This expedient makes it possible to remedy, not only the errors of the data memory areas, but also the errors which have developed in the substitutive memory areas having once substituted for the data memory areas. The substitutive memory areas having undergone the errors may be replaced in the same manner as in the case where the errors have developed in the data memory areas. The replacements of the substitutive memory areas can extend the service life of the storage device.
Further, in the present invention, the storage capacity of the substitutive memory areas may be afforded by predetermined ones of the data memory areas. As the predetermined areas, areas which are rewritten most frequently may be selected. Then, the service life of the storage device can be rendered much longer with a small number of substitutive areas.
As set forth above, the present invention has the effect that the service life of a semiconductor disk storage device employing a flash memory as its storage medium can be extended.
Now, the third embodiment of the present invention will be described with reference to
First, the operation of a flash memory will be explained with reference to
Next, the system architecture and operation of the third embodiment of the storage device employing the flash memory will be explained with reference to
In operation, when an access request for reading data is received from a system (client system) which issues access requests to the system of this embodiment, the processor 23 refers to the logical sector table 25 to deduce a physical sector in which the data of a pertinent logical sector is stored. Subsequently, the processor 23 accesses the physical sector and transmits the requested data to the client system.
The processing of the processor 23 which complies with a request for writing data as received from the client system, will be explained with reference to the flow chart of
Incidentally, at the step (a), the decision on the status of the sector may well be recorded in the status table 28. The status of the sector can also be decided in view of the physical sector table 26. This status can be easily checked in such a way that all bits are set at H (high level) or L (low level) for an unwritten sector in the physical sector table 26.
Next, the erase management routine mentioned above will be explained with reference to
Thereafter, the erase management routine returns to the main routine. Incidentally, the sector selected as having the smallest number of erasures is erased once more, so that the corresponding number of erasures counter of the erase management table 27 needs to be incremented.
In addition, when the replacement flags of all the sectors have been raised, they are cleared. Alternatively, the logical decision levels of the replacement flags are inverted. That is, the replacements having been decided with the level “1” shall be decided with the level “0” thenceforth.
Besides, the prescribed number of erasures at the step (b) in
Owing to the erase management routine, when the data of limited blocks have been frequently erased, they are replaced with the data of blocks exhibiting smaller numbers of erasures, whereby the data of the sectors erased less frequently are stored in the blocks exhibiting larger numbers of erasure's, so that the numbers of erasures can be uniformalized. This expedient is considered very effective for the stored data of ordinary auxiliary storages. By way of example, although data are not rewritten at all in an area in which an operation system program is stored, data are frequently rewritten in areas in which the graphic data and text data to serve as the data of application programs are stored. Therefore, unless the numbers of erasures are uniformalized, the memory of the system program area does not degrade at all due to an incremented number of erasures because no data changes, whereas the memories of the other data areas are frequently erased in limited memory spaces and rapidly increase the numbers of erasures. Thus, it can be said that the erase management routine is especially effective when the number of the usable areas is small.
The third embodiment operates as stated above. This embodiment brings forth the following effects: Since the processor 23 is mounted, fine controls can be performed in accordance with the contents of the program memory 24. Moreover, the speed of a data writing operation is heightened owing to the write buffer 29, and the recording of the statuses of individual sectors is extended owing to the status table 28. Besides, since the service life of the flash memory is prolonged, the optimum file administration in which the numbers of erasures are managed is realized.
Now, the fourth embodiment of the present invention will be described with reference to
First, the chip of the flash memory in this embodiment and a method of using this chip will be explained in conjunction with
This embodiment is applied to the memory chip in which the file data are stored in sector unit, but in compliance with a request for rewriting the file data of a certain sector 52, also the other sectors of the erase block 53 are simultaneously erased.
The operation of the fourth embodiment will be explained below. A read access is processed by referring to the logical sector table 96 and the physical sector table 45 in the same manner as in the third embodiment.
On the other hand, a write access is processed as illustrated in
Next, the arrangement routine will be explained. This routine is an operation routine which is executed when the block pointed to by the write pointer has had the data already written into all its sectors and is therefore unwritable. The reason why the arrangement routine is required, is as follows: According to the data writing method explained above, the data of the same file to be rewritten is written into a physical sector different from the physical sector in which the data is stored. That is, the stored data becomes unnecessary before being rewritten, but it is kept stored in the memory and is to be erased. However, in a case where the data is erased each time it becomes unnecessary, the flash memory which has a limited in the number of erase operations would have its service life shortened. Therefore, the arrangement routine is required. This arrangement routine is executed when the block has become full of the written data.
A concrete method of arrangement proceeds in accordance with the flow chart of
Next, the erase management routine will be explained in conjunction with the flow chart shown in
Owing to the erase management routine, in the same manner as in the third embodiment, when the data of limited blocks have been frequently erased, they are replaced with the data of blocks exhibiting smaller numbers of erasures, whereby the numbers of erasures of the blocks can be uniformalized.
The fourth embodiment is operated as explained above. This embodiment brings forth the effect that, when the erase block is too large as the unit of the data writing sector, it can be divided and used efficiently.
Incidentally, although the write buffer and the arrangement buffer are separate in the illustrated embodiment, they may well be identical.
Now, the fifth embodiment of the present invention will be described with reference to
The hardware architecture of the fourth embodiment is as illustrated in
The number of erasures counter of the erase management table 101 corresponding to the superblock 91 in which an erased sector is included, is incremented at the first step (step (a)). Whether or not the number of erasures of the superblock 91 has reached a prescribed value, is subsequently decided (step (b)). When the prescribed number of times has not been reached, the, erase management routine returns to the main routine. On the other hand, when the prescribed number of erasures has been reached, the numbers of erasures of all the superblocks 91 are examined to seek out the superblock 91 which has the smallest number of erasures and whose data has not been replaced (step (c)). Subsequently, the data of the two superblocks 91 are replaced with each other (step (d)). Further, the replacement flags of both the superblocks 91 are raised (step (e)), and the contents of the relevant tables are rerecorded (step (f)).
The merits of this embodiment are as stated below. In a memory wherein data can be erased in sector unit, erase operations are managed in plural-sector unit, thereby simplifying the erase management. Especially in rewriting a file of large storage capacity, there are attained the effects that a wait time can be shortened and that the storage capacity of the erase management table 101 can be reduced. Accordingly, the fifth embodiment is suited to storage devices of large capacities in which it is difficult to manage the erase operations in sector units.
Now, the tables such as the logical sector table and the physical sector table, which are the constituents of the embodiments described before, will be explained in more detail. The flash memory is a nonvolatile memory. It is accordingly natural that data in the flash memory are not lost even when the system of the present invention has its power supply cut off while it is not operating. However, when the contents of the tables are lost, the data saved in the flash memory become incomprehensible and meaningless data because the corresponding relations of the data to sectors becomes unknown. Therefore, the information stored in the tables also needs to be obtained after the cutoff of the power supply. It is not necessary, however, to save all the information in the tables. The information of the logical sector table, for example, can be easily originated from the information of the physical sector table. The converse is also possible. That is, the information of either of the tables may be saved.
Therefore, the physical sector table is stored in an electrically erasable and programmable read-only memory (EEPROM) which is nonvolatile, while the logical sector table is originated from the physical sector table by the processor at the start of the system at which the power supply is initiated. Thus, a volatile memory can be employed as the logical sector table.
Likewise, the number-of-written-sectors table for respective blocks can be originated from the physical sector table. It is therefore originated in a volatile memory at the start of the system.
The tables mentioned above can also be developed in the main memory of the main system. The other tables are the erase management table and the status table, which cannot originate from any table. The erase management table is stored in an EEPROM because the information thereof ought not to be lost. The status table is obtained when data is written or erased once more, but this table should be stored in an EEPROM in order to avoid repetitive trouble. For the purpose of saving a memory capacity, however, it can be stored also in a volatile memory.
Regarding the storage media of the tables, the number of chips can also be reduced by storing the tables in an identical memory chip. By way of example, since both the physical sector table and the number of erasures table ought to be stored in nohvolatile memories, they are stored in the identical EEPROM chip. Then, only one EEPROM chip is necessary.
Besides, when the processor is implemented by a one-chip microcomputer, a table of comparatively small storage capacity, such as the number-of-written-sectors table, is stored in a RAM core which is built into the one-chip microcomputer.
The architecture of the sixth embodiment in which the above measures concerning the tables are collectively taken, is illustrated in
The number-of-written-sectors table is stored in the RAM core 112, while control programs for the microcomputer proper are stored in the ROM core 113. The physical sector table and the erase management table are stored in the EEPROM 114, while the logical sector table is stored in the RAM 115. In addition, the empty area of the RAM 115 is used as the arrangement buffer (51 in
In this manner, according to the sixth embodiment, the tables and the buffers are collectively formed in accordance with the features of the storage media, whereby the number of chips can be reduced.
Further, embodiments concerning the configuration of the flash memory itself are illustrated in
The embodiment in
This expedient equalizes the service lives of the data area 131 and the table area 132. That is, it can avoid a situation where the block becomes unusable because the table area 132 is broken in spite of the usable status of the data area 131. Such a tendency intensifies more when the data area 131 and the table area 132 are closer to each other. Moreover, since the tables are formed for every erase block 131, address lines can be shared with ease.
Incidentally, the acceptance means may well receive information on modes so as to select the information of the tables.
The embodiment in
The embodiment in
When a write access is received, the first transfer means writes data to-be-written into the buffer area 142. Besides, when an address is input, the second transfer means transfers a plurality of items of data to the corresponding data area 141 at one stroke so as to be written thereinto. With such a memory, the write buffer which is externally mounted for heightening the speed of a write operation can be omitted. In a read operation, a plurality of items of data can be transferred contrariwise from the data area 141 to the buffer area 142 at one stroke by inputting an address. Also, a read access is simplified.
In this case, the memory becomes more convenient in such a way that the buffer area 142 is constructed as a serial access memory, making it unnecessary to apply successive addresses as inputs. Then, when the clock inputs are applied, the internal address counter 143 counts up, whereby the successive data areas 141 can be accessed to deliver the stored data.
It is most effective to construct the buffer area 142 in sector units. This buffer area is not restricted to one sector unit, but it can include a plurality of sector units in order to enhance the buffering effect thereof. By way of example, when one sector is an erase block unit, the buffer area 142 whose capacity corresponds to one sector can write or read the data of one sector at a time. The buffer area 142 whose capacity corresponds to a plurality of sectors can accept accesses for writing the data of the plurality of sectors, and can prepare the data of the plurality of sectors to-be-read-out. Further, this buffer area 142 is effective to omit the arrangement buffer 51 which is externally mounted.
The third embodiment et seq. of the present invention bring forth effects as stated below.
In the data management scheme of an auxiliary storage employing a flash memory which is limited in the number of erase operations, even when specified logical sector addresses are frequently rewritten, the same physical storage areas are not used. Besides, when the number of erasures has increased in a certain area, the data of the area is replaced with that of an area whose number of erasures is small, to thereby uniformalizing increases in the numbers of erasures. Therefore, the service life of the whole storage system is extended.
In addition, the number of data memory elements may correspond to an actual capacity for storing the file data of the system, and no redundant memory element is required.
Further, in a case where the memory is formed, not only with data areas, but also with an information holding area and a data buffer area, the numbers of elements of peripheral circuits can be decreased to reduce the size of the whole system.
Many different embodiments of the present invention may be constructed without departing from the spirit and scope of the invention. It should be understood that the present invention is not limited to the specific embodiments described in this specification. To the contrary, the present invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US4530054||Mar 3, 1982||Jul 16, 1985||Sperry Corporation||Processor-addressable timestamp for indicating oldest written-to cache entry not copied back to bulk memory|
|US4563752||Jun 6, 1983||Jan 7, 1986||U.S. Philips Corporation||Series/parallel/series shift register memory comprising redundant parallel-connected storage registers, and display apparatus comprising a picture memory thus organized|
|US4841482 *||Feb 17, 1988||Jun 20, 1989||Intel Corporation||Leakage verification for flash EPROM|
|US4899272||Oct 23, 1987||Feb 6, 1990||Chips & Technologies, Inc.||Addressing multiple types of memory devices|
|US4922456||Apr 29, 1988||May 1, 1990||Scientific-Atlanta, Inc.||Method of reducing wearout in a non-volatile memory with double buffer|
|US4924375||Oct 23, 1987||May 8, 1990||Chips And Technologies, Inc.||Page interleaved memory access|
|US5043940||Jul 17, 1989||Aug 27, 1991||Eliyahou Harari||Flash EEPROM memory systems having multistate storage cells|
|US5053990||Feb 17, 1988||Oct 1, 1991||Intel Corporation||Program/erase selection for flash memory|
|US5065364||Sep 15, 1989||Nov 12, 1991||Intel Corporation||Apparatus for providing block erasing in a flash EPROM|
|US5092463 *||Feb 7, 1991||Mar 3, 1992||Dees Kent L||Tool storage container|
|US5095344 *||Jun 8, 1988||Mar 10, 1992||Eliyahou Harari||Highly compact eprom and flash eeprom devices|
|US5245572||Jul 30, 1991||Sep 14, 1993||Intel Corporation||Floating gate nonvolatile memory with reading while writing capability|
|US5263003||Nov 12, 1991||Nov 16, 1993||Allen-Bradley Company, Inc.||Flash memory circuit and method of operation|
|US5267218||Mar 31, 1992||Nov 30, 1993||Intel Corporation||Nonvolatile memory card with a single power supply input|
|US5268870||Aug 6, 1990||Dec 7, 1993||Eliyahou Harari||Flash EEPROM system and intelligent programming and erasing methods therefor|
|US5280447||Jun 19, 1992||Jan 18, 1994||Intel Corporation||Floating gate nonvolatile memory with configurable erasure blocks|
|US5295255||Feb 22, 1991||Mar 15, 1994||Electronic Professional Services, Inc.||Method and apparatus for programming a solid state processor with overleaved array memory modules|
|US5297148||Oct 20, 1992||Mar 22, 1994||Sundisk Corporation||Flash eeprom system|
|US5341339||Nov 1, 1993||Aug 23, 1994||Intel Corporation||Method for wear leveling in a flash EEPROM memory|
|US5341489||Apr 14, 1992||Aug 23, 1994||Eastman Kodak Company||Memory card with programmable interleaving|
|US5357473||Oct 6, 1993||Oct 18, 1994||Mitsubishi Denki Kabushiki Kaisha||Semiconductor storage system including defective bit replacement|
|US5359569||Oct 29, 1992||Oct 25, 1994||Hitachi Ltd.||Semiconductor memory|
|US5369616||Mar 7, 1994||Nov 29, 1994||Intel Corporation||Method for assuring that an erase process for a memory array has been properly completed|
|US5418752||Oct 20, 1992||May 23, 1995||Sundisk Corporation||Flash EEPROM system with erase sector select|
|US5524230 *||Mar 27, 1995||Jun 4, 1996||International Business Machines Incorporated||External information storage system with a semiconductor memory|
|US5530673 *||Apr 8, 1994||Jun 25, 1996||Hitachi, Ltd.||Flash memory control method and information processing system therewith|
|US5530828||Jun 22, 1993||Jun 25, 1996||Hitachi, Ltd.||Semiconductor storage device including a controller for continuously writing data to and erasing data from a plurality of flash memories|
|US5535328||Feb 23, 1995||Jul 9, 1996||Sandisk Corporation||Non-volatile memory system card with flash erasable sectors of EEprom cells including a mechanism for substituting defective cells|
|US5572466||Oct 6, 1993||Nov 5, 1996||Kabushiki Kaisha Toshiba||Flash memory chips|
|US5630093||Apr 19, 1996||May 13, 1997||Intel Corporation||Disk emulation for a non-volatile semiconductor memory utilizing a mapping table|
|US5644539 *||Nov 25, 1992||Jul 1, 1997||Hitachi, Ltd.||Storage device employing a flash memory|
|US5661800||Jun 28, 1996||Aug 26, 1997||Fujitsu, Limited||Method and manufacture for preventing unauthorized use by judging the corresponding relationship between logical and physical addresses|
|US5663901||Sep 12, 1995||Sep 2, 1997||Sandisk Corporation||Computer memory cards using flash EEPROM integrated circuit chips and memory-controller systems|
|US5671229||May 25, 1994||Sep 23, 1997||Sandisk Corporation||Flash eeprom system with defect handling|
|US5673383||Jun 25, 1996||Sep 30, 1997||Kabushiki Kaisha Toshiba||Storage system with a flash memory module|
|US5689676||Nov 18, 1996||Nov 18, 1997||Sony Corporation||Sequential EEPROM writing apparatus which sequentially and repetitively replaces a head position pointer with a last position pointer|
|US5696917||Jun 3, 1994||Dec 9, 1997||Intel Corporation||Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory|
|US5696929||Oct 3, 1995||Dec 9, 1997||Intel Corporation||Flash EEPROM main memory in a computer system|
|US5719808||Mar 21, 1995||Feb 17, 1998||Sandisk Corporation||Flash EEPROM system|
|US5724285||Sep 13, 1996||Mar 3, 1998||Mitsubishi Denki Kabushiki Kaisha||Flash memory PC card capable of refreshing data a predetermined time after the PC card is removed from a host|
|US5734887||Sep 29, 1995||Mar 31, 1998||International Business Machines Corporation||Method and apparatus for logical data access to a physical relational database|
|US5737764||Jun 7, 1995||Apr 7, 1998||Texas Instruments Incorporated||Generation of memory column addresses using memory array type bits in a control register of a computer system|
|US5742934||Mar 11, 1996||Apr 21, 1998||Mitsubishi Denki Kabushiki Kaisha||Flash solid state disk card with selective use of an address conversion table depending on logical and physical sector numbers|
|US5774396||Dec 9, 1996||Jun 30, 1998||Aplus Integrated Circuits, Inc.||Flash memory with row redundancy|
|US5778425||Jun 7, 1995||Jul 7, 1998||Texas Instruments Incorporated||Electronic system having a first level write through cache memory and smaller second-level write-back cache memory and method of operating the same|
|US5802551||Aug 19, 1994||Sep 1, 1998||Fujitsu Limited||Method and apparatus for controlling the writing and erasing of information in a memory device|
|US5805854||Jun 7, 1995||Sep 8, 1998||Texas Instruments Incorporated||System and process for memory column address organization in a computer system|
|US5812814||Feb 24, 1994||Sep 22, 1998||Kabushiki Kaisha Toshiba||Alternative flash EEPROM semiconductor memory system|
|US5862083||Apr 30, 1996||Jan 19, 1999||Hitachi, Ltd.||Information processing system|
|US5943692||Apr 30, 1997||Aug 24, 1999||International Business Machines Corporation||Mobile client computer system with flash memory management utilizing a virtual address map and variable length data|
|US5953513||Jul 24, 1995||Sep 14, 1999||Hitachi, Ltd.||Recording and reproducing device for recording and reproducing information from different kinds of storage media having different sector formats|
|US5963983||Apr 15, 1997||Oct 5, 1999||International Business Machines Corporation||Method and apparatus for dynamically creating conversion tables to access a semiconductor memory device|
|US5983312||Aug 18, 1997||Nov 9, 1999||Fujitsu Limited||Simultaneously writing to and erasing two commonly numbered sectors|
|US6000006||Aug 25, 1997||Dec 7, 1999||Bit Microsystems, Inc.||Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage|
|US6078520||Jul 21, 1999||Jun 20, 2000||Hitachi, Ltd.||Flash memory control method and information processing system therewith|
|US6081447||Mar 5, 1999||Jun 27, 2000||Western Digital Corporation||Wear leveling techniques for flash EEPROM systems|
|US6125424||Jan 22, 1998||Sep 26, 2000||Fujitsu Limited||Method of writing, erasing, and controlling memory and memory device having erasing and moving components|
|US6130837 *||Jan 13, 1997||Oct 10, 2000||Hitachi, Ltd.||Storage device employing a flash memory|
|US6131139||Jan 27, 1997||Oct 10, 2000||Tokyo Electron Limited||Apparatus and method of simultaneously reading and writing data in a semiconductor device having a plurality of flash memories|
|US6230233||Sep 13, 1991||May 8, 2001||Sandisk Corporation||Wear leveling techniques for flash EEPROM systems|
|US6266792||Oct 26, 1999||Jul 24, 2001||Hitachi, Ltd.||Semiconductor memory, memory device, and memory card|
|US6341085||Sep 12, 2000||Jan 22, 2002||Hitachi, Ltd.||Storage device employing a flash memory|
|US6347051||May 30, 2001||Feb 12, 2002||Hitachi, Ltd.||Storage device employing a flash memory|
|US6374324||Mar 18, 1999||Apr 16, 2002||Hyundai Electronics Industries Co., Ltd.||Flash memory array access method and device|
|US6430650||Jun 17, 1996||Aug 6, 2002||Mitsubishi Denki Kabushiki Kaisha||Semiconductor storage device for group management of data sectors|
|US6567334||Jan 16, 2002||May 20, 2003||Hitachi, Ltd.||Storage device employing a flash memory|
|US6788609||Apr 9, 2003||Sep 7, 2004||Renesas Technology Corp.||Storage device employing a flash memory|
|US6925012 *||May 19, 2004||Aug 2, 2005||Renesas Technology Corp.||Storage device employing a flash memory|
|US7002851 *||Mar 22, 2005||Feb 21, 2006||Renesas Technology Corp.||Storage device employing a flash memory|
|DE2840305A1||Sep 15, 1978||Mar 27, 1980||Siemens Ag||Permanent store programming before storage of binary value - applies programming signal of specified duration to storage location and uses test interval to control duration length|
|DE3200872A1||Jan 14, 1982||Jul 21, 1983||Sartorius Gmbh||Electronic balance|
|EP0392895A2||Mar 30, 1990||Oct 17, 1990||Sundisk Corporation||Flash EEprom system|
|EP0492106A1||Nov 12, 1991||Jul 1, 1992||International Business Machines Corporation||Endurance management for solid state files|
|EP0522780A2||Jul 1, 1992||Jan 13, 1993||International Business Machines Corporation||Control method for a computer memory device|
|EP0569040A2||May 10, 1993||Nov 10, 1993||Kabushiki Kaisha Toshiba||Memory card device|
|EP0615193A1||Nov 30, 1992||Sep 14, 1994||Kabushiki Kaisha Toshiba||Memory card device|
|GB2251323A||Title not available|
|GB2251324A||Title not available|
|JP2001243110A||Title not available|
|JPH0325798A||Title not available|
|JPH0330034A||Title not available|
|JPH0433029A||Title not available|
|JPH0457295A||Title not available|
|JPH0527924A||Title not available|
|JPH0528039A||Title not available|
|JPH01235075A||Title not available|
|JPH01251372A||Title not available|
|JPH01292455A||Title not available|
|JPH02189790A||Title not available|
|JPH02289997A||Title not available|
|JPH02292798A||Title not available|
|JPH03127116A||Title not available|
|JPH03252993A||Title not available|
|JPH03283094A||Title not available|
|JPH04123243A||Title not available|
|JPH04243096A||Title not available|
|JPH05204561A||Title not available|
|JPH05241741A||Title not available|
|JPH05324000A||Title not available|
|JPH09161490A||Title not available|
|JPH09282111A||Title not available|
|JPS6236799A||Title not available|
|WO1992018928A1||Apr 14, 1992||Oct 29, 1992||Bull S.A.||Coupling circuit, use thereof in a card, and method|
|WO1993011491A1||Nov 30, 1992||Jun 10, 1993||Kabushiki Kaisha Toshiba||Memory card device|
|1||Communications of the Association for Computing Machinery, "Asymmetric Memory Hierarchies", vol. 16, No. 4, Apr. 1973, pp. 213-222.|
|2||Fujio Masuoka , "256K bit EEPROM going as far as substituting with the ultraviolet rays erasing type EPROM-just providing erasing gates with the EPROM", Nikkei Electronics, 1985, Jul. 29, No. 374, pp. 195-209; Nikkei-McGraw-Hill.|
|3||Patent Abstracts of Japan, vol. 10, No. 30, Feb. 5, 1986. Computer Technology Review, "Flash Memory for Top Speeds in Mobile Computing", vol. 12, No. 7, Jun. 1992, pp. 36-37.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7715243||Dec 17, 2007||May 11, 2010||S4, Inc.||Storage device employing a flash memory|
|US8031536||Mar 29, 2010||Oct 4, 2011||S4, Inc.||Storage device employing a flash memory|
|US8209471||Feb 10, 2009||Jun 26, 2012||Kabushiki Kaisha Toshiba||Memory system|
|US8514642||Jan 13, 2011||Aug 20, 2013||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor memory device|
|US8661191||Jan 26, 2012||Feb 25, 2014||Kabushiki Kaisha Toshiba||Memory system|
|US20110176377 *||Jan 13, 2011||Jul 21, 2011||Semiconductor Energy Laboratory Co., Ltd.||Semiconductor memory device|
|U.S. Classification||365/230.01, 711/152, 711/103, 365/185.33, 711/202, 711/160, 711/221, 365/185.11|
|International Classification||G06F12/02, G06F3/06, G11C29/00, G11C16/10, G11C8/00|
|Cooperative Classification||G06F3/0601, G06F12/0246, G06F2212/2022, G06F2003/0694, G06F3/0679, G11C29/765, G11C16/102, G11C16/349, G06F3/0616, G06F3/064, G06F3/0619, G06F3/0659|
|European Classification||G11C29/765, G06F3/06A6L2F, G06F3/06A2R2, G06F3/06A4F2, G11C16/34W, G06F3/06A2R6, G06F3/06A4T6, G06F3/06A, G11C16/10E|
|Aug 30, 2007||AS||Assignment|
Owner name: SOLID STATE STORAGE SOLUTIONS LLC, WISCONSIN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:RENESAS TECHNOLOGY CORP.;REEL/FRAME:019773/0294
Effective date: 20070808
|Apr 21, 2010||AS||Assignment|
Owner name: SOLID STATE STORAGE SOLUTIONS, INC.,TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:SOLID STATE STORAGE SOLUTIONS LLC;REEL/FRAME:024265/0084
Effective date: 20090930
Owner name: SOLID STATE STORAGE SOLUTIONS, INC., TEXAS
Free format text: CHANGE OF NAME;ASSIGNOR:SOLID STATE STORAGE SOLUTIONS LLC;REEL/FRAME:024265/0084
Effective date: 20090930
|May 14, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Jun 26, 2014||FPAY||Fee payment|
Year of fee payment: 8
|Dec 12, 2016||AS||Assignment|
Owner name: ACACIA RESEARCH GROUP LLC, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SOLID STATE STORAGE SOLUTIONS, INC.;REEL/FRAME:040886/0619
Effective date: 20151228
|Dec 22, 2016||AS||Assignment|
Owner name: EMERGENCE MEMORY SOLUTIONS LLC, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ACACIA RESEARCH GROUP LLC;REEL/FRAME:041176/0010
Effective date: 20161212