|Publication number||US7161831 B2|
|Application number||US 11/150,799|
|Publication date||Jan 9, 2007|
|Filing date||Jun 10, 2005|
|Priority date||Jun 10, 2005|
|Also published as||CN1877741A, CN1877741B, US20060279987|
|Publication number||11150799, 150799, US 7161831 B2, US 7161831B2, US-B2-7161831, US7161831 B2, US7161831B2|
|Original Assignee||Macronix International Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (9), Non-Patent Citations (1), Classifications (7), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
There are many memory devices that have different voltage threshold (Vt) states by storing different amounts of charges in their memory cells. A two-sided memory device cell has a transistor with two sides (i.e., the drain or source side of a transistor) separated by a channel in the substrate for storing a charge as shown in FIG. 1 of U.S. Pat. No. 5,768,192 (Eitan). However, the voltage threshold (Vt) state of one side of the memory cell could interact with the other side of the memory cell during an operation. This interaction between the sides of the memory cell makes it difficult to analyze or to predict the Vt variation during the memory device operation.
Prior art, such as U.S. Pat. No. 6,320,784 (Muralidhar et al.) at column 2, lines 32–36, discusses a method for programming nanocrystals. However, no threshold state interaction analysis is discussed for this device for each side of the memory cell. In addition, U.S. Pat. No. 5,768,192 (Eitan) at column 2, lines 41–65 and column 3, line 16 through column 4, line 3, discusses the operation of NROM cells. However, two-sided voltage threshold analysis is not presented to show the interaction from one side of the memory cell to the other side of the memory cell. Furthermore, a paper published in the International Electron Devices Meeting Digest, 2002, pages 931–934 (Yeh et al.) discusses the operation of PHINES cells and the threshold voltage for each operating condition, but does not discuss an analysis method of the two-sided voltage threshold interactions for its memory cell.
The present invention provides a method of analyzing an interaction of threshold states of a multiple-bit memory cell associated with a memory device by plotting each threshold state for each side of the memory cell on a coordinate system. The memory device has a plurality of memory cells comprising a plurality of threshold states. The coordinate system comprises a plurality of axes with one axis associated to a threshold state. Each axis is associated to a side of a multiple-bit memory cell, thereby allowing an analysis of the interaction between the threshold states of different sides of the memory cell.
The traces plotted on the coordinate system show the threshold states of the multiple-bit memory cell for the sides on the same plot for the device under a particular operation condition. An operation (e.g., programming, reading, or erasing) is initiated on one side of the memory cell from a start point to a target point. From this operation, a plot is created of the threshold states for each side of the memory cell. Since the coordinate system illustrates the threshold states for each side of the multiple-bit memory cell together, the interaction of the threshold states of sides of the memory cell to one another can be analyzed.
The leaf plot of the present invention is an analysis method that is based on a coordinate system that uses a plurality of axes. The axes of the coordinate system can be separated from one another by any defined angle. Each axis is associated to each side's threshold state of a multiple-bit memory cell and the other axes are for the other side's threshold state of the memory cell. Every point in the coordinate system corresponds to one combinational memory state (e.g., a different threshold state combination for each point).
To create the leaf plot, an operation condition is initialized, wherein an operation can be any of the following: program (e.g., write), read, or erase operation, on the first side of the memory cell. Next, begin plotting the threshold state on the coordinate system from a start point (e.g., an erase state) to a target point of the first side of the memory cell. After completing the operation to the target point of the memory cell, next program a second side of the memory cell. Then plot its threshold state on the coordinate system from the target point of the first side of the memory cell to a first target point of the second side of the memory cell.
The same leaf plot of
One embodiment of the present invention is programming (e.g., writing) a memory cell of a two-side memory device wherein a memory device is a flash memory device. By applying different target thresholds, fine grids can be defined on the leaf plot for the selected programming and reading conditions, as shown in
One preferred embodiment of the present invention, can use different programming and reading condition that results in different grids on a leaf plot.
A second preferred embodiment for the present invention is plotting the targets for an erase operation of a memory cell for a memory device. Similar to programming, the erase operation results in a different grid for a leaf plot as shown in
A third preferred embodiment for the present invention is plotting the threshold target states for a reading operation of a device. A different leaf plot exists for different device structures and for different reading and programming conditions. For example,
A fourth preferred embodiment of the present invention is for programming the PHINES cell. The programming voltage threshold for the cell can be either upwards or downwards of the voltage threshold levels. When programming is initiated, it can start either at a high or low voltage threshold level, which is a characteristic of a device. For example, an erase state of a PHINES cell is at a high voltage threshold and when programming this cell, it starts at its high voltage threshold level and programs to a lower voltage threshold level. To complete the operation, a PHINES memory cell requires using injection of band-to-band-tunneling hot holes (BTBTHH) to program to the storage layer. This programming condition decreases the voltage threshold level from the high state to a lower voltage threshold state.
The leaf plot provides a method to analyze or predict the voltage threshold states under different device operations, regardless of whether the operation condition is a program (e.g., write), an erase or a read operation. The leaf plot and its method of analysis can be applied to all physically multiple-bit-per-cell devices such as NROM, nanocrystal memory, programming by hot-hole injection nitride electron storage (PHINES), asymmetric two-side program one-side read memory (ATPOR), two-side split gate memory, two-side space storage memory, and other devices that have multiple physical storage sites.
The method of analyzing a memory cell of a memory device by creating a leaf plot, makes it easy to understand the device operation window. In addition, it aids to analyze the device under different operating conditions, and predict the memory state of the device under complex operating algorithms.
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|1||(Yeh, et al.), 4 pages (International Electron Devices Meeting Digest, 2002, pp. 931-934 PUB Date: Dec. 8-11, 2002.|
|U.S. Classification||365/185.03, 365/185.01, 365/185.24|
|International Classification||G11C11/34, G11C16/04|
|Aug 8, 2005||AS||Assignment|
Owner name: MACRONIX INTERNATIONAL CO., LTD., TAIWAN
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, MING-HSIU;REEL/FRAME:016364/0374
Effective date: 20050614
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