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Publication numberUS7166528 B2
Publication typeGrant
Application numberUS 10/683,937
Publication dateJan 23, 2007
Filing dateOct 10, 2003
Priority dateOct 10, 2003
Fee statusPaid
Also published asCN1875461A, CN100468625C, CN101483136A, CN101483136B, EP1680808A1, US7517775, US7737007, US20050079691, US20060234488, US20090011578, WO2005038890A1
Publication number10683937, 683937, US 7166528 B2, US 7166528B2, US-B2-7166528, US7166528 B2, US7166528B2
InventorsYihwan Kim, Arkadii V. Samoilov
Original AssigneeApplied Materials, Inc.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Methods of selective deposition of heavily doped epitaxial SiGe
US 7166528 B2
Abstract
The invention generally teaches a method for depositing a silicon film or silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in the range from about 600° C. to about 900° C. while maintaining a pressure in the range from about 0.1 Torr to about 200 Torr. A deposition gas is provided to the process chamber and includes SiH4, an optional germanium source gas, an etchant, a carrier gas and optionally at least one dopant gas. The silicon film or the silicon germanium film is selectively and epitaxially grown on the substrate. One embodiment teaches a method for depositing a silicon-containing film with an inert gas as the carrier gas. Methods may include the fabrication of electronic devices utilizing selective silicon germanium epitaxial films.
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Claims(45)
1. A method for depositing a silicon germanium film on a substrate comprising:
providing a substrate within a process chamber;
heating the substrate to a temperature within a range from about 500° C. to about 900° C.;
exposing the substrate to a first deposition gas comprising silane, germanium, a carbon source, hydrogen chloride, a carrier gas, and at least one dopant gas to epitaxially and selectively deposit a first silicon germanium material on the substrate, wherein the first silicon germanium material contains a dopant concentration of about 2.5×1021 atoms/cm3; and
exposing the substrate to a second deposition gas comprising dichlorosilane and a germanium source to epitaxially and selectively deposit a second silicon germanium material on the substrate.
2. The method of claim 1, wherein the at least one dopant gas is a boron containing compound selected from the group consisting of borane, diborane, triborane, trimethylborane, triethylborane, and derivatives thereof.
3. The method of claim 2, wherein the first silicon germanium material contains a boron concentration of about 2.5×1021 atoms/cm3.
4. The method of claim 3, wherein the carbon source is an organosilane.
5. The method of claim 4, wherein the carbon source is methylsilane.
6. The method of claim 1, wherein the at least one dopant gas includes an arsenic containing compound or a phosphorus containing compound.
7. The method of claim 1, wherein the carrier gas is selected from the group consisting of hydrogen, argon, nitrogen, helium, and combinations thereof.
8. The method of claim 7, wherein the first deposition gas further comprises dichlorosilane.
9. The method of claim 7, wherein the temperature is within a range from about 600° C. to about 750° C. and the process chamber is at a pressure within a range from about 0.1 Torr to about 200 Torr.
10. The method of claim 7, wherein the silicon germanium film has a thickness within a range from about 100 Å to about 3,000 Å.
11. The method of claim 10, wherein the silicon germanium film is deposited within a device used for CMOS, Bipolar, or BiCMOS application.
12. The method of claim 11, wherein the silicon germanium film is deposited during a fabrication step selected from the group consisting of contact plug, source/drain extension, elevated source/drain, and bipolar transistor.
13. The method of claim 1, wherein a silicon-containing material is deposited on the substrate before the first silicon germanium material.
14. The method of claim 13, wherein the silicon-containing material is deposited by a deposition process comprising dichlorosilane.
15. A selective epitaxial method for depositing a silicon germanium film on a substrate comprising:
placing a substrate within a process chamber;
heating the substrate to a temperature within a range from about 500° C. to about 900° C.; and
exposing the substrate to a deposition gas comprising silane, a germanium source, a carbon source, an etchant source, a carrier gas, and at least one dopant gas to epitaxially and selectively form a silicon germanium material containing a dopant concentration of about 2.5×1021 atoms/cm3.
16. The method of claim 15, wherein the germanium source is selected from the group consisting of germane, digermane, trigermane, tetragermane, and derivatives thereof.
17. The method of claim 16, wherein the carrier gas is selected from the group consisting of hydrogen, argon, nitrogen, helium, and combinations thereof.
18. The method of claim 17, wherein the temperature is within a range from about 600° C. to about 750° C. and the process chamber is at a pressure within a range from about 0.1 Torr to about 200 Torr.
19. The method of claim 18, wherein the etchant source is selected from the group consisting of hydrogen chloride, tetrachlorosilane, tetrachloromethane, dichloromethane, chlorine, derivatives thereof, and combinations thereof.
20. The method of claim 15, wherein the at least one dopant gas is a boron containing compound selected from the group consisting of borane, diborane, triborane, trimethylborane, triethylborane, and derivatives thereof.
21. The method of claim 20, wherein the carbon source is an organosilane.
22. The method of claim 21, wherein the carbon source is methylsilane.
23. The method of claim 15, wherein the at least one dopant gas is selected from the group consisting of an arsenic containing compound and a phosphorus containing compound.
24. The method of claim 15, wherein the deposition gas further comprises dichlorosilane.
25. The method of claim 18, wherein the silicon germanium film has a thickness within a range from about 100 Å to about 3,000 Å.
26. The method of claim 25, wherein the silicon germanium film is deposited within a device used for CMOS, Bipolar, or BiCMOS application.
27. The method of claim 26, wherein the silicon germanium film is deposited during a fabrication step selected from the group consisting of contact plug, source/drain extension, elevated source/drain, and bipolar transistor.
28. The method of claim 15, wherein the silicon germanium material is deposited having a first thickness, thereafter, the silane is replaced by dichlorosilane, and a second silicon germanium material is epitaxially and selectively deposited having a second thickness on the silicon germanium material.
29. The method of claim 15, wherein a silicon-containing material is deposited on the substrate before the silicon germanium material.
30. The method of claim 29, wherein the silicon-containing material is deposited by a deposition process comprising dichlorosilane.
31. A method for depositing a silicon germanium film on a substrate comprising:
placing a substrate within a process chamber;
heating the substrate to a temperature within a range from about 500° C. to about 900° C.; and
exposing the substrate to a deposition gas comprising a silicon-containing gas, a germanium source, a carbon source, hydrogen chloride, and a boron-containing dopant gas to epitaxially and selectively deposit a silicon germanium material on the substrate, wherein the silicon germanium material contains a boron concentration of about 2.5×1021 atoms/cm3.
32. A method for depositing a silicon germanium film on a substrate comprising:
placing a substrate within a process chamber;
exposing the substrate to a first deposition gas comprising silane, a first germanium source, a carbon source, hydrogen chloride, and a carrier gas to epitaxially deposit a first silicon germanium containing material having a first thickness on the substrate and containing a dopant concentration of about 2.5×1021 atoms/cm3; and
exposing the substrate to a second deposition gas comprising dichlorosilane and a second germanium source to epitaxially deposit a second silicon germanium containing material having a second thickness on the first silicon germanium containing material.
33. The method of claim 32, wherein the first silicon germanium containing material is selectively deposited on the substrate.
34. The method of claim 33, wherein the first deposition gas further comprises at least one dopant gas.
35. The method of claim 34, wherein the at least one dopant gas comprises an element selected from the group consisting boron, arsenic, phosphorus, and combinations thereof.
36. The method of claim 35, wherein the at least one dopant gas comprises a boron containing compound selected from the group consisting of borane, diborane, triborane, trimethylborane, triethylborane, and derivatives thereof.
37. The method of claim 36, wherein the carbon source is an organosilane.
38. The method of claim 37, wherein the carbon source is methylsilane.
39. The method of claim 33, wherein the second silicon germanium containing material is selectively deposited on the substrate.
40. The method of claim 39, wherein the second deposition gas further comprises hydrogen chloride and at least one dopant gas.
41. The method of claim 40, wherein the at least one dopant gas comprises an element selected from the group consisting boron, arsenic, phosphorus, and combinations thereof.
42. The method of claim 41, wherein the at least one dopant gas comprises a boron containing compound selected from the group consisting of borane, diborane, triborane, trimethylborane, triethylborane, and derivatives thereof.
43. The method of claim 33, wherein the first and second germanium sources are independently selected from the group consisting of germane, digermane, trigermane, tetragermane, and derivatives thereof.
44. The method of claim 43, wherein the first and second thicknesses are independently within a range from about 100 Å to about 3,000 Å.
45. The method of claim 44, wherein the substrate is heated to a first temperature during the exposure of the first deposition gas and to a second temperature during the exposure of the second deposition gas, wherein the first and second temperatures are independently a temperature within a range from about 500° C. to about 900° C.
Description
BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention generally relate to the field of semiconductor manufacturing processes and devices, more particular, to methods of depositing silicon-containing films forming semiconductor devices.

2. Description of the Related Art

As smaller transistors are manufactured, ultra shallow source/drain junctions are becoming more challenging to produce. According to the International Technology Roadmap for Semiconductors (ITRS), junction depth is required to be less than 30 nm for sub-100 nm CMOS (complementary metal-oxide semiconductor) devices. Conventional doping by implantation and annealing is less effective as the junction depth approaches 10 nm. Doping by implantation requires a post-annealing process in order to activate dopants and post-annealing causes enhanced dopant diffusion into layers.

Recently, heavily-doped (about >1019 atoms/cm3), selective SiGe epitaxy has become a useful material to deposit during formation of elevated source/drain and source/drain extension features. Source/drain extension features are manufactured by etching silicon to make a recessed source/drain feature and subsequently filling the etched surface with a selectively grown SiGe epilayer. Selective epitaxy permits near complete dopant activation with in-situ doping, so that the post annealing process is omitted. Therefore, junction depth can be defined accurately by silicon etching and selective epitaxy. On the other hand, the ultra shallow source/drain junction inevitably results in increased series resistance. Also, junction consumption during silicide formation increases the series resistance even further. In order to compensate for junction consumption, an elevated source/drain is epitaxially and selectively grown on the junction.

Selective Si epitaxial deposition and SiGe epitaxial deposition permits growth of epilayers on Si moats with no growth on dielectric areas. Selective epitaxy can be used in semiconductor devices, such as within elevated source/drains, source/drain extensions, contact plugs, and base layer deposition of bipolar devices. Generally, a selective epitaxy process involves two reactions: deposition and etching. They occur simultaneously with relatively different reaction rates on Si and on dielectric surface. A selective process window results in deposition only on Si surfaces by changing the concentration of an etchant gas (e.g., HCl). A popular process to perform selective, epitaxy deposition is to use dichlorosilane (SiH2Cl2) as a silicon source, germane (GeH4) as a germanium source, HCl as an etchant to provide selectivity during the deposition and hydrogen (H2) as a carrier gas.

Although SiGe epitaxial deposition is suitable for small dimensions, this approach does not readily prepare doped SiGe, since the dopants react with HCl. The process development of heavily boron doped (e.g., higher than 5×1019 cm−3) selective SiGe epitaxy is a much more complicated task because boron doping makes the process window for selective deposition narrow. Generally, when more boron concentration (e.g., B2H6) is added to the flow, a higher HCl concentration is necessary to achieve selectivity due to the increase growth rate of deposited film(s) on any dielectric areas. This higher HCl flow rate proportionally reduces boron incorporation into the epilayers presumably because the B—Cl bond is stronger than Ge—Cl and Si—Cl bonds.

Therefore, there is a need to have a process for selectively and epitaxially depositing silicon and silicon compounds with an enriched dopant concentration. Furthermore, the process must maintain a high growth of the deposited material. Also, the process must have less dependency on germanium and boron concentrations in the silicon compound in relation to an etchant flow rate.

SUMMARY OF THE INVENTION

In one embodiment, the invention generally provides a method of depositing a silicon germanium film on a substrate comprising placing the substrate within a process chamber and heating the substrate surface to a temperature in a range from about 500° C. to about 900° C. while maintaining a pressure in a range from about 0.1 Torr to about 200 Torr. A deposition gas is provided to the process chamber and includes SiH4, GeH4, HCl, a carrier gas and at least one dopant gas, such as diborane, arsine or phosphine. A doped silicon germanium film is epitaxially grown on the substrate.

In another embodiment, the invention generally provides a selective epitaxial method for growing a doped silicon germanium film on a substrate comprising placing the substrate within a process chamber at a pressure in a range from about 0.1 Torr to about 200 Torr and heating the substrate surface to a temperature in a range from about 500° C. to about 900° C. A deposition gas is provided to the process chamber and includes SiH4, a germanium source, an etchant source, a carrier gas and at least one dopant gas. The silicon germanium film is grown with a dopant concentration in a range from about 1×1020 atoms/cm3 to about 2.5×1021 atoms/cm3.

In another embodiment, the invention generally provides a selective epitaxial method for growing a silicon-containing film on a substrate comprising placing the substrate within a process chamber at a pressure in a range from about 0.1 Torr to about 200 Torr and heating the substrate surface to a temperature in a range from about 500° C. to about 900° C. A deposition gas is provided to the process chamber and includes SiH4, HCl and a carrier. The silicon-containing film is grown at a rate between about 50 Å/min and about 600 Å/min.

In another embodiment, the invention generally provides a selective epitaxial method for growing a silicon-containing film on a substrate comprising placing the substrate within a process chamber at a pressure in a range from about 0.1 Torr to about 200 Torr, heating the substrate to a temperature in a range from about 500° C. to about 900° C., providing a deposition gas comprising Cl2SiH2, HCl and a carrier gas and depositing a silicon-containing layer on the substrate. The method further comprises providing a second deposition gas comprising SiH4, HCl and a second carrier gas and depositing a second silicon-containing layer on the silicon-containing layer.

In another embodiment, the invention generally provides a method of selectively depositing a silicon-containing film on a substrate comprising placing the substrate within a process chamber, heating the substrate to a temperature in a range from about 500° C. to about 900° C. and maintaining a pressure in a range from about 0.1 Torr to about 200 Torr. The method further comprises providing a deposition gas comprising a silicon-containing gas, a germanium source, HCl, at least one dopant gas and a carrier gas selected from the group consisting of N2, Ar, He and combinations thereof and depositing the silicon-containing film epitaxially on the substrate

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.

FIGS. 1A–C show several devices with epitaxially deposited silicon-containing layer; and

FIGS. 2A–F show schematic illustrations of fabrication techniques for a source/drain extension device within a MOSFET.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The invention provides a process to epitaxially deposit silicon containing compounds during the manufacture of various device structures. In some embodiments, the process utilizes the silicon precursor silane (SiH4) during the deposition of silicon compounds. While past techniques usually have used silicon precursors such as dichlorosilane, tetrachlorosilane or hexachlorodisilane, processes of the present invention teach the utilization of silane as a precursor. The use of silane has been found to deposit silicon containing films more quickly than that of dichlorosilane. Also, the use of silane during these processes provides a higher degree of control for dopant concentrations within the film and increased deposition rate.

Embodiments of the present invention teach processes to grow films of selective, epitaxial silicon compounds. Selective silicon containing film growth generally is conducted when the substrate or surface includes more than one material, such as exposed single crystalline silicon surface areas and features that are covered with dielectric material, such as oxide or nitride layers. Usually, these features are dielectric material. Selective epitaxial growth to the crystalline, silicon surface is achieved while the feature is left bare, generally, with the utilization of an etchant (e.g., HCl). The etchant removes amorphous silicon or polysilicon growth from features quicker than the etchant removes crystalline silicon growth from the substrate, thus selective epitaxial growth is achieved.

Carrier gases are used throughout the processes and include H2, Ar, N2, He and combinations thereof. In one example, H2 is used as a carrier gas. In another example N2 is used as a carrier gas. In one embodiment, a carrier gas during an epitaxial deposition process is conducted with neither H2 nor atomic hydrogen. However, an inert gas is used as a carrier gas, such as N2, Ar, He and combinations thereof. Carrier gases may be combined in various ratios during some embodiments of the process.

In one embodiment, a carrier gas includes N2 and/or Ar to maintain available sites on the silicon compound film. The presence of hydrogen on the silicon compound surface limits the number of available sites (i.e., passivates) for Si or SiGe to grow when an abundance of H2 is used as a carrier gas. Consequently, a passivated surface limits the growth rate at a given temperature, particularly at lower temperatures (e.g., <650° C.). Therefore, a carrier gas of N2 and/or Ar may be used during a process at lower temperature and reduce the thermal budget without sacrificing growth rate.

In one embodiment of the invention, a silicon compound film is epitaxially grown as a Si film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2) and an etchant (e.g., HCl). The flow rate of the silane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 600° C. to about 900° C. for example, from 600° C. to 750° C., for another example from 650° C. to 800° C. The mixture of reagents is thermally driven to react and epitaxially deposit crystalline silicon. The HCl etches any deposited amorphous silicon or polycrystalline silicon from dielectric features upon the surface of the substrate. The process is conducted to form the deposited silicon compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 50 Å/min and about 600 Å/min, preferably at about 150 Å/min. In one embodiment, the silicon compound has a thickness greater than 500 Å, such as about 1,000 Å.

Etchants are utilized to control the areas on the device to be free of deposited silicon compound. Etchants that are useful during deposition processes of the invention include HCl, HF, HBr, Si2Cl6, SiCl4, Cl2SiH2, CCl4, Cl2 and combinations thereof. Other silicon precursors, besides silane, that are useful while depositing silicon compounds include higher silanes and organosilanes. Higher silanes include the compounds with the empirical formula SixH(2X+2), such as disilane (Si2H6), trisilane (Si3H8) and tetrasilane (Si4H10), as well as others. Organosilanes include compounds with the empirical formula RySixH(2x+2−y), where R=methyl, ethyl, propyl or butyl, such as methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilane ((CH3)Si2H5), dimethyldisilane ((CH3)2Si2H4) and hexamethyldisilane ((CH3)6Si2). Organosilane compounds have been found to be advantageous silicon sources and carbon sources during embodiments of the present invention to incorporate carbon in to deposited silicon compound.

In another embodiment of the invention, a silicon compound film is epitaxially grown as a SiGe film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4) and an etchant (e.g., HCl). The flow rate of the silane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon compound, namely a silicon germanium film. The HCl etches any deposited amorphous SiGe compounds from dielectric features upon the surface of the substrate. The process is conducted to form the deposited SiGe compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 50 Å/min and about 300 Å/min, preferably at about 150 Å/min. The germanium concentration is in the range from about 1 atomic percent to about 30 atomic percent of the SiGe compound, preferably at about 20 atomic percent.

Other germanium sources or precursors, besides germane, that are useful while depositing silicon compounds include higher germanes and organogermanes. Higher germanes include the compounds with the empirical formula GexH(2x+2), such as digermane (Ge2H6), trigermane (Ge3H8) and tetragermane (Ge4H10), as well as others. Organogermanes include compounds with the empirical formula RyGexH(2x+2−y), where R=methyl, ethyl, propyl or butyl, such as methylgermane ((CH3)GeH3), dimethylgermane ((CH3)2GeH2), ethylgermane ((CH3CH2)GeH3), methyldigermane ((CH3)Ge2H5), dimethyldigermane ((CH3)2Ge2H4) and hexamethyldigermane ((CH3)6Ge2). Germanes and organogermane compounds have been found to be an advantageous germanium sources and carbon sources during embodiments of the present invention to incorporate germanium and carbon in to the deposited silicon compounds, namely SiGe and SiGeC compounds.

In one embodiment of the invention, a silicon compound film is epitaxially grown as a doped Si film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the dopant is from about 0.01 sccm to about 3 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The mixture of reagents is thermally driven to react and epitaxially deposit doped silicon films. The HCl etches any deposited amorphous silicon or polycrystalline silicon from dielectric features upon the surface of the substrate. The process is conducted to form the deposited, doped silicon compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 50 Å/min and about 600 Å/min, preferably at about 150 Å/min.

Dopants provide the deposited silicon compounds with various conductive characteristics, such as directional electron flow in a controlled and desired pathway required by the electronic device. Films of the silicon compounds are doped with particular dopants to achieve the desired conductive characteristic. In one embodiment, the silicon compound is doped p-type, such as by using diborane to add boron at a concentration in the range from about 1015 atoms/cm3 to about 1021 atoms/cm3. In one embodiment, the p-type dopant has a concentration of at least 5×1019 atoms/cm3. In another embodiment, the p-type dopant is in the range from about 1×1020 atoms/cm3 to about 2.5×1021 atoms/cm3. In another embodiment, the silicon compound is doped n-type, such as with phosphorus and/or arsenic to a concentration in the range from about 1015 atoms/cm3 to about 1021 atoms/cm3.

Besides diborane, other boron containing dopants include boranes and organoboranes. Boranes include borane, triborane, tetraborane and pentaborane, while alkylboranes include compounds with the empirical formula RxBH(3−x), where R=methyl, ethyl, propyl or butyl and x=0, 1, 2 or 3. Alkylboranes include trimethylborane ((CH3)3B), dimethylborane ((CH3)2BH), triethylborane ((CH3CH2)3B) and diethylborane ((CH3CH2)2BH). Dopants also include arsine (AsH3), phosphine (PH3) and alkylphosphines, such as with the empirical formula RxPH(3−x), where R=methyl, ethyl, propyl or butyl and x=0, 1, 2 or 3. Alkylphosphines include trimethylphosphine ((CH3)3P), dimethylphosphine ((CH3)2PH), triethylphosphine ((CH3CH2)3P) and diethylphosphine ((CH3CH2)2PH).

In another embodiment of the invention, a silicon compound film is epitaxially grown to produce a doped SiGe. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm. The flow rate of the dopant is from about 0.01 sccm to about 3 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon compound, namely a silicon germanium film. The HCl etches any deposited amorphous SiGe from features upon the surface of the substrate. The process is conducted to form the doped SiGe compound with a thickness in a range from about 100 Å to about 3,000 Å and at a rate between about 50 Å/min and about 600 Å/min, preferably at about 150 Å/min. The germanium concentration is in the range from about 1 atomic percent to about 30 atomic percent of the SiGe compound, preferably at about 20 atomic percent. The boron concentration is in the range from about 1×1020 atoms/cm3 to about 2.5×1021 atoms/cm3 of the SiGe compound, preferably at about 2×1020 atoms/cm3.

In another embodiment of the invention, a silicon compound film is epitaxially grown as a SiGeC film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4), a carbon source (e.g., CH3SiH3) and an etchant (e.g., HCl). The flow rate of the silane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm. The flow rate of the carbon source is from about 0.1 sccm to about 50 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 500° C. to about 700° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon compound, namely a silicon germanium carbon film. The HCl etches any deposited amorphous or polycrystalline SiGeC compounds from dielectric features upon the surface of the substrate. The process is conducted to form the deposited SiGeC compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 50 Å/min and about 600 Å/min, preferably at about 150 Å/min. The germanium concentration is in the range from about 1 atomic percent to about 30 atomic percent of the SiGeC compound, preferably at about 20 atomic percent. The carbon concentration is in the range from about 0.1 atomic percent to about 5 atomic percent, preferably at about 2 atomic percent of the SiGeC compound.

Other carbon sources or precursors, besides ethylene or methane, are useful while depositing silicon compounds and include alkyls, alkenes and alkynes of ethyl, propyl and butyl. Such carbon sources include ethyne (C2H2), propane (C3H8), propene (C3H6), butyne (C4H6), as well as others. Other carbon sources include organosilane compounds, as described in relation to silicon sources.

In another embodiment of the invention, a silicon compound film is epitaxially grown as a doped-SiGeC film. A substrate (e.g., 300 mm OD) containing a semiconductor feature is placed into the process chamber. During this deposition technique, silicon precursor (e.g., silane) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4), a carbon source (e.g., CH3SiH3), a dopant (e.g., B2H6) and an etchant (e.g., HCl). The flow rate of the silane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm. The flow rate of the carbon source is from about 0.1 sccm to about 50 sccm. The flow rate of the dopant is from about 0.01 sccm to about 3 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 500° C. to about 700° C. The reagent mixture is thermally driven to react and epitaxially deposit a silicon compound, namely a doped silicon germanium carbon film. The HCl etches any deposited amorphous or polycrystalline SiGeC compounds from dielectric features upon the surface of the substrate. The process is conducted to form the deposited SiGeC compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 50 Å/min and about 600 Å/min, preferably at about 150 Å/min. The germanium concentration is in the range from about 1 atomic percent to about 30 atomic percent of the SiGeC compound, preferably at about 20 atomic percent. The carbon concentration is in the range from about 0.1 atomic percent to about 5 atomic percent of the SiGeC compound, preferably at about 2 atomic percent. The boron concentration is in the range from about 1×1020 atoms/cm3 to about 2.5×1021 atoms/cm3 of the SiGe compound, preferably at about 2×1020 atoms/cm3.

In another embodiment of the invention, a second silicon compound film is epitaxially grown as a SiGe film by using dichlorosilane, subsequently to depositing any of the silicon compounds as described above via silane as a silicon source. A substrate (e.g., 300 mm OD) containing any of the above described silicon containing compounds is placed into the process chamber. During this deposition technique, silicon precursor (e.g., Cl2SiH2) is flown concurrently into the process chamber with a carrier gas (e.g., H2 and/or N2), a germanium source (e.g., GeH4) and an etchant (e.g., HCl). The flow rate of the dichlorosilane is in the range from about 5 sccm to about 500 sccm. The flow rate of the carrier gas is from about 1,000 sccm to about 60,000 sccm. The flow rate of the germanium source is from about 0.1 sccm to about 10 sccm. The flow rate of the etchant is from about 5 sccm to about 1,000 sccm. The process chamber is maintained with a pressure from about 0.1 Torr to about 200 Torr, preferably at about 15 Torr. The substrate is kept at a temperature in the range from about 500° C. to about 1,000° C., preferably from about 700° C. to about 900° C. The reagent mixture is thermally driven to react and epitaxially deposit a second silicon compound, namely a silicon germanium film. The HCl etches any deposited amorphous or polycrystalline SiGe compounds from any dielectric features upon the surface of the substrate. The process is conducted to form the deposited SiGe compound with a thickness in a range from about 100 Å to about 3,000 Å and at a deposition rate between about 10 Å/min and about 100 Å/min, preferably at about 50 Å/min. The germanium concentration is in the range from about 1 atomic percent to about 30 atomic percent of the SiGe compound, preferably at about 20 atomic percent. This embodiment describes a process to deposit a SiGe film, though substitution of silane with dichlorosilane to any of the previously described embodiments will produce a second silicon containing film. In another embodiment, a third silicon containing layer is deposited using any of the silane based process discussed above.

Therefore, in one embodiment, a silicon compound laminate film may be deposited in sequential layers of silicon compound by altering the silicon precursor between silane and dichlorosilane. In one example, a laminate film of about 2,000 Å is formed by depositing four silicon compound layers (each of about 500 Å), such that the first and third layers are deposited using dichlorosilane and the second and fourth layers are deposited using silane. In another aspect of a laminate film, the first and third layers are deposited using silane and the second and fourth layers are deposited using dichlorosilane. The thickness of each layer is independent from each other; therefore, a laminate film may have various thicknesses of the silicon compound layers.

In one embodiment, dichlorosilane is used to deposit the silicon compound layer when the previous layer contains surface islands (e.g., contamination or irregularity to film). A process incorporating dichlorosilane may be less sensitive to the surface islands while depositing the silicon compound layer over the previous layer. The use of dichlorosilane as the silicon source has a high horizontal or lateral growth rate relative to the use of silane. Once the surface island is covered and the silicon compound layer has a consistent surface, dichlorosilane is replaced with silane and deposition of the silicon compound layer is continued.

Embodiments of the invention teach processes to deposit silicon compounds on many substrates and surfaces. Substrates on which embodiments of the invention may be useful include, but are not limited to semiconductor wafers, such as crystalline silicon (e.g., Si<100> and Si<111>), silicon oxide, silicon germanium, doped or undoped wafers and patterned or non-patterned wafers. Substrates have a variety of geometries (e.g., round, square and rectangular) and sizes (e.g., 200 mm OD, 300 mm OD). Surfaces and./or substrates include wafers, films, layers and materials with dielectric, conductive and barrier properties and include polysilicon, silicon on insulators (SOI), strained and unstrained lattices. Pretreatment of surfaces includes polishing, etching, reduction, oxidation, hydroxylation, annealing and baking. In one embodiment, wafers are dipped into a 1% HF solution, dried and baked in a hydrogen atmosphere at 800° C.

In one embodiment, silicon compounds include a germanium concentration within the range from about O atomic percent to about 95 atomic percent. In another embodiment, a germanium concentration is within the range from about 1 atomic percent to about 30 atomic percent, preferably from about 15 atomic percent to about 25 atomic percent and more preferably at about 20 atomic percent. Silicon compounds also include a carbon concentration within the range from about 0 atomic percent to about 5 atomic percent. In other aspects, a carbon concentration is within the range from about 200 ppm to about 2 atomic percent.

The silicon compound films of germanium and/or carbon are produced by various processes of the invention and can have consistent, sporadic or graded elemental concentrations. Graded silicon germanium films are disclosed in U.S. patent applications 20020174826 and 20020174827 assigned to Applied Material, Inc., and are incorporated herein by reference in entirety for the purpose of describing methods of depositing graded silicon compound films. In one embodiment, silane and a germanium source (e.g., GeH4) are used to deposit silicon germanium containing films. In this embodiment, the ratio of silane and germanium source can be varied in order to provide control of the elemental concentrations while growing graded films. In another embodiment, silane and a carbon source (e.g., CH3SiH3) are used to deposit silicon carbon containing films. The ratio of silane and carbon source can be varied in order to provide control of the elemental concentration while growing homogenous or graded films. In another embodiment, silane, a germanium source (e.g., GeH4) and a carbon source (e.g., CH3SiH3) are used to deposit silicon germanium carbon containing films. The ratio of silane, germanium and carbon source can be varied in order to provide control of the elemental concentration while growing homogenous or graded films.

In processes of the invention, silicon compound films are grown by chemical vapor deposition (CVD) processes, wherein CVD processes include atomic layer deposition (ALD) processes and/or atomic layer epitaxy (ALE) processes. Chemical vapor deposition includes the use of many techniques, such as plasma-assisted CVD (PA-CVD), atomic layer CVD (ALCVD), organometallic or metalorganic CVD (OMCVD or MOCVD), laser-assisted CVD (LA-CVD), ultraviolet CVD (UV-CVD), hot-wire (HWCVD), reduced-pressure CVD (RP-CVD), ultra-high vacuum CVD (UHV-CVD) and others. In one embodiment, the preferred process of the present invention is to use thermal CVD to epitaxially grow or deposit the silicon compound, whereas the silicon compound includes silicon, SiGe, SiC, SiGeC, doped variants thereof and combinations thereof.

The processes of the invention can be carried out in equipment known in the art of ALE, CVD and ALD. The apparatus brings the sources into contact with a heated substrate on which the silicon compound films are grown. The processes can operate at a range of pressures from about 1 mTorr to about 2,300 Torr, preferably between about 0.1 Torr and about 200 Torr. Hardware that can be used to deposit silicon-containing films includes the Epi Centura® system and the Poly Gen® system available from Applied Materials, Inc., located in Santa Clara, Calif. An ALD apparatus is disclosed in U.S. patent application 20030079686, assigned to Applied Material, Inc., and entitled “Gas Delivery Apparatus and Methods for ALD”, and is incorporated herein by reference in entirety for the purpose of describing the apparatus. Other apparatuses include batch, high-temperature furnaces, as known in the art.

The processes are extremely useful while depositing silicon compound layers in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) and bipolar transistors as depicted in FIGS. 1A–1C. Herein, silicon compounds are the deposited layers or films and include Si, SiGe, SiC, SiGeC, doped variants thereof and combinations thereof, epitaxially grown during the processes of the present invention. The silicon compounds include strained or unstrained layers within the films.

FIGS. 1A–1B show the epitaxially grown silicon compound on a MOSFET. The silicon compound is deposited to the source/drain features of the device. The silicon compound adheres and grows from the crystal lattice of the underlying layer and maintains this arrangement as the silicon compound grows with thickness. In one embodiment, FIG. 1A demonstrates the silicon compound deposited as a source/drain extension source, while in another embodiment, FIG. 1B shows the silicon compound deposited as an elevated source/drain (ESD).

The source/drain layer 12 is formed by ion implantation of the substrate 10. Generally, the substrate 10 is doped n-type while the source/drain layer 12 is doped p-type. Silicon compound layer 14 is epitaxially grown to the source/drain layer 12 by the various embodiments of the present invention. A gate oxide layer 18 bridges the either the segmented silicon compound layer 14 (FIG. 1A) or the segmented source/drain layer 12 (FIG. 1B). Generally, gate oxide layer 18 is composed of silicon dioxide, silicon oxynitride or tantalum oxide. Partially encompassing the gate oxide layer 18 is a spacer 16, which is usually an isolation material such as a nitride/oxide stack (e.g., Si3N4/SiO2/Si3N4). Also within the spacer 16 is off-set layers 20 (e.g., Si3N4) and the gate layer 22 (e.g., W or Ni).

In another embodiment, FIG. 1C depicts the deposited silicon compound layer 34 as a base layer of a bipolar transistor. The silicon compound layer 34 is epitaxially grown with the various embodiments of the invention. The silicon compound layer 34 is deposited to an n-type collector layer 32 previously deposited to substrate 30. The transistor further includes isolation layer 33 (e.g., SiO2 or Si3N4), contact layer 36 (e.g., heavily doped poly-Si), off-set layer 38 (e.g., Si3N4) and a second isolation layer 40 (e.g., SiO2 or Si3N4).

In one embodiment, as depicted in FIGS. 2A–2F, a source/drain extension is formed within a MOSFET wherein the silicon compound layers are epitaxially and selectively deposited on the surface of the substrate. FIG. 2A depicts a source/drain layer 132 formed by implanting ions into the surface of a substrate 130. The segments of source/drain layer 132 are bridged by the gate 136 formed within off-set layer 134. A portion of the source/drain layer is etched and wet-cleaned, to produce a recess 138, as in FIG. 2B.

FIG. 2C illustrates several embodiments of the present invention, in which silicon compound layers 140 (epitaxial) and 142 (polycrystalline) are selectively deposited. Silicon compound layers 140 and 142 are deposited simultaneously without depositing on the off-set layer 134. Silicon compound layers 140 and 142 are generally doped SiGe containing layers with a germanium concentration at about 1 atomic percent to about 30 atomic percent, preferably at about 20 atomic percent and a dopant (e.g., B, As or P) concentration from about 1×1020 atoms/cm3 to about 2.5×1021 atoms/cm3, preferably at about 2×1020 atoms/cm3. During the next step, FIG. 2D shows the nitride spacer 144 (e.g., Si3N4) deposited to the off-set layer 134.

FIG. 2E depicts another embodiment of the present invention, in which a silicon compound is epitaxially and selectively deposited as silicon compound layer 148. Silicon compound layer 148 is deposited on layer 140 (doped-SiGe). Polysilicon layer 146 is deposited on the silicon compound layer 142 (doped-SiGe).

In the next step shown in FIG. 2F, a metal layer 154 is deposited over the features and the device is annealed. The metal layer 154 includes cobalt, nickel or titanium, among other metals. During the annealing process, polysilicon layer 146 and silicon compound layer 148 are converted to metal silicide layers, 150 and 152, respectively. That is, when cobalt is deposited as metal layer 154, then metal silicide layers 150 and 152 are cobalt silicide.

The silicon compound is heavily doped with the in-situ dopants. Therefore, annealing steps of the prior art are omitted and the overall throughput is shorter. An increase of carrier mobility along the channel and subsequent drive current is achieved with the optional addition of germanium and/or carbon into the silicon compound layer. Selectively grown epilayers of the silicon compound above the gate oxide level can compensate junction consumption during the silicidation, which can relieve concerns of high series resistance of ultra shallow junctions. These two applications can be implemented together as well as solely for CMOS device fabrication.

Silicon compounds are utilized within embodiments of the processes to deposit silicon compounds films used for Bipolar (e.g., base, emitter, collector, emitter contact), BiCMOS (e.g., base, emitter, collector, emitter contact) and CMOS (e.g., channel, source/drain, source/drain extension, elevated source/drain, substrate, strained silicon, silicon on insulator and contact plug). Other embodiments of processes teach the growth of silicon compounds films that can be used as gate, base contact, collector contact, emitter contact, elevated source/drain and other uses.

EXAMPLE 1 Boron Doped Silicon Germanium Deposition

A substrate, Si<100>, (e.g., 300 mm OD) was employed to investigate selective, monocrystalline film growth by CVD. A dielectric feature existed on the surface of the wafer. The wafer was prepared by subjecting to a 1% HF dip for 45 seconds. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Silane (100 sccm) and germane (6 sccm) were added to the chamber at 15 Torr and 725° C. Hydrogen chloride was delivered with a flow rate of 460 sccm. Diborane was delivered with a flow rate of 1 sccm. The substrate was maintained at 725° C. Deposition was carried out for 5 minutes to form a 500 Å SiGe film with a germanium concentration of 21 atomic percent and the boron concentration was 2.0×1020 cm−3.

EXAMPLE 2 Phosphorus Doped Silicon Germanium Deposition

A substrate was prepared as in Example 1. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Silane (100 sccm) and germane (4 sccm) were added to the chamber at 15 Torr and 725° C. Hydrogen chloride was delivered with a flow rate of 250 sccm. Phosphine was delivered to the chamber with a flow rate of 1 sccm. The substrate was maintained at 725° C. Deposition was carried out for 5 minutes to form a 500 Å SiGe film with a germanium concentration of 20 atomic percent and the phosphorus concentration was 1.6×1020 cm−3.

EXAMPLE 3 Boron Doped Silicon Germanium Deposition with Sequential Cl2SiH2 and SiH4 Flows

The substrates were prepared as in Example 1. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Dichlorosilane (100 sccm), germane (2.8 sccm), and diborane (0.3 sccm) were added to the chamber at 15 Torr and 725° C. Hydrogen chloride was delivered with a flow rate of 190 sccm. The substrate was maintained at 725° C. Deposition was conducted for 72 seconds to form a first layer of silicon compound with a thickness of 50 Å. On top of the first layer, a subsequent epitaxial layer (i.e., a second layer of silicon compound) was deposited using silane (100 sccm), germane (6 sccm), hydrogen chloride (460 sccm) and diborane (1 sccm). The chamber pressure and temperature remained constant (15 Torr and 725° C.) and the deposition was conducted for 144 seconds to form 250 Å layer of the second layer.

EXAMPLES 4 Boron Doped Silicon Germanium Deposition with Sequential Using SiH4 and Cl2SiH2

The substrates were prepared as in Example 1. The wafer was loaded into the deposition chamber (Epi Centura® chamber) and baked in a hydrogen atmosphere at 800° C. for 60 seconds to remove native oxide. A flow of carrier gas, hydrogen, was directed towards the substrate and the source compounds were added to the carrier flow. Silane (100 sccm), germane (6 sccm), and diborane (1 sccm) were added to the chamber at 15 Torr and 725° C. Hydrogen chloride was delivered with a flow rate of 460 sccm. The substrate was maintained at 725° C. Deposition was conducted for 144 seconds to form a first layer of silicon compound with a thickness of 250 Å. On top of the first layer, a second layer of silicon compound was sequentially deposited using dichlorosilane (100 sccm), germane (2.8 sccm), hydrogen chloride (190 sccm) and diborane (0.3 sccm). The chamber pressure and temperature remained constant (15 Torr and 725° C.) was conducted for 72 seconds to form additional 50 Å layer.

While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US4834831Sep 4, 1987May 30, 1989Research Development Corporation Of JapanMethod for growing single crystal thin films of element semiconductor
US5112439Nov 14, 1990May 12, 1992McncMasking, reducing and disproportionation to form coatings for integrated circuits
US5273930 *Sep 3, 1992Dec 28, 1993Motorola, Inc.Method of forming a non-selective silicon-germanium epitaxial film
US5294286Jan 12, 1993Mar 15, 1994Research Development Corporation Of JapanAlternating supply of dichlorosilane and evacuating; counting cycles; semiconductors
US5372860Jul 6, 1993Dec 13, 1994Corning IncorporatedHeating glass substrate to compact, applying noncrystalline silicon film, heating to covert to polycrystalline silicon
US5374570Aug 19, 1993Dec 20, 1994Fujitsu LimitedAtomic layer epitaxy
US5469806Aug 20, 1993Nov 28, 1995Nec CorporationChlorination of semiconductor surfaces, dechlorination by forming hydrogen chloride with hydrogen and epitaxial crystallization
US5480818Feb 9, 1993Jan 2, 1996Fujitsu LimitedMethod for forming a film and method for manufacturing a thin film transistor
US5527733Feb 18, 1994Jun 18, 1996Seiko Instruments Inc.Covering substrate with oxide film, removal of film by reduction and heat treatment, applying boron hydrogen gas to form adsorption layer
US5674304Sep 23, 1994Oct 7, 1997Semiconductor Energy Laboratory Co., Ltd.Method of heat-treating a glass substrate
US5693139Jun 15, 1993Dec 2, 1997Research Development Corporation Of JapanDoping compound semiconductor single crystal layer by alternate introduction of source gases while growth chamber is being evacuated continuously
US5796116Jul 25, 1995Aug 18, 1998Sharp Kabushiki KaishaThin-film semiconductor device including a semiconductor film with high field-effect mobility
US5807792Dec 18, 1996Sep 15, 1998Siemens AktiengesellschaftRotation; alternating supplying segments
US5906680Dec 24, 1996May 25, 1999International Business Machines CorporationMethod and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US6025627May 29, 1998Feb 15, 2000Micron Technology, Inc.Alternate method and structure for improved floating gate tunneling devices
US6042654Jan 13, 1998Mar 28, 2000Applied Materials, Inc.Thermally decomposing chlorine gas to form free radicals; reacting free radicals with said deposits formed inside process chamber on internal components made of quartz, silicon carbide coated graphite, stainless steel; removing by products
US6159852Feb 13, 1998Dec 12, 2000Micron Technology, Inc.Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor
US6232196Mar 5, 1999May 15, 2001Asm America, Inc.Method of depositing silicon with high step coverage
US6235568 *Jan 22, 1999May 22, 2001Intel CorporationSemiconductor device having deposited silicon regions and a method of fabrication
US6284686Dec 22, 1999Sep 4, 2001Osram Sylvania Inc.Lead and arsenic free borosilicate glass and lamp containing same
US6291319Dec 17, 1999Sep 18, 2001Motorola, Inc.Method for fabricating a semiconductor structure having a stable crystalline interface with silicon
US6335280Jan 13, 1997Jan 1, 2002Asm America, Inc.Tungsten silicide deposition process
US6348420Dec 23, 1999Feb 19, 2002Asm America, Inc.Situ dielectric stacks
US6352945Jun 7, 1999Mar 5, 2002Asm Japan K.K.Introducing silicon compound having two alkoxy groups or less with no additive gas into reaction chamber for plasma chemical vapor deposition containing semiconductor substrate, activating plasma polymerization to form silicone film
US6358829Sep 16, 1999Mar 19, 2002Samsung Electronics Company., Ltd.Semiconductor device fabrication method using an interface control layer to improve a metal interconnection layer
US6383955Jun 7, 1999May 7, 2002Asm Japan K.K.Forming polysiloxanes using plasma polymerization and controlling the residence time to control the dielectric constant; oxygen plasma resistance
US6410463Oct 18, 2000Jun 25, 2002Asm Japan K.K.Method for forming film with low dielectric constant on semiconductor substrate
US6451119Nov 29, 2000Sep 17, 2002Genus, Inc.Apparatus and concept for minimizing parasitic chemical vapor deposition during atomic layer deposition
US6458718Apr 24, 2001Oct 1, 2002Asm Japan K.K.Providing a substrate; providing a chemical precursor of the formula (f3c)4-m-nmxmrn, wherein m is silicon or germenium, x is halogen, r is hydrogen or d, activating the precursor to deposit a fluorine containing material onto the substrate
US6489241Sep 17, 1999Dec 3, 2002Applied Materials, Inc.Apparatus and method for surface finishing a silicon film
US6544900Nov 14, 2001Apr 8, 2003Asm America, Inc.In situ dielectric stacks
US6559520Apr 25, 2002May 6, 2003Asm Japan K.K.Vaporizing a dialkoxydialkylsilicon for chemical vapor deposition on a semiconductor and introducing oxygen and an inert gas to activate plasma polymerisation; low dielectric constant; humidity and heat resistance
US6562720Feb 14, 2002May 13, 2003Applied Materials, Inc.Apparatus and method for surface finishing a silicon film
US6797558Jan 15, 2002Sep 28, 2004Micron Technology, Inc.Methods of forming a capacitor with substantially selective deposite of polysilicon on a substantially crystalline capacitor dielectric layer
US6821825Feb 11, 2002Nov 23, 2004Asm America, Inc.Vapor deposition using silane compound; uniform thickness
US20010020712Jan 18, 2001Sep 13, 2001Ivo RaaijmakersMethod of depositing silicon with high step coverage
US20010024871Jan 31, 2001Sep 27, 2001Fuji Xerox Co.Semiconductor device and method and apparatus for manufacturing semiconductor device
US20010045604 *Apr 3, 2001Nov 29, 2001Hitachi, Ltd.Semiconductor device and manufacturing method
US20010046567Apr 6, 2001Nov 29, 2001Nobuo MatsukiVaporizing a silicon-containing hydrocarbon compound producing gas for polysiloxane, chemical vapor deposition wherein semiconductor is placed, introducing additive gas (inert and oxidizing), forming film via plasma polymerization
US20010055672Feb 7, 2001Dec 27, 2001Todd Michael A.Low dielectric constant materials and processes
US20020090818Feb 14, 2002Jul 11, 2002Anna Lena ThilderkvistApparatus and method for surface finishing a silicon film
US20020093042Nov 13, 2001Jul 18, 2002Sang-Jeong OhIntegrated circuit devices that utilize doped Poly-Si1-xGex conductive plugs as interconnects and methods of fabricating the same
US20020142557 *Mar 4, 2002Oct 3, 2002Takashi HashimotoSemiconductor device and a method of manufacturing the same
US20020145168Feb 5, 2001Oct 10, 2002International Business Machines CorporationMethod for forming dielectric stack without interfacial layer
US20020168868Feb 11, 2002Nov 14, 2002Todd Michael A.First and second surfaces with different morphology, adding trisilane to the chamber under chemical vapor depostion, and depositing a silane containing film
US20020173113Feb 11, 2002Nov 21, 2002Todd Michael A.Vapor deposition; doping
US20020173130Feb 11, 2002Nov 21, 2002Pomerede Christophe F.Vapor deposition using silane and dopant gas mixture; overcoating with dielectrics and electrodes; controlling concentration of gas mixture
US20020197831Feb 11, 2002Dec 26, 2002Todd Michael A.Thin Films and Methods of Making Them
US20030022528Feb 11, 2002Jan 30, 2003Todd Michael A.Improved Process for Deposition of Semiconductor Films
US20030036268May 29, 2002Feb 20, 2003Brabant Paul D.Low temperature load and bake
US20030082300Feb 11, 2002May 1, 2003Todd Michael A.Vapor deposition using silane compound; uniform thickness
US20030189208Apr 5, 2002Oct 9, 2003Kam LawDeposition of silicon layers for active matrix liquid crystal display (AMLCD) applications
US20040033674Aug 14, 2002Feb 19, 2004Todd Michael A.Deposition of amorphous silicon-containing films
US20040226911Apr 24, 2003Nov 18, 2004David DuttonLow-temperature etching environment
US20040253776Jun 12, 2003Dec 16, 2004Thomas HoffmannGate-induced strain for MOS performance improvement
US20050045905 *Aug 29, 2003Mar 3, 2005International Business Machines CorporationUltra high-speed si/sige modulation-doped field effect transistors on ultra thin soi/sgoi substrate
US20050079691Oct 10, 2003Apr 14, 2005Applied Materials, Inc.Methods of selective deposition of heavily doped epitaxial SiGe
EP1150345A2Apr 26, 2001Oct 31, 2001Asm Japan K.K.Fluorine-containing materials and processes
JP2001111000A Title not available
JP2001189312A Title not available
JPH0547665A Title not available
JPH01270593A Title not available
JPH02172895A Title not available
JPH03286522A Title not available
JPH05102189A Title not available
JPS5898917A Title not available
JPS6362313A Title not available
JPS62171999A Title not available
WO1998020524A1Nov 6, 1997May 14, 1998Pacific Solar Pty LtdForming a crystalline semiconductor film on a glass substrate
WO2001041544A2Nov 17, 2000Jun 14, 2001Asm IncDeposition of gate stacks including silicon germanium layers
WO2002064853A2Feb 12, 2002Aug 22, 2002Asm IncThin films and methods of making them using trisilane
WO2002065508A2Feb 12, 2002Aug 22, 2002Asm IncDopant precursors and processes
WO2002065516A2Feb 12, 2002Aug 22, 2002Asm IncImproved process for deposition of semiconductor films
WO2002065517A2Feb 12, 2002Aug 22, 2002Asm IncDeposition method over mixed substrates using trisilane
WO2002065525A1Feb 12, 2002Aug 22, 2002Asm IncIntegration of high k gate dielectric
WO2002080244A2Feb 1, 2002Oct 10, 2002Asm IncImproved process for deposition of semiconductor films
WO2002097864A2May 29, 2002Dec 5, 2002Asm IncLow temperature load and bake
WO2005038890A1Sep 21, 2004Apr 28, 2005Applied Materials IncMethods of selective deposition of heavily doped epitaxial sige
Non-Patent Citations
Reference
1Article by Kamins et al., entitled "Kinetics of Selective epitaxial deposition Si<SUB>1-x</SUB>Ge<SUB>x</SUB>", American Institute of Physics, Aug. 1992, No. 6, pp. 669-671.
2Article by Menon et al., entitled "Loading effect in SiGe layers grown by dichlorosilane-and silane-based epitaxy", American Institute of Physics, Nov. 2001, vol. 90, No. 9, pp. 4805-4809.
3Article by Sedgwick et al., entitled "Selective SiGe and heavily as doped Si deposited at low temperature by atmospheric pressure chemical vapor deposition", Journal of Vacuum Science & Technology, May/Jun. 1993, No. 3, pp. 1124-1128.
4Article by Uchino et al., entitled "A Raised Source/Drain Technology Using In-situ P-doped SiGe and B-doped Si for 0.1-mum CMOS ULSIs", IEDM, Dec. 1997, Technical Digest, pp. 479-482.
5Choi, et al., Stability of TiB<SUB>2 </SUB>as a Diffusion Barrier on Silicon.Electrochemical Society vol. 138 No. 10 Oct. 1991.
6International Search Report dated Mar. 30, 2006 for International Application No. PCT/US2005/016160 (APPM/008539PC02) , 10 pages.
7International Search Report mailed Feb. 22, 2005 for PCT/US2004/030872 (AMAT/8539-PCT).
8Invitation to Pay Additional Fees and Partial International Search Report for PCT/US2005/016160 Feb. 8, 2006, 6 pages.
9Jeong, et al. "Growth and Characterization of Aluminum Oxide (Al<SUB>2</SUB>O<SUB>3</SUB>) Thin Films by Plasma-Assisted Atomic Layer Controlled Deposition," J. Korean Inst. Met. Mater., vol. 38, No. 10, Oct. 2000 pp. 1395-1399.
10Jeong, et al. "Plasma-assisted Atomic Layer Growth of High-Quality Aluminum Oxide Thin Films," Jpn. J. Appl. Phys. 1, Regul. Pap. Short Notes, vol. 40, No. 1, Jan. 2001 pp. 285-289.
11Lee, et al., Cyclic technique for the enhancement of highly oriented diamond film growt, Elsevier Science S.A., Thin Solid Films (1997) 264-268.
12Paranjpe, et al., Atomic Layer Deposition of AIO<SUB>x </SUB>for Thin Film Head Gap Applications, ECS, Journal of the Electrochemical Society, 148 (9) G465-G471 (2001).
13Written Opinion of the International Searching Authority dated Mar. 30, 2006 for International Application No. PCT/US2005/016160 (APPM/008539PC02) , 12 pages.
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7238580 *Jan 26, 2005Jul 3, 2007Freescale Semiconductor, Inc.Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration
US7410875 *Apr 6, 2006Aug 12, 2008United Microelectronics Corp.Semiconductor structure and fabrication thereof
US7439142Oct 9, 2006Oct 21, 2008Applied Materials, Inc.Methods to fabricate MOSFET devices using a selective deposition process
US7453120 *Jul 13, 2007Nov 18, 2008Unitd Microelectronics Corp.Semiconductor structure
US7517775May 30, 2006Apr 14, 2009Applied Materials, Inc.Methods of selective deposition of heavily doped epitaxial SiGe
US7605060 *Mar 25, 2004Oct 20, 2009Nxp B.V.Method of epitaxial deoposition of an n-doped silicon layer
US7612389 *Sep 15, 2005Nov 3, 2009Taiwan Semiconductor Manufacturing Company, Ltd.Embedded SiGe stressor with tensile strain for NMOS current enhancement
US7655543Dec 21, 2007Feb 2, 2010Asm America, Inc.Separate injection of reactive species in selective formation of films
US7709391Jan 20, 2006May 4, 2010Applied Materials, Inc.Methods for in-situ generation of reactive etch and growth specie in film formation processes
US7732269May 1, 2007Jun 8, 2010Applied Materials, Inc.Method of ultra-shallow junction formation using Si film alloyed with carbon
US7737007Aug 29, 2008Jun 15, 2010Applied Materials, Inc.Methods to fabricate MOSFET devices using a selective deposition process
US7781799Oct 24, 2007Aug 24, 2010Taiwan Semiconductor Manufacturing Company, Ltd.Source/drain strained layers
US7808081 *Jan 3, 2007Oct 5, 2010International Business Machines CorporationStrained-silicon CMOS device and method
US7897491Dec 16, 2009Mar 1, 2011Asm America, Inc.Separate injection of reactive species in selective formation of films
US7939447Oct 26, 2007May 10, 2011Asm America, Inc.Inhibitors for selective deposition of silicon containing films
US7960236Dec 17, 2007Jun 14, 2011Applied Materials, Inc.Phosphorus containing Si epitaxial layers in N-type source/drain junctions
US7973337 *Jul 28, 2010Jul 5, 2011Taiwan Semiconductor Manufacturing Company, Ltd.Source/drain strained layers
US7977690Aug 19, 2009Jul 12, 2011International Business Machines CorporationTechniques for use of nanotechnology in photovoltaics
US7994010Dec 27, 2007Aug 9, 2011Chartered Semiconductor Manufacturing Ltd.Process for fabricating a semiconductor device having embedded epitaxial regions
US7998788 *Jul 27, 2006Aug 16, 2011International Business Machines CorporationTechniques for use of nanotechnology in photovoltaics
US8168501May 27, 2011May 1, 2012Taiwan Semiconductor Manufacturing Co., Ltd.Source/drain strained layers
US8394196 *Dec 12, 2006Mar 12, 2013Applied Materials, Inc.Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon
US8501594Jun 15, 2010Aug 6, 2013Applied Materials, Inc.Methods for forming silicon germanium layers
US8598020Jun 25, 2010Dec 3, 2013Applied Materials, Inc.Plasma-enhanced chemical vapor deposition of crystalline germanium
US8652945 *Jul 28, 2011Feb 18, 2014Applied Materials, Inc.Epitaxy of high tensile silicon alloy for tensile strain applications
US20090305474 *Aug 13, 2009Dec 10, 2009International Business Machines CorporationStrained-silicon cmos device and method
WO2012102755A1 *Jul 27, 2011Aug 2, 2012Applied Materials, Inc.Carbon addition for low resistivity in situ doped silicon epitaxy
Classifications
U.S. Classification438/607, 438/503, 257/E21.131, 257/E21.106, 438/300, 438/481
International ClassificationH01L21/336, H01L21/205, H01L21/44, H01L21/20
Cooperative ClassificationH01L21/02579, H01L21/02576, H01L29/78, H01L21/0262, H01L29/7848, H01L21/02636, H01L21/0237, H01L21/02532
European ClassificationH01L21/02K4C1A3, H01L21/02K4E3S, H01L21/02K4A1, H01L21/02K4C3C1, H01L21/02K4E3C, H01L21/02K4C3C2, H01L29/78R6
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