|Publication number||US7187033 B2|
|Application number||US 10/890,648|
|Publication date||Mar 6, 2007|
|Filing date||Jul 14, 2004|
|Priority date||Jul 14, 2004|
|Also published as||US20060011974, US20070114607|
|Publication number||10890648, 890648, US 7187033 B2, US 7187033B2, US-B2-7187033, US7187033 B2, US7187033B2|
|Original Assignee||Texas Instruments Incorporated|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (15), Non-Patent Citations (1), Referenced by (54), Classifications (19), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates generally to semiconductor devices and more particularly to extended-drain MOS transistor devices and fabrication methods for making the same.
Power semiconductor products are often fabricated using N or P channel drain-extended metal-oxide-semiconductor (DEMOS) transistor devices, such as lateral diffused MOS (LDMOS) devices or REduced SURface Field (RESURF) transistors, for high power switching applications. DEMOS devices advantageously combine short-channel operation with high current handling capabilities, relatively low drain-to-source on-state resistance (Rdson), and the ability to withstand high blocking voltages without suffering voltage breakdown failure. Breakdown voltage is typically measured as drain-to-source breakdown voltage with the gate and source shorted together (BVdss), where DEMOS device designs often involve a tradeoff between breakdown voltage BVdss and Rdson. In addition to performance advantages, DEMOS device fabrication is relatively easy to integrate into CMOS process flows, facilitating use in devices where logic, low power analog, or other circuitry is also to be fabricated in a single integrated circuit (IC).
N-channel drain-extended transistors (DENMOS) are asymmetrical devices often formed in an n-well with a p-well (e.g., sometimes referred to as a p-body) formed in the n-well. An n-type source is formed within the p-well, where the p-well provides a p-type channel region between the source and an extended n-type drain. The extended drain typically includes an n-type drain implanted within the n-well, and a drift region in the n-well extending between the channel region and the drain. Low n-type doping on the drain side provides a large depletion layer with high blocking voltage capability, wherein the p-well is typically connected to the source by a p-type back-gate connection to prevent the p-well from floating, thereby stabilizing the device threshold voltage (Vt). The device drain region is spaced from the channel (e.g., extended) to provide a drift region or drain extension in the n-type semiconductor material therebetween. In operation, the spacing of the drain and the channel spreads out the electric fields, thereby increasing the breakdown voltage rating of the device (higher BVdss). However, the drain extension increases the resistance of the drain-to-source current path (Rdson), whereby DEMOS device designs often involve a tradeoff between high breakdown voltage BVdss and low Rdson.
DEMOS devices have been widely used for power switching applications requiring high blocking voltages, and high current carrying capability, particularly where a solenoid or other inductive load is to be driven. In one common configuration, two or four n-channel DEMOS devices are arranged as a half or full “H-bridge” circuit to drive a load. In a half H-bridge arrangement, two DEMOS transistors are coupled in series between a supply voltage VCC and ground with a load coupled from an intermediate node between the two transistors to ground. In this configuration, the transistor between the intermediate node and ground is referred to as the “low-side” transistor and the other transistor is a “high-side” transistor, wherein the transistors are alternatively activated to provide current to the load. In a full H-bridge driver circuit, two high-side drivers and two low-side drivers are provided, with the load being coupled between two intermediate nodes.
In operation, the high-side DEMOS has a drain coupled with the supply voltage and a source coupled to the load. In an “on” state, the high-side driver conducts current from the supply to the load, wherein the source is essentially pulled up to the supply voltage. Typical DEMOS devices are fabricated in a wafer having a p-doped silicon substrate with an epitaxial silicon layer formed over the substrate, where the substrate is grounded and the transistor source, drain, and channel (e.g., including the n-well and the p-well) are formed in the epitaxial silicon. In the on-state for the high-side DEMOS device, therefore, it is desirable to separate the p-well that surrounds the source from the underlying p-type substrate that is grounded, to prevent punch-thru current between the p-well and the substrate. Although the n-well may extend under the p-well, the n-well is typically only lightly doped, and therefore does not provide an adequate barrier to on-state punch-thru current from the source to the substrate. Accordingly, a heavily doped n-buried layer (e.g., NBL) is sometimes formed in the substrate prior to forming the epitaxial silicon layer to separate the n-well from the substrate, and to thereby inhibit on-state punch-thru current from the p-well to the substrate in high-side DEMOS drivers. The n-buried layer may be connected by a deep diffusion or sinker to the drain terminal in such high-side DEMOS devices, and hence is tied to the supply voltage so as to prevent or inhibit on-state punch-thru currents.
Although the n-buried layer operates to prevent on-state punch-thru current, the NBL limits the off-state breakdown voltage rating of high-side DEMOS drivers. In an “off” state, the high-side driver source is essentially pulled to ground while the low-side driver is conducting, wherein the drain-to-source voltage across the high-side DEMOS is essentially the supply voltage VCC. In high voltage switching applications, the presence of the n-buried layer under the p-well limits the drain-to-source breakdown of the device, since the n-buried layer is tied to the drain at VCC. In this situation, the p-well is at ground, since the source is low in the off-state, and the supply voltage VCC is essentially dropped across the n-well portion extending between the bottom of the p-well and the n-buried layer, and between the channel-side of the p-well and the drain. Furthermore, as the high-side driver is shut off when driving an inductive load, the transient drain-to-source voltage may increase beyond the supply voltage level VCC.
In these situations, the lateral spacing of the drain from the p-well may be adjusted to prevent p-well to drain breakdown. However, the vertical spacing between the bottom of the p-well and the n-buried layer is more difficult to increase. One approach is to increase the thickness of the epitaxial silicon layer. However, this is costly in terms of process complexity, particularly in forming the deep diffusions to connect the n-buried layer to the drain. Accordingly, there is a need for improved DEMOS devices and fabrication methods by which increased voltage breakdown withstanding capabilities can be achieved, without increasing epitaxial silicon thicknesses and without sacrificing device performance.
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates to n or p-channel drain-extended MOS (DEMOS) transistors and fabrication methods in which an extended drain is separated from a first buried layer and coupled thereto by an internal or external diode. The invention facilitates increased breakdown voltage operation of high-side drivers and other DEMOS devices without requiring thicker epitaxial silicon layers and without adversely impacting Rdson, whereby increased driver operating voltages can be achieved with minimal changes to existing fabrication process flows. The first buried layer may be separated from the extended drain by a second buried layer of opposite conductivity type formed prior to epitaxial growth. The diode may be formed separately in the epitaxial layer with connections from an anode to the first buried layer and from a cathode to the extended drain being formed in interconnection or metalization layers, or external connections may be formed for coupling an external diode between the first buried layer and the extended drain.
The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed.
One or more implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout, and wherein the illustrated structures are not necessarily drawn to scale. The invention provides improved DEMOS transistors and fabrication methods therefor, by which high breakdown voltage ratings can be achieved without increasing epitaxial silicon thickness, wherein a buried layer is diode coupled to an extended drain. The invention finds particular utility in high-side driver transistor applications in full or half-bridge circuits, although the transistors and methods of the invention are not limited to such applications. The various aspects of the invention are illustrated and described hereinafter in the context of NMOS driver transistors, although PMOS implementations are also possible, with p-doped regions being substituted for n-doped regions and vice versa. In addition, while the exemplary devices below are formed using a semiconductor body having a silicon substrate and an overlying epitaxial silicon layer, other semiconductor bodies may be used, including but not limited to standard semiconductor wafers, SOI wafers, etc., wherein all such variant implementations are contemplated as falling within the scope of the present invention and the appended claims.
As illustrated in
On the left side of the H-bridge in
In order to appreciated one or more shortcomings of conventional DEMOS transistors in applications such as the H-bridge of
As illustrated in
In such a driver application, the high-side device drain 56 is connected to the supply voltage VCC and the source 54 is coupled to the load at the intermediate node N1. When the high side transistor 3 is on, both the source 54 and the drain 56 are at or near the supply voltage VCC, wherein the n-buried layer 20 helps to prevent punch-thru current from flowing between the p-well 18 and the grounded p-type substrate 4, wherein the n-buried layer 20 is tied to the drain 56 (e.g., to VCC). However, when the high-side transistor 3 is off, the source 54 is essentially pulled to ground via the low-side transistor, whereby the drain-to-source voltage across the high-side DENMOS 3 is essentially the supply voltage VCC. Moreover, when switching from the on-state to the off-state, the high-side driver 3 may experience transient drain-to-source voltages greater than VCC where the load is inductive.
The inventor has appreciated that these regions 21 and 22 are susceptible to breakdown at higher supply voltages in the high-side driver off-state due at least in part to the n-buried layer 20 located beneath the n-well 8, wherein the breakdown voltage BVdss of the illustrated conventional DENMOS 3 is relatively low. Thus, while the n-buried layer 20 inhibits on-state punch-thru current from the p-well 18 to the substrate 4, the off-state breakdown voltage BVdss of the high-side driver 3 is limited by the presence of the NBL 20. In this regard, the inventor has appreciated that the presence of the n-buried layer 20 at the drain potential (VCC) contributes to the equipotential line crowding of
The present invention provides DEMOS transistors that facilitate improved breakdown voltage ratings without increasing Rdson or the epitaxial silicon layer thickness. The invention thus facilitates use of such devices in new applications requiring higher supply voltages, including but not limited to full or half H-bridge configurations as in
As illustrated in
The transistor T2 also comprises an n-well 108 implanted with n-type dopants (e.g., arsenic, phosphorus, etc.) in the epitaxial silicon 106, as well as a p-well or p-body 118 formed within the n-well 108, with field oxide (FOX) structures 134 formed in the upper portion of the epitaxial silicon 106 between transistor source, drain, and back gate terminals. Other implementations are possible, for example, where the back gates may be connected directly to the sources, where the isolation structures are formed using shallow trench isolation (STI) techniques, deposited oxide, etc., wherein all such alternative implementations having a first buried layer (e.g., NBL 120) separated from the DEMOS by a second buried layer of opposite conductivity type (e.g., PBL 130), with a diode (e.g., diode 148) coupled therebetween are contemplated as falling within the scope of the invention and the appended claims.
The transistor T2 comprises a p-type back gate 152 and an n-type source 154 formed in the p-well 118, as well as an n-type drain 156 formed in the n-well, wherein a portion of the n-well 108 between the drain 150 and the p-well 118 provides a drain extension or drift region. Thus, the transistor T3 includes an extended drain comprising the drift region of the n-well 108 and the drain 56. In operation, the back gate 152 may, but need not, be coupled to the source 154 in an overlying metalization layer (not shown). In one possible alternative implementation, the field oxide (FOX) structure 134 between the back gate 152 and the source 154 may be omitted for direct connection of the back gate 152 to the source 154. A gate structure is formed over a channel portion of the p-well 118 and over a portion of a drift region of the n-well 108, including a gate oxide 140 and a gate electrode 142, where a portion of the gate electrode 142 is further extended over a field oxide structure 134 above the drain extension or drift region of the n-well 108 in the exemplary transistor T2.
In a half or full H-bridge load driver configuration, the drain 156 is connected to the supply voltage VCC together with the cathode of the internal or external diode 148, and the source 154 is coupled to the load at the intermediate node N1 in
The lower n-buried layer potential and the presence of the intervening p-buried layer result in much different electric field profiles in the device during the off-state compared with those of conventional high-side drivers.
In a preferred implementation, the dopant concentration of the n-buried layer 120 is higher than that of the p-buried layer 130, so as to inhibit on-state punch-thru current from flowing between the p-well 118 and the p-type substrate 104 when the n-well 108 is depleted between the p-well 118 and the p-buried layer 130. In one example, the p-buried layer 130 has a peak dopant concentration of about 5E15 cm−3 or more and about 5E17 cm−3 or less, wherein the n-buried layer 120 has a peak concentration of about 1E17 cm−3 or more and about 1E20 cm−3 or less, with the n-buried layer peak concentration being higher than that of the p-buried layer 130.
Another aspect of the invention provides methods for semiconductor device fabrication, which may be used to fabricate devices having NMOS and/or PMOS extended drain transistors having improved breakdown voltage performance. In this aspect of the invention, a first buried layer of a first conductivity type is implanted in a substrate, and a second buried layer of a second conductivity type is then implanted. An epitaxial silicon layer is formed over the implanted substrate, and a drain-extended MOS transistor is formed above the second buried layer in the epitaxial silicon layer, where an extended drain of the transistor is separated from the first buried layer. The method may include forming a diode in the epitaxial layer to couple the first buried layer to the extended drain, or forming external connections to the first buried layer and the extended drain for coupling an external diode therebetween.
While the exemplary method 202 is illustrated and described below as a series of acts or events, it will be appreciated that the present invention is not limited by the illustrated ordering of such acts or events. For example, some acts may occur in different orders and/or concurrently with other acts or events apart from those illustrated and/or described herein, in accordance with the invention. In addition, not all illustrated steps may be required to implement a methodology in accordance with the present invention. Furthermore, the methods according to the present invention may be implemented in association with the fabrication of devices which are illustrated and described herein as well as in association with other devices and structures not illustrated.
The method 202 begins at 204 in
At 210 in
At 214 in
At 216, n-wells are implanted in the epitaxial silicon 106 in the high-side region 112, which may then be thermally diffused at 218. A deep n-type diffusion (e.g., a sinker) is formed in the epitaxial silicon 106, either before or after the n-well formation at 216, to provide connection to the n-buried layer 120. In
At 220, p-wells or p-base regions 118 are implanted into portions of the transistor n-well 108, which may be followed by another thermal diffusion anneal (not shown).
At 222 in
With the patterned gate structure formed, LDD and/or MDD implants may be performed and sidewall spacers are formed at 230 along the lateral sidewalls of the patterned gate structure. At 232, the source and drain regions 154 and 156 are implanted with n-type dopants, and the back gate 152 is implanted with p-type dopants at 234, wherein any suitable masks and implantation processes may be used in forming the n-type source 154 and drain 156 and the p-type back gate 152. Silicide, metalization, and other back-end processing are then performed at 236 and 238, respectively, to create conductive metal silicide material 172 and conductive plugs 178 (e.g., tungsten, etc.) in a first pre-metal dielectric (PMD) layer 174 over the gate 142, source 154, drain 156, and back-gate 152 of the DEMOS transistor T2, as well as over the p-type anode 118 a and the n-type cathode 118 a in the case of an internal diode 148 (
Further metalization layers (not shown) are then formed to create a multilevel interconnect routing structure at 240, after which the method 202 ends at 240 in
Although the invention has been illustrated and described with respect to one or more implementations, alterations and/or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular regard to the various functions performed by the above described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component or structure which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising”.
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|U.S. Classification||257/339, 257/E27.016, 257/336, 257/E29.063, 257/344, 257/328, 257/335, 257/342|
|Cooperative Classification||H01L27/0629, H01L29/7816, H01L29/66689, H01L29/7818, H01L29/1083|
|European Classification||H01L29/66M6T6F14L2, H01L27/06D4V, H01L29/78B4, H01L29/78B4A2, H01L29/10F2B2|
|Jul 14, 2004||AS||Assignment|
Owner name: TEXAS INSTRUMENTS INCORPORATED, TEXAS
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:PENDHARKAR, SAMEER;REEL/FRAME:015575/0018
Effective date: 20040708
|Aug 24, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Aug 25, 2014||FPAY||Fee payment|
Year of fee payment: 8