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Publication numberUS7187085 B2
Publication typeGrant
Application numberUS 10/853,492
Publication dateMar 6, 2007
Filing dateMay 26, 2004
Priority dateJan 31, 2001
Fee statusPaid
Also published asUS6759332, US20020100983, US20040217480
Publication number10853492, 853492, US 7187085 B2, US 7187085B2, US-B2-7187085, US7187085 B2, US7187085B2
InventorsLawrence A. Clevenger, Larry A. Nesbit
Original AssigneeInternational Business Machines Corporation
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Semiconductor device including dual damascene interconnections
US 7187085 B2
Abstract
A method (and structure) of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.
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Claims(19)
1. A semiconductor device, comprising:
a semiconductor substrate;
a dual damascene structure formed in at least one dielectric film formed on the semiconductor substrate, including a relatively narrow first structure and a relatively wider second structure, which is separate from said first structure;
a liner formed in said relatively narrow first structure and said relatively wider second structure, such that a lower portion of said relatively narrow first structure is substantially filled by said liner; and
a metallization formed over said liner to completely fill said relatively wider second structure.
2. The semiconductor device of claim 1, wherein said liner comprises at least one of tungsten, aluminum, titanium nitride, Ta, TaN, Ru, other refractory metals, and combinations thereof.
3. The semiconductor device of claim 1, wherein said metallization comprises at least one of copper, Al, Au, Ag, and combinations thereof.
4. A semiconductor device, comprising:
a semiconductor substrate;
a dual damascene structure formed in at least one dielectric film formed on the semiconductor substrate, including a relatively narrow first structure and a relatively wider second structure, which is separate from said first structure;
a first material formed in said relatively narrow first structure and said relatively wider second structure, such that a lower portion of said relatively narrow first structure is substantially filled by said first material; and
a second material formed over said first material to completely fill said relatively wider second structure.
5. The semiconductor device of claim 4, wherein said first material comprises at least one of tungsten, aluminum, titanium nitride, Ta, TaN, Ru, other refractory metals and combinations thereof.
6. The semiconductor device of claim 4, wherein said second material comprises any of copper, Al, Au, Ag, and combinations thereof.
7. A semiconductor device comprising:
a semiconductor substrate;
a dielectric formed on said semiconductor substrate, said dielectric including:
a plurality of troughs formed on said dielectric; and
a contact that includes one of said plurality of troughs and a lower portion of a dual damascene structure, wherein said contact is separate from said plurality of troughs, other than said one of said plurality of troughs;
a liner that lines said plurality of troughs, completely fills said lower portion of said contact, and forms a liner layer above said dielectric; and
a metal that completely fills said plurality of troughs, which are lined, to a level coplanar wit an upper surface of said liner layer.
8. The semiconductor device of claim 7, wherein said dielectric comprises at least one of tetraethylorthosilicate (TEOS) oxide, silane oxide, low K polymer dielectric, CVD dielectric, porous dielectric, and combinations thereof.
9. The semiconductor device of claim 7, further comprising:
a first metal level formed on the semiconductor substrate; and
a second metal level formed on said metal that completely fills said plurality of troughs and is formed on said upper surface of said liner layer.
10. The semiconductor device of claim 7, wherein said liner comprises at least one of tungsten, aluminum, titanium nitride, Ta, TaN, Ru, other refractory metals, and combinations thereof.
11. The semiconductor device of claim 7, wherein said metal comprises at least one of copper, Al, Au, Ag, and combinations thereof.
12. A semiconductor device comprising:
troughs formed in a dielectric between first and second metal levels, said dielectric being formed on a substrate, and said troughs including a slot;
a contact formed in said dielectric that includes a lower portion of a dual damascene structure, wherein said contact is separate from said troughs;
a liner that completely fills said lower portion and that forms a liner layer above an upper surface of said dielectric; and
a metal that completely fills said troughs including said slot to a level coplanar with said upper surface of said dielectric.
13. The semiconductor device of claim 12, wherein said dielectric comprises at least one of tetraethylorthosilicate (TEOS) oxide, silane oxide, a low K polymer dielectric, CVD dielectric, porous dielectric, and combinations thereof.
14. The semiconductor device of claim 12, wherein said liner comprises at least one of tungsten, aluminum, titanium nitride, Ta, TaN, Ru, other refractory metals, and combinations thereof.
15. The semiconductor device of claim 12, wherein said metal comprises at least one of copper, Al, Au, Ag, and combinations thereof.
16. The semiconductor device of claim 1, wherein said liner comprises tungsten.
17. The semiconductor device of claim 1, wherein said liner is tungsten.
18. The semiconductor device of claim 1, wherein said metallization comprises copper.
19. The semiconductor device of claim 1, wherein said metallization is copper.
Description

The present Application is a Divisional Application of U.S. patent application Ser. No. 09/772,920, filed on Jan. 31, 2001, now U.S. Pat. No.6,759,332.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method (and resultant structure) of forming a semiconductor device, and more particularly to a method (and resultant structure) of forming a dual damascene interconnection.

2. Description of the Related Art

Currently, it is difficult to adequately line contacts for copper filling at contact dimensions below 280 nm, and to line contacts reliably below contact opening sizes of less than 320 nm. This presents a major challenge to dynamic random access memory back-end-of-line (DRAM BEOL) processing that would like to migrate to a copper back-end in the near future.

Additionally, in the conventional methods, there are a large number of types of conducting materials that must be implemented in a BEOL process.

Further, the conventional methods require a separate method for producing DRAM BEOL and a separate method for producing the logic BEOL so that different manufacturing lines are required to produce either DRAM or logic with the same type and number of tools.

Finally, the conventional methods typically attempt to fill substantially both small and large structures with copper, thereby requiring additional and costly processing such as multiple CVD and advanced PVD diffusion barriers and liners which enable Cu plating.

SUMMARY OF THE INVENTION

In view of the foregoing problems, drawbacks, and disadvantages of the conventional methods, it is an object of the present invention to provide a structure and method for producing a dual damascene structure.

Another object is to fill small contacts with a highly reliable material and fill wider metal lines with, for example, copper.

In a first aspect of the present invention, a method of forming an interconnect on a semiconductor substrate, includes forming a relatively narrow first structure in a dielectric formed on a semiconductor substrate, forming a relatively wider second structure in the dielectric formed on the semiconductor substrate, forming a liner in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and forming a metallization over the liner to completely fill the second structure.

In a second aspect, a method of forming an interconnect on a semiconductor substrate, includes forming a contact, including a slot, in a dielectric formed on a semiconductor substrate, forming troughs in the dielectric, thereby to form a dual damascene structure (it is noted that the order in which these levels are masked and etched may be reversed), depositing a thick conducting material on the dielectric, depositing a metal over the conducting material to completely fill the slot and metal troughs, removing the metal either to the conducting material or both the metal and the conducting material simultaneously back to the dielectric, and selectively removing the conducting material.

In a third aspect, a semiconductor device, includes a semiconductor substrate, a dual damascene structure formed in at least one dielectric film formed on the semiconductor substrate, including a relatively narrow first structure and a relatively wider second structure, a liner formed in the first and second structures such that the first structure is substantially filled and the second structure is substantially unfilled, and a metallization formed over the liner to completely fill the second structure.

With the unique and unobvious advantages of the present invention, small contacts (e.g., C1 contacts) can be filled with a highly reliable material and wider metal lines (e.g., C1 slots) with, for example, copper.

Further, the invention provides a method for easily and adequately lining contacts for copper filling at contact dimensions below 280 nm, and to lining contacts reliably below contact opening sizes of less than 320 nm.

Moreover, the invention provides a method which is advantageous from a manufacturing perspective in which the number of types of conducting materials that must be implemented in a BEOL process is minimized. Also, the same method can be used to make the DRAM BEOL and the logic BEOL. Thus, a same manufacturing line can produce either DRAM or logic devices with the same type and number of tools.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which:

FIG. 1 is a schematic diagram of a cross-section of a semiconductor chip according to the present invention;

FIG. 2 is a cross-section of the chip (a wafer) after a tungsten fill;

FIG. 3 is a cross-section of the semiconductor chip showing copper being formed over the tungsten;

FIG. 4 is a cross-section of the semiconductor chip showing a removal of the copper over the tungsten other than that in a trough (e.g., C1 slot); and

FIG. 5 is a wafer cross-section after selective removal of the tungsten, either by selective etching or chemical mechanical polishing (CMP).

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

Referring now to the drawings, and more particularly to FIGS. 1–5, there are shown preferred embodiments of the method and structures according to the present invention.

Generally, the invention is directed to a method (and resulting structure) of forming a dual damascene interconnection.

Referring to FIG. 1, in a first step of the method, contacts 101 (e.g., C1 contacts between first and second metal levels M0 and M1), including C1 slots 102 are etched into the C1/M1 dielectric 103. This dielectric can be either a nitride/oxide, low K polymer or a combination thereof.

In step 2, M1 troughs 104 are etched into the C1/M1 TEOS (or dielectric) 103. Preferably, such an etch is performed by reactive ion etching (RIE). It is noted that the order in which these levels are masked and etched may be reversed.

Thus, FIG. 1 shows a cross-section of a semiconductor chip, showing the C1 contacts, C1 slots, and M1 troughs etched into the C1/M1 TEOS or dielectric to form a dual damascene structure.

Referring now to FIG. 2, a thick (e.g., <2000 Å) reliable conducting material(s), such as a chemical vapor-deposited (CVD) metal (e.g., tungsten) is deposited on the wafer. Instead of tungsten, titanium nitride, aluminum, etc. may be used. For illustration purposes only, it will be assumed that tungsten is employed.

The thickness of the conducting material(s) is adjusted so as to substantially completely fill the relatively small C1 contacts. The small C1 contacts are typically from about 2000 to about 8000 Å deep. Thus, FIG. 2 shows the wafer after the tungsten fill.

Thereafter, as shown in FIG. 3, a metal like copper or any other conducting material different from the first metal deposition, is then deposited over the tungsten by plating, physical vapor deposition, or chemical vapor deposition to completely fill the relatively wider lines (e.g., C1 slots and the M1 metal troughs).

Thereafter in FIG. 4, the copper is polished back by CMP either to the contact fill material (e.g., tungsten) or both the copper and the contact fill material are simultaneously polished back to the dielectric.

Then, as shown in FIG. 5, the tungsten is selectively removed, either by a selective etch, or by a selective CMP. Subsequent dielectric films and metal layers may be deposited on the resulting structure. Thus, FIG. 5 illustrates the wafer cross-section after selective removal of the tungsten, either by selective etch or CMP.

With the unique and unobvious features of the present invention, small contacts (e.g., C1 contacts) can be filled with a highly reliable material (e.g., CVD metal) and wider metal lines (e.g., C1 slots) can be filled with, for example, copper. Thus, the invention fills the substantially smaller areas/structures with CVD metal, and the wider areas/structures are filled with copper metallization.

Further, the invention easily and adequately lines contacts for copper filling at contact dimensions below 280 nm, and lines contacts reliably below contact opening sizes of less than 320 nm.

Moreover, the invention provides a method which is advantageous from a manufacturing perspective in which the number of types of conducting materials that must be implemented in a BEOL process is minimized. Also, the same method can be used to make the DRAM BEOL and the logic BEOL. Thus, a same manufacturing line can produce either DRAM or logic devices with the same type and number of tools.

While the invention has been described in terms of preferred embodiments, those skilled in the art will recognize that the invention can be practiced with modification within the spirit and scope of the appended claims.

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Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7402883 *Apr 25, 2006Jul 22, 2008International Business Machines Corporation, Inc.Back end of the line structures with liner and noble metal layer
US7585765 *Aug 15, 2007Sep 8, 2009International Business Machines CorporationFormation of oxidation-resistant seed layer for interconnect applications
US7704884Apr 11, 2008Apr 27, 2010Micron Technology, Inc.Semiconductor processing methods
US7745324Jan 9, 2009Jun 29, 2010International Business Machines CorporationInterconnect with recessed dielectric adjacent a noble metal cap
US7915168Mar 10, 2010Mar 29, 2011Micron Technology, Inc.Semiconductor processing methods
US8232195Jun 12, 2008Jul 31, 2012International Business Machines CorporationMethod for fabricating back end of the line structures with liner and seed materials
US8440567Feb 23, 2011May 14, 2013Micron Technology, Inc.Semiconductor processing methods
US8735292Apr 8, 2013May 27, 2014Micron Technology, Inc.Semiconductor processing methods
US9034664May 16, 2012May 19, 2015International Business Machines CorporationMethod to resolve hollow metal defects in interconnects
US20070246792 *Apr 25, 2006Oct 25, 2007Chih-Chao YangMethod for fabricating back end of the line structures with liner and seed materials
US20070275557 *Aug 15, 2007Nov 29, 2007International Business Machines CorporationFormation of oxidation-resistant seed layer for interconnect applications
US20080242082 *Jun 12, 2008Oct 2, 2008Chih-Chao YangMethod for fabricating back end of the line structures with liner and seed materials
US20090258485 *Apr 11, 2008Oct 15, 2009Junting LiuSemiconductor Processing Methods
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US20100176514 *Jan 9, 2009Jul 15, 2010International Business Machines CorporationInterconnect with recessed dielectric adjacent a noble metal cap
Classifications
U.S. Classification257/774, 257/E21.02, 257/752, 257/E21.57, 257/E21.585, 438/233, 257/751, 257/E23.161, 257/763, 257/761, 257/758, 257/762
International ClassificationH01L23/48, H01L21/3205, H01L23/532, H01L21/768, H01L23/522, H01L23/52
Cooperative ClassificationH01L23/53228, H01L2924/0002, H01L21/76877, H01L21/76843
European ClassificationH01L21/768C4, H01L21/768C3B, H01L23/532M1C
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