|Publication number||US7190079 B2|
|Application number||US 11/265,302|
|Publication date||Mar 13, 2007|
|Filing date||Nov 3, 2005|
|Priority date||Jul 3, 2003|
|Also published as||US7008871, US20050001325, US20060076685, WO2005004234A1|
|Publication number||11265302, 265302, US 7190079 B2, US 7190079B2, US-B2-7190079, US7190079 B2, US7190079B2|
|Inventors||Panayotis C. Andricacos, Shyng-Tsong Chen, John M. Cotte, Hariklia Deligianni, Mahadevaiyer Krishnan, Wei-Tsu Tseng, Philippe M. Vereecken|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (32), Non-Patent Citations (5), Referenced by (36), Classifications (27), Legal Events (3)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This application is a divisional of U.S. patent application Ser. No. 10/611,931, filed Jul. 3, 2003, now U.S. Pat. No. 7,008,871, issued Mar. 7, 2006.
The present invention relates to fabricating patterned copper structures and particularly patterned copper structures wherein the copper is in contact with a liner material. The present invention is concerned with selectively capping the copper employing selective etching and/or selective electroplating. The present invention also relates to apparatus suitable for depositing the capping material on the copper.
Copper wiring for on-chip interconnections, currently fabricated by a (single or dual) Damascene integration approach, is surrounded on the sides and at the bottom by a liner or barrier (e.g.—Ta, W, nitrides thereof and multilayers thereof), whose role is to prevent Cu diffusion into the interlayer dielectric material (ILD) (e.g. SiO2 and low k dielectrics) and to provide excellent adhesion between the Cu conductor and the ILD. Additionally, the liner prevents the diffusion of O2 or other substances into the Cu conductor. The diffusion of such materials would cause chemical changes to the conductor and adversely affect its resistivity and other properties. Recent work by Hu et al., “Electromigration in On-Chip Single/Dual Damascene Cu Interconnections”, J. Electrochem. Soc., 149, G408 (2002); and Hu et al. “Scaling Effect on Electromigration in On-Chip Cu Wiring”, Proc. IITC (1999) p. 267; C.-K. Hu and S. Reynolds, “CVD Cu Interconnections and Electromigration”, Electrochem. Soc. Proc. Vol. 97–25 (1997), p. 1514, has shown that surface diffusion is a predominant way for Cu to electromigrate; it is therefore evident that good adhesion of the Cu conductor to the liner helps suppress electromigration. Materials such as Ta/TaN bilayers have been shown to be excellent diffusion barriers and to provide excellent adhesion and electromigration suppression. For example, see Edelstein, et al. “A High Performance Liner for Copper Damascene Interconnects,” Proceedings of the 2001 IEEE IITC, pp 9–11, (2001).
Providing an appropriate capping material on the copper suppresses electromigration of the copper conductor material. Although Damascene integration provides a facile way to protect Cu conductors on the side and at the bottom, it does not provide a satisfactory solution at the top of the structure.
Capping the top of these structures poses more of a challenge due to the desire for planarity between layers in fabricating a multilayer interconnects structure. Electroless plating has been demonstrated to selectivity deposit on the interconnect; however, this approach offers only a limited set of materials and lacks planarity between layers. Also, presently, to suppress Cu diffusion or electromigration from the top, a blanket film of a material such as SixNy is deposited after the Cu and surrounding ILD is planarized and before the subsequent layer of metallization is built (
Accordingly, the present invention relates to improved methods and apparatus for selectively capping copper.
The present invention relates to addressing problems of capping of copper. In particular, one aspect of the present invention is concerned with a method for fabricating patterned copper structures which comprises providing a dielectric material on a substrate; providing at least one trench/via in the dielectric material; providing a liner on the bottom and sidewalls of the at least one trench/via and on horizontal surfaces of the dielectric material in the vicinity of the at least one trench/via; depositing copper in the at least one trench/via/via on the liner for filling the trench/via; selectively electroetching or selectively chemically etching the copper to recess the copper with respect to the top surfaces of the structure.
Another aspect of the present invention relates to a patterned copper structure comprising a substrate having a dielectric material on the substrate wherein the dielectric material contains at least one trench/via therein;
located on the bottom and sidewalls a liner of the at least one trench/via;
copper located on the liner in the at least one trench/via; and a
capping structure located directly on top of the copper and comprising a first metal or alloy layer selected from the group consisting of Co, CoP, CoWP, CoMoP, Ni, NiP, NiWP, NiMoP, NiW, NiMo, CoMo, NiFe, CoFe, NiFeP, CoFeP, NiB, CoB, NiFeB, CoFeB, NiCo, NiCoP, NiCoB, NiWB, NiMoB, CoWB, CoMoB, CoV, NiV, CoFeV, NiFeV, NiCoV, NiCoFeV, NiCo; and a second metal or alloy layer selected from the group consisting of Ru, Re, Pt, Pd, Rh, Os, NiPd, CoPd, Pb, Sn, Sb, and In.
A still further aspect of the present invention related to a patterned upper structure comprising a substrate having a dielectric material on the substrate wherein the dielectric material contains at least one trench/via/via therein;
located on the bottom and sidewalls a liner of the at least one trench/via;
copper located on the liner in the at least one trench/via; and a capping structure located on top of the copper and comprising a layer containing ruthenium, rhenium, osmium, and rhodium.
A still further aspect of the present invention relates to a method for fabricating patterned copper structures, which comprises providing a dielectric material on a substrate;
providing a liner on the bottom and sidewalls of the at least one trench/via and on horizontal surfaces of the dielectric material in the vicinity of the at least one trench/via;
depositing copper in the at least one trench/via/via on the liner for filling the trench/via;
selectively recessing copper;
selectively electroplating a metal or alloy on the copper.
The present invention also relates to the products obtained by the above disclosed methods.
An even further aspect of the present invention relates to apparatus for etching or plating which comprises a wafer-holding fixture that permits wafers rotation and another fixture, substantially parallel to the first, which is segmented in right-shaped segments that can be electrically isolated from each other, and capable of ejecting the electrolyte in doughnut shaped flow regions of progressively increasing or decreasing internal diameter.
A still further aspect of the present invention relates to an apparatus for etching or plating comprising a wafer-holding fixture that permits wafers rotation and another ring-shaped fixture, substantially parallel to the first, whose area can be changed such that the electrochemical reactions on the wafer are localized.
Other objectives and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein it is shown and described only the preferred embodiments of the invention simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature and not as restrictive.
According to the present invention, copper in the presence of a liner material is selectively capped employing selective etching and/or selective electroplating. According to the present invention, the planarization process employed in a typical process to create a copper structure, such as a damascene or double damascene process, is stopped prior to removal of the liner material. According to the present invention the selective etching and/ selectively is carried out in the presence of the liner. This makes possible the elimination of bridging and shorts upon the subsequent removal of the liner.
As illustrated in
As will be discussed hereinbelow in detail, the copper surface is selectively etched and/or selectively plated with a capping material. In order to fabricate an understanding of the present invention, reference will be made to the frames.
As illustrated in
A liner or barrier layer 12 is employed along the bottom and sidewalls of the copper wiring 10 between the copper wiring 10 and dielectric 16. The liner 12 also is present on the horizontal surface of the dielectric 16 in the vicinity of the copper wiring 10.
According to one aspect of the present invention, as shown in
The liner 12 is typically Ta, TaN, W, WN or multiple layers of two or more of these materials.
Copper recessing in the presence of the liner 12 on the horizontal surfaces can be done without a mask by chemical etching, or by electrochemical etching with the latter preferably under electropolishing conditions. Chemical etching in the presence of a liner material exhibits an advantage as compared to the absence of a liner in that all features are at the same electrical potential thereby enhancing the uniformity of the chemical etching process. An example of a chemical etching process comprises using a solution containing about 0.5% vol. acetic acid and 0.3% vol. hydrogen peroxide. Initially the solution is primed by dissolving about 8–9 ppm (mg/l) of Cu+2 in the bath and then the actual experimental parts are run. The solution is pumped at a rate of about 1 to about 10 liters/min and then sprayed unsubmerged onto the wafer. Typical dissolution rates are about 300 to about 1000 Angstroms/min of recessed copper. Electroetching is preferred since it has better selectivity. Cu can be electroetched preferentially to the typical liner materials such as Ta, TaN, W, WN, Ti and TiN. In contrast, chemical etching solutions, although suitable may not be as compatible universally with liner materials.
Copper electroetching is preferably carried out under mass transport controlled—or electropolishing—conditions in order to improve wafer scale uniformity and to prevent crystallographic etching. Experiments carried out in concentrated phosphoric acid at different values of the applied voltage confirmed that at the higher voltages (6V), the onset of mass transport control causes the surface of the Cu to be flat in contrast to lower voltages (4V) where AFM analysis revealed the existence of considerable roughness resulting from crystallographic etching (
Typical etching processing can employ as electrolyte, about 50%–100% H3PO4 and a voltage of about 1–20 volts. Typical etching parameters are disclosed in the table below.
As illustrated in
In another ruthenium electroplating example, a commercially available bath available under the trade designation “Ruthenex SP” from Enthone OMI is modified to contain about 4 g/l Ru to about 12 g/l Ru. In addition, the “Ruthenex SP” bath contains relatively large amounts of Mg salts and relatively small amounts of Ni. Mg deposits with the Ru metal and acts as a stress reducer. The conditions for the elctrodepositing with the baths containing Mg and/Ni are similar to those discussed above.
In a further example, Rh is deposited from a bath commercially available under the trade designation “Rhodex 100” from Enthone OMI. The bath contains about 4 g/l of Rh and a stress reducer additive. Rhodium is typically deposited at a current density of less than 10 mA/cm with current efficiencies of greater than about 30%. It is preferred to control the deposition rate to a current density in order to control deposit roughness.
Examples of other suitable metals or alloys employed as capping layers are Ta, TaN, TaSiN, W, WN, Co, COP, CoMoP, Ni, NiP, NiWP, NiMoP, NiW, NiMo, CoMo, NiFe, CoFe, NiFeP, CoFeP, NiB, CoB, NiFeB, CoFeB, NiCo, NiCoP, NiCoB, NiWvB, NiMoB, CoWB, CoMoB, CoV, NiV, CoFeV, NiFeV, NiCoV, NiCoFeV, NiCo, Ru, Re, Pt, Pd, Rh, Os, NiPd, CoPd, Pb, Sn, Sb, and In.
Some preferred structures according to the present invention include Cu conducting lines capped by a first metal or alloy selected from the group of Co, CoP, CoWP, CoMoP, Ni, NiP, NiWP, NiMoP, NiW, NiMo, CoMo, NiFe, CoFe, NiFeP, CoFeP, NiB, CoB, NiFeB, CoFeB, NiCo, NiCoP, NiCoB, NiWB, NiMoB, CoWB, CoMoB, CoV, NiV, CoFeV, NiFeV, NiCoV, NiCoFeV, NiCo and a second metal or alloy selected from the group of Ru, Re, Pt, Pd, Rh, Os, NiPd, CoPd, Pb, Sn, Sb, and In.
Next as shown in
In an alternative process sequence, the capping is selectively deposited by electroless or exchange plating. According to the materials employed, after the copper 10 is recessed, the liner on the horizontal surfaces is removed such as by CMP and a seed layer, such as palladium or tin-palladium catalyst is deposited selectively on the copper 10, followed by the selective plating on the seeded surfaces. Selective seeding on the copper and avoidance of seeding on the dielectric can be achieved by rinsing with a solution containing a complexing agent, such as EDTA, or sodium citrate to remove any Pd ions adsorbed on the dielectric without removing the Pd metal on the copper surface as disclosed, for instance, in U.S. Pat. No. 6,503,834 B1, disclosure of which is incorporated herein by reference. For example, see column 3, lines 64 and 65 thereof. An example of an electroless deposition for ruthenium can be found in Ramani et al., “Synthesis and Characterization of Hydrous Ruthenium Oxide-Carbon Supercapacitor”, J. Electrochem. Soc., 148 (4), A374–380 (2001), disclosure of which being incorporated herein by reference. For instance, a typical bath employed contains about 0.014 Molar ruthenium chloride, about 0.27 Molar sodium hypophosphite, about 0.014 Molar diammonium hydrogen citrate and about 0.07 Molar ammonium oxalate. The pH of the bath is typically maintained at about 9.5 by the periodic addition of sodium hydroxide and the temperature of the bath is typically kept about 90° C.
Another sequence according to the present invention is shown in
As shown in
It is preferred that the total thickness of the barrier or capping assembly is at most about 10% of the thickness of the Cu conductor and typically at least about 50 angstroms and more typically about 50 angstroms to about 500 angstroms.
The preferred process of the present invention employ selective recessing of the copper such as illustrated in
It is apparent that the integration sequences described above are not limited to the fabrication of Cu interconnect structures. Any other device using Cu metallization and requiring recessing of the Cu can make use of the approaches described above. Such devices may include thick Cu inductors, capacitors whose metal plates are made of Cu, MEMS devices such as MEMS switches and MEMS resonators, and the like.
The electroetching according to the present invention was initially conducted in an apparatus described by Datta et al. in U.S. Pat. No. 5,486,282, equipped with a fountain-type nozzle having a width of about 10% of the wafer diameter and a length that is greater than the wafer diameter. The wafer (anode) was placed facing down over the fountain nozzle/cathode; inter electrode distance was filled with electrolyte (concentrated phosphoric acid). The potential was applied between the anode/wafer and the cathode/nozzle either in direct or pulsating form. As shown in Table 1 below, the amount of Cu recess can be controlled by such parameters as duty cycle of the applied voltage wave form and nozzle speed. However, the amount of recessed Cu at the center of the wafer was considerably less than the amount at the edge of the wafer. Accordingly, a preferred aspect of this invention is to overcome the ‘terminal effect.’
In both selective electroetching and electroplating processes described in this invention, the role of the liner is to distribute the current from the electrical contacts on the wafer periphery to all Cu surfaces on the wafer where these reactions occur. Because of the appreciable resistance of the liner the current is lower towards the center of the wafer; it has to cross an increasingly resistive path as it flows from the wafer edge inwards. This problem, called ‘terminal effect,’ is aggravated as the wafer size increases (e.g. from 200 mm to 300 mm) and as feature size decreases driving a decrease in the thickness, hence an increase in the resistance, of the liner.
In order to circumvent the terminal effect, a few types of tools are preferred. In one, the nozzle used is circular and its diameter is considerably smaller than the diameter of the wafer (see
In another type of tool, the terminal effect can be overcome by segmenting the counter electrode and independently controlling each segment to give uniform deposition or etching. Electrolyte then can be supplied locally in a fountain type of flow between the electrodes forming an electrochemical cell only in the desired regions. One method of locally filling the inter-electrode gap would be to use a manifold type electrode illustrated in
All publications and patent applications cited in this specification are herein incorporated by reference, and for any and all purposes, as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference.
The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention but, as mentioned above, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the invention concept as expressed herein, commensurate with the above teachings and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5374454||Feb 4, 1993||Dec 20, 1994||International Business Machines Incorporated||Method for conditioning halogenated polymeric materials and structures fabricated therewith|
|US5380546||Jun 9, 1993||Jan 10, 1995||Microelectronics And Computer Technology Corporation||Multilevel metallization process for electronic components|
|US5486282||Nov 30, 1994||Jan 23, 1996||Ibm Corporation||Electroetching process for seed layer removal in electrochemical fabrication of wafers|
|US5723387||Jul 22, 1996||Mar 3, 1998||Industrial Technology Research Institute||Method and apparatus for forming very small scale Cu interconnect metallurgy on semiconductor substrates|
|US5865984||Jun 30, 1997||Feb 2, 1999||International Business Machines Corporation||Electrochemical etching apparatus and method for spirally etching a workpiece|
|US6017803||Jun 24, 1998||Jan 25, 2000||Chartered Semiconductor Manufacturing, Ltd.||Method to prevent dishing in chemical mechanical polishing|
|US6130157 *||Jul 16, 1999||Oct 10, 2000||Taiwan Semiconductor Manufacturing Company||Method to form an encapsulation layer over copper interconnects|
|US6157081 *||Mar 10, 1999||Dec 5, 2000||Advanced Micro Devices, Inc.||High-reliability damascene interconnect formation for semiconductor fabrication|
|US6171960||Apr 9, 1998||Jan 9, 2001||United Microelectronics Corp.||Method of fabricating copper interconnection|
|US6191029 *||Sep 9, 1999||Feb 20, 2001||United Silicon Incorporated||Damascene process|
|US6239021 *||Sep 5, 2000||May 29, 2001||Advanced Micro Devices, Inc.||Dual barrier and conductor deposition in a dual damascene process for semiconductors|
|US6251774||Apr 28, 1999||Jun 26, 2001||Mitsubishi Denki Kabushiki Kaisha||Method of manufacturing a semiconductor device|
|US6258713||Dec 3, 1999||Jul 10, 2001||United Microelectronics Corp.||Method for forming dual damascene structure|
|US6261963||Jul 7, 2000||Jul 17, 2001||Advanced Micro Devices, Inc.||Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices|
|US6274499||Nov 19, 1999||Aug 14, 2001||Chartered Semiconductor Manufacturing Ltd.||Method to avoid copper contamination during copper etching and CMP|
|US6281127||Apr 15, 1999||Aug 28, 2001||Taiwan Semiconductor Manufacturing Company||Self-passivation procedure for a copper damascene structure|
|US6333560||Jan 14, 1999||Dec 25, 2001||International Business Machines Corporation||Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies|
|US6339258||Jul 2, 1999||Jan 15, 2002||International Business Machines Corporation||Low resistivity tantalum|
|US6350687||Mar 18, 1999||Feb 26, 2002||Advanced Micro Devices, Inc.||Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film|
|US6368484||May 9, 2000||Apr 9, 2002||International Business Machines Corporation||Selective plating process|
|US6372633 *||Jul 8, 1998||Apr 16, 2002||Applied Materials, Inc.||Method and apparatus for forming metal interconnects|
|US6395607||Jun 9, 1999||May 28, 2002||Alliedsignal Inc.||Integrated circuit fabrication method for self-aligned copper diffusion barrier|
|US6406996 *||Sep 30, 2000||Jun 18, 2002||Advanced Micro Devices, Inc.||Sub-cap and method of manufacture therefor in integrated circuit capping layers|
|US6441492||Sep 28, 2000||Aug 27, 2002||James A. Cunningham||Diffusion barriers for copper interconnect systems|
|US6524957 *||Sep 17, 2001||Feb 25, 2003||Agere Systems Inc.||Method of forming in-situ electroplated oxide passivating film for corrosion inhibition|
|US6528409 *||Apr 29, 2002||Mar 4, 2003||Advanced Micro Devices, Inc.||Interconnect structure formed in porous dielectric material with minimized degradation and electromigration|
|US6537913 *||Jun 29, 2001||Mar 25, 2003||Intel Corporation||Method of making a semiconductor device with aluminum capped copper interconnect pads|
|US6670274||Oct 1, 2002||Dec 30, 2003||Taiwan Semiconductor Manufacturing Company||Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure|
|US6696758 *||Nov 7, 2002||Feb 24, 2004||Intel Corporation||Interconnect structures and a method of electroless introduction of interconnect structures|
|US6730982 *||Mar 30, 2001||May 4, 2004||Infineon Technologies Ag||FBEOL process for Cu metallizations free from Al-wirebond pads|
|US20010019892 *||Feb 15, 2001||Sep 6, 2001||Naoki Komai||Process for fabricating a semiconductor device|
|US20040224474 *||May 5, 2003||Nov 11, 2004||Hans-Joachim Barth||Single mask MIM capacitor top plate|
|1||Hu et al., "Chemical Vapor Deposition Copper Interconnections and Electromigration," Elecrochemical Society Proceedings, vol. 97-25, 1997, pp. 1514-1522.|
|2||Hu et al., "Electromigration in On-Chip Single/Dual Damascene Cu Interconnections," Journal of The Electrochemical Society, 149 (7) 2002, pp. G408-G415.|
|3||Ramani et al., "Synthesis and Characterizaiton of Hydrous Ruthenium Oxide-Carbon Supercapacitors," Journal of The Electrochemical Society, 148 (4), 2001, pp. A374-A380.|
|4||Rosenberg et al., "Scaling Effect on Electromigration in On-Chip Cu Wiring," IEEE, 1999, pp. 267-269.|
|5||Uzoh et al., "A High Performance Liner for Copper Damascene Interconnects," IEEE, 2001, pp. 9-11.|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7544601 *||Nov 14, 2006||Jun 9, 2009||Dongbu Hitek Co., Ltd.||Semiconductor device and a method for manufacturing the same|
|US7619310 *||Nov 3, 2006||Nov 17, 2009||Infineon Technologies Ag||Semiconductor interconnect and method of making same|
|US7727890||Dec 10, 2007||Jun 1, 2010||International Business Machines Corporation||High aspect ratio electroplated metal feature and method|
|US7737560 *||May 18, 2006||Jun 15, 2010||Infineon Technologies Austria Ag||Metallization layer for a power semiconductor device|
|US7951714||Feb 16, 2010||May 31, 2011||International Business Machines Corporation||High aspect ratio electroplated metal feature and method|
|US8119525||Feb 26, 2008||Feb 21, 2012||Applied Materials, Inc.||Process for selective growth of films during ECP plating|
|US8242600||May 19, 2009||Aug 14, 2012||International Business Machines Corporation||Redundant metal barrier structure for interconnect applications|
|US8404582||May 4, 2010||Mar 26, 2013||International Business Machines Corporation||Structure and method for manufacturing interconnect structures having self-aligned dielectric caps|
|US8432031 *||Dec 22, 2009||Apr 30, 2013||Western Digital Technologies, Inc.||Semiconductor die including a current routing line having non-metallic slots|
|US8592306||Jun 21, 2012||Nov 26, 2013||International Business Machines Corporation||Redundant metal barrier structure for interconnect applications|
|US8623761||Sep 6, 2012||Jan 7, 2014||International Business Machines Corporation||Method of forming a graphene cap for copper interconnect structures|
|US8779574||Apr 1, 2013||Jul 15, 2014||Western Digital Technologies, Inc.||Semiconductor die including a current routing line having non-metallic slots|
|US8802563||Sep 4, 2012||Aug 12, 2014||International Business Machines Corporation||Surface repair structure and process for interconnect applications|
|US8823176||Oct 8, 2008||Sep 2, 2014||International Business Machines Corporation||Discontinuous/non-uniform metal cap structure and process for interconnect integration|
|US8889546||Aug 31, 2012||Nov 18, 2014||International Business Machines Corporation||Discontinuous/non-uniform metal cap structure and process for interconnect integration|
|US8895433||Jan 6, 2014||Nov 25, 2014||Samsung Electronics Co., Ltd.||Method of forming a graphene cap for copper interconnect structures|
|US9299638||Dec 6, 2012||Mar 29, 2016||Globalfoundries Inc.||Patterning transition metals in integrated circuits|
|US9299639||Jan 4, 2013||Mar 29, 2016||Globalfoundries Inc.||Patterning transition metals in integrated circuits|
|US9318413||Oct 29, 2013||Apr 19, 2016||Globalfoundries Inc.||Integrated circuit structure with metal cap and methods of fabrication|
|US9318414||Oct 29, 2013||Apr 19, 2016||Globalfoundries Inc.||Integrated circuit structure with through-semiconductor via|
|US9472450 *||May 10, 2012||Oct 18, 2016||Samsung Electronics Co., Ltd.||Graphene cap for copper interconnect structures|
|US9659869 *||Sep 28, 2012||May 23, 2017||Intel Corporation||Forming barrier walls, capping, or alloys /compounds within metal lines|
|US20070128847 *||Nov 14, 2006||Jun 7, 2007||Hong Ji H||Semiconductor device and a method for manufacturing the same|
|US20070267749 *||May 18, 2006||Nov 22, 2007||Matthias Stecher||Metallization layer for a power semiconductor device|
|US20080108219 *||Nov 3, 2006||May 8, 2008||Frank Huebinger||Semiconductor interconnect and method of making same|
|US20090020883 *||Jul 17, 2008||Jan 22, 2009||Kayo Nomura||Semiconductor device and method for fabricating semiconductor device|
|US20090148677 *||Dec 10, 2007||Jun 11, 2009||International Business Machines Corporation||High aspect ratio electroplated metal feature and method|
|US20090212334 *||May 6, 2009||Aug 27, 2009||Ji Ho Hong||Semiconductor device and a method for manufacturing the same|
|US20090215264 *||Feb 26, 2008||Aug 27, 2009||Yu Jick M||Process for selective growth of films during ecp plating|
|US20090223832 *||Jan 7, 2009||Sep 10, 2009||Interuniversitair Microelektronica Centrum Vzw (Imec)||Method and Apparatus for Preventing Galvanic Corrosion in Semiconductor Processing|
|US20100084766 *||Oct 8, 2008||Apr 8, 2010||International Business Machines Corporation||Surface repair structure and process for interconnect applications|
|US20100084767 *||Oct 8, 2008||Apr 8, 2010||International Business Machines Corporation||Discontinuous/non-uniform metal cap structure and process for interconnect integration|
|US20100295181 *||May 19, 2009||Nov 25, 2010||International Business Machines Corporation||Redundant metal barrier structure for interconnect applications|
|US20130224948 *||Feb 28, 2012||Aug 29, 2013||Globalfoundries Inc.||Methods for deposition of tungsten in the fabrication of an integrated circuit|
|US20130299988 *||May 10, 2012||Nov 14, 2013||International Business Machines Corporation||Graphene cap for copper interconnect structures|
|WO2013169424A1 *||Apr 8, 2013||Nov 14, 2013||International Business Machines Corporation||Graphene cap for copper interconnect structures|
|U.S. Classification||257/774, 438/652, 257/E21.585, 257/758, 257/E21.175, 438/669, 257/762|
|International Classification||H01L21/288, H01L23/48, H01L23/52, H01L21/768, H01L21/00, H01L29/40|
|Cooperative Classification||H01L21/76883, H01L21/6708, H01L21/76849, H01L21/7685, H01L21/76846, H01L21/76874, H01L21/2885|
|European Classification||H01L21/67S2D8W4, H01L21/768C3S4, H01L21/768C3B4, H01L21/768C3B8, H01L21/288E, H01L21/768C4, H01L21/768C3C|
|Oct 18, 2010||REMI||Maintenance fee reminder mailed|
|Mar 13, 2011||LAPS||Lapse for failure to pay maintenance fees|
|May 3, 2011||FP||Expired due to failure to pay maintenance fee|
Effective date: 20110313