US 7191316 B2 Abstract A system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions that both index a same set of registers is provided. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit includes a first counter arranged to increment for each of the plurality of single precision floating point instructions forwarded down a pipeline; a second counter arranged to increment for each of the plurality of double precision floating point instructions forwarded down the pipeline; a first mask register and a second mask register. The first mask register is updated by each of the single precision floating point instructions forwarded and the second mask register is updated by each of the double precision floating point instructions forwarded.
Claims(22) 1. A method for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions in a fetch group without conflict in registers,
wherein the method utilizes a decode unit comprising:
a first counter arranged to increment for at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded;
a second counter arranged to increment for at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions forwarded;
a first mask register indexed by single precision registers, wherein the first mask register is updated by at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded; and
a second mask register indexed by double precision registers, wherein the second mask register is updated by at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions forwarded,
wherein the method comprises:
decoding at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions;
evaluating the at least one of the plurality of the single precision floating point instructions and the at least one of the double precision floating point instructions in the fetch group, wherein the evaluating is based on values of the first counter and the second counter and based on a value of an entry in the first mask register and a value of an entry in the second mask register; and
based on the evaluating, processing the at least one of the plurality of the single precision floating point instructions and the at least one of the plurality of the double precision floating point instructions.
2. The method of
determining values of the first counter and the second counter;
determining whether the at least one of the plurality of the single precision floating point instructions is younger than a double precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the single precision floating point instructions references a destination register of the double precision floating point instruction; and
if the first and the second counters are non-zero, determining whether the value of the entry in the second mask register corresponding to the source register of the single precision floating point instruction is indexed with a particular logic value.
3. The method of
forwarding the at least one of the plurality of the single precision floating point instructions;
incrementing the first counter; and
updating a value of an entry in the first mask register.
4. The method of
committing the at least one of the plurality of the single precision floating point instructions; and
decrementing the first counter, and if the first counter reaches zero, clearing the first mask register.
5. The method of
6. The method of
determining values of the first counter and the second counter;
determining whether the at least one of the plurality of the double precision floating point instructions is younger than a single precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the double precision floating point instructions references a destination register of the single precision floating point instruction; and
if the first and the second counters are non-zero, determining whether the value of the entry in the first mask register corresponding to the source register of the double precision floating point instruction is indexed with a particular logic value.
7. The method of
forwarding the at least one of the plurality of the double precision floating point instructions;
incrementing the second counter; and
updating a value of an entry in the second mask register.
8. The method of
committing the at least one of the plurality of the double precision floating point instructions; and
decrementing the second counter, and if the second counter reaches zero, clearing the second mask register.
9. The method of
10. The method of
11. The method of
12. The method of
13. The system of
14. A method for handling a plurality of single precision and a plurality of double precision floating point instructions without conflict in registers,
wherein the method utilizes a decode unit comprising:
a first counter arranged to increment for at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded;
a second counter arranged to increment for at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions forwarded;
a first mask register indexed by single precision registers, wherein the first mask register is updated by at least one of the plurality of single precision floating point instructions forwarded, without regard to double precision floating point instructions forwarded; and
a second mask register indexed by double precision registers, wherein the second mask register is updated by at least one of the plurality of double precision floating point instructions forwarded, without regard to single precision floating point instructions fowarded,
wherein the method comprises:
step for decoding at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions;
step for evaluating the at least one of the plurality of the single precision floating point instructions and the at least one of the plurality of the double precision floating point instructions in the fetch group, wherein the step for evaluating is based on values of the first counter and the second counter and based on indexing of the first mask register and the second mask register; and
based on the step for evaluating, step for processing the at least one of the plurality of the single precision floating point instructions and the at least one of the plurality double precision floating point instructions.
15. The method of
step for determining values of the first counter and the second counter;
step for determining whether the at least one of the plurality of the single precision floating point instructions is younger than a double precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the single precision floating point instructions references a destination register of the double precision floating point instruction; and
if the first and the second counters are non-zero, step for determining whether the value of the entry in the second mask register corresponding to the source register of the single precision floating point instruction is indexed with a particular logic value.
16. The system of
step for forwarding the at least one of single precision floating point instructions;
step for incrementing the first counter; and
step for updating a value of an entry in the first mask register.
17. The system of
step for committing the at least one of the single precision floating point instructions; and
step for decrementing the first counter, and if the first counter reaches zero, step for clearing the first mask register.
18. The system of
19. The method of
step for determining values of the first counter and the second counter;
step for determining whether the at least one of the plurality of the double precision floating point instructions is younger than a single precision floating point instruction in the fetch group and whether a source register of the at least one of the plurality of the double precision floating point instructions references a destination register of the single precision floating point instruction; and
if the first and the second counters are non-zero, step for determining whether the value of the entry in the first mask register corresponding to the source register of the double precision floating point instruction is indexed with a particular logic value.
20. The system of
step for forwarding the at least one of the double precision floating point instructions;
step for incrementing the second counter; and
step for updating a value of an entry in the second mask register.
21. The system of
step for committing the at least one of the double precision floating point instructions; and
step for decrementing the second counter, and if the second counter reaches zero, step for clearing the second mask register.
22. The method of
Description A typical computer system includes at least a microprocessor and some form of memory. The microprocessor has, among other components, arithmetic, logic, and control circuitry that interpret and execute instructions necessary for the operation and use of the computer system. An instruction executed by the typical computer system shown in Depending on the type of instruction being executed, storage areas or registers are specified that contain data or an address to a location that contains data used in executing the instruction. Additional registers are used to facilitate the execution of instructions in a program, e.g., instruction registers, program counters, pipe stages registers (i.e., intermediary registers along the pipeline). The facilitation of floating point registers is particularly important to the proper execution of floating point instructions. First, a floating point number is a number that is carried out to a certain number of decimal positions. For example, the number pi is 3.14159265 when carried out to the eighth decimal place. Decimal numbers may be represented in binary form as a floating point number. Floating point numbers are stored in three parts: the sign (plus or minus), the significant (or mantissa), and the exponent (or order of magnitude of the significant). The exponent determines the decimal place to which the decimal point “floats.” Floating point numbers may be single or double precision. Typically, a single precision floating point number requires thirty-two bits to be represented. The first bit is the sign, the next eight bits form the exponent, and the remaining twenty-three bits form the significant. A double precision floating point number typically requires sixty-four bits to be represented. The first bit is the sign, the next eleven bits form the exponent; and the remaining fifty-two bits form the significant. In a typical microprocessor as shown in Floating point instructions may manipulate (e.g., move, convert, or perform arithmetic, trigonometric, logarithmic, or exponential operations) both single precision and double precision floating point numbers. Floating point instructions that operate on floating point numbers typically include two source registers in which the source operands are stored and a destination register in which the result of the operation is written. Floating point operations operate specifically on single or double precision floating point numbers and are considered single precision floating point operations or double precisions floating point operations, respectively. Because double precision floating point numbers require two registers for each source operand, floating point operations may execute improperly if source registers are not read from appropriate sources, e.g., floating point working register file (FWRF), floating point architectural register file (FARF), data cache unit (DCU), or bypass. For example, Code Sample 1: Floating Point Operations1 fpop 2 fpop 3 fpop In line 1 of Code Sample In In line 3 of Code Sample Typically, in handling floating point operations, a rename unit and issue unit work together to ensure that the appropriate data is forwarded (i.e., from FWRF, FARF, cache, by-pass, or the like) to the single precision and double precision floating point instructions when issued thereby avoiding potential conflict. The additional logic necessitated by a rename unit and issue unit for handling single precision and double precision floating point instructions often results in complicated logic, substantially increasing the power and design time. In general, one aspect of the invention involves a system for handling a plurality of single precision floating point instructions and double precision floating point instructions. The system comprises a decode unit arranged to decode, stall, and forward at least one of the plurality of single precision and at least one of the plurality of double precision floating point instructions in a fetch group. The decode unit comprises a first counter arranged to increment for at least one of the plurality of single precision floating point instructions forwarded; a second counter arranged to increment for at least one of the plurality of double precision floating point instructions forwarded; a first mask register indexed by double precision registers, wherein the first mask register is updated by at least one of the plurality single precision floating point instructions forwarded; and a second mask register indexed by single precision registers, wherein the second mask register is updated by at least one of the plurality double precision floating point instructions forwarded. In general, one aspect of the invention involves a method for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions in an instruction stream (i.e., fetch groups forwarded by the fetch unit). The method comprises decoding at least one of the plurality of single precision floating point instructions and at least one of the plurality of the double precision floating point instructions and evaluating the at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions, and based on the evaluating, processing the at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions. The evaluating is based on values of a first counter and a second counter and based on indexing of a first mask register and a second mask register. In general, one aspect of the invention involves a method for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions in an instruction stream. The method comprises step for decoding at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions, step for evaluating the at least one of the single precision floating point instructions and the at least one of the plurality of the double precision floating point instructions, and based on the step for evaluating, step for processing the at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions. The step for evaluating is based on values of a first counter and a second counter and based on indexing of a first mask register and a second mask register. In general, one aspect of the invention relates to a system for handling a plurality of single precision floating point instructions and a plurality of double precision floating point instructions. The system comprises means for decoding, stalling and forwarding, at least one of the plurality of the single precision floating point instructions and at least one of the plurality of the double precision floating point instructions. The means for decoding, stalling and forwarding comprises a first means for counting at least one of the plurality of single precision floating point instructions forwarded; a second means for counting at least one of the plurality of double precision floating point instructions forwarded; a first means for indexing a first mask register, wherein the first mask register is updated by at least one of the plurality of single precision floating point instructions forwarded down the pipeline; and a second means for indexing a second mask register, wherein the second mask register is updated by at least one of the plurality of double precision floating point instructions forwarded down the pipeline. Other aspects and advantages of the invention will be apparent from the following description and the appended claims. Exemplary embodiments of the invention will now be described in detail with references to the accompanying figures. Like elements in various figures are denoted by like reference numerals throughout the figures for consistency. In the following detailed description of the invention, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the invention. Embodiments of the invention relate to a method for handling a mix of single precision and double precision floating point instructions in a program or instruction stream. The SP counter ( In addition to the SP counter ( For example, bit-zero ( Bit-zero ( Furthermore, bit-zero ( Otherwise, a criteria is applied depending on the floating point instructions (Step On the other hand, if the criteria does apply, the floating point instruction and all younger instructions, i.e., instructions that are after the current floating point instruction in a fetch group, are stalled (Step After the appropriate mask register is cleared (Step In one embodiment, the criteria used to determine whether a floating point instruction is stalled involves examining floating point instructions in view of the SP counter, the DP counter, the SP mask, and DP mask. The floating point instruction is stalled in the four following instances, according to the criteria. 1) In the fetch group, there is a double precision floating point instruction where at least one of double precision floating point instruction's source registers when used to index into the thirty-two bit SP mask register reveals a logic 1 in the source register's corresponding position. For example, the double precision floating point instruction has Register 2) In the fetch group, there is a single precision floating point instruction where at least one of the single precision floating point instruction's source registers when used to index into the sixteen bit DP mask register reveals a logic 1 in the source register's corresponding position. For example, the single precision instruction has Register 3) In the fetch group, there is a single precision instruction that is “younger” than a double precision instruction in the same fetch group. The younger single precision floating point instruction references as source operand the destination register of the “older” double precision instruction in the same fetch group. In this case, the decode unit forwards all instructions older to the single precision floating point instruction in the fetch group, but stalls on the single precision floating point instruction and all instructions younger to the single precision floating point instruction in the fetch group. 4) In the fetch group, there is a double precision instruction that is “younger” than a single precision instruction in the same fetch group. The younger double precision floating point instruction references as source operand the destination register of the “older” single precision instruction in the same fetch group. In this case, the decode unit forwards all instructions older to the double precision floating point instruction in the fetch group, but stalls on the double precision floating point instruction and all instructions younger to the double precision floating point instruction in the fetch group. One skilled in the art will understand that the term “younger” and “older” is used to describe the ordering of an instruction relative to another instruction. 2: “Younger” Floating Point Operations1 fpop(N)- - - 2 fpop (N+1)- - - For example, in Code Sample One skilled in the art will also understand that the criteria may include a variety of factors that satisfy the scenarios For example, the criteria may involve a “counter boolean,” a “mask boolean,” and a “operand boolean.” The operand boolean includes an “ordinal boolean” and a “reference boolean.” Table 1 shows exemplary combination of evaluations of the boolean values and a result in accordance with one embodiment of the invention.
The counter boolean, in the first column of Table 1, indicates whether both a DP counter and SP counter are zero. According to the counter boolean, the operand boolean and/or mask boolean are evaluated. If the counter boolean is evaluated to be zero (“true”), only the operand boolean is used to determine whether the floating point instruction is forwarded or stalled. The operand boolean, in the second column of Table 1, is formed by the reference and ordinal booleans. The reference boolean indicates whether a single precision destination register of a floating point instruction is referenced by one or more double precision source registers or a double precision destination register of a floating point instruction is referenced by one or more single precision source registers. The ordinal boolean indicates whether the floating point operation referencing the destination register is a “younger” floating point instruction. Both the reference boolean and the ordinal boolean must be evaluated as “true” to potentially stall a floating point instruction. For example, In another example shown in However, if the counter boolean is evaluated as “false,” i.e., the SP counter and/or DP counter is/are non-zero, then the operand boolean and/or the mask boolean determine if the floating point instruction is stalled or forwarded. The mask boolean evaluates to “true,” if, and only if, the source register referenced by a floating point instruction when indexed into the appropriate mask register reveals logic 1 at the corresponding position (or positions) (i.e., a single precision source register referenced by floating point instruction when indexed into the DP mask register reveals a logic 1 at the corresponding position or a double precision source register referenced by floating point instruction when indexed into the SP mask register reveals a logic 1 at any one of its two corresponding positions). Therefore, as shown in Table 1, a floating point instruction is stalled in two ways according to a criteria. First, if the operand boolean is “true,” meaning both the ordinal boolean and the reference boolean are evaluated as “true,” the floating point instruction is stalled. Second, if the counter boolean is “false” and mask boolean is “true,” the floating point instruction is stalled. All other combinations of the criteria result in the floating point instruction being forwarded. In applying the invention to Code Sample Assuming that a SP counter and DP counter are zero, a floating point operation in line 1 of Code Sample In line 2 of Code Sample The SP and DP counters are now non-zero, and neither floating point operations has committed. In this case, the criteria is applied to the floating point operation in line 3 of Code Sample Advantages of the present invention may include one or more of the following. In one or more embodiments, the design effort and complexity of logic typically required in a rename and issue units to handle floating point instructions is minimized by a single precision mask register and counter, and a double precision mask register and counter in the decode unit. The cycle time in the rename and issue unit may be reduced by allowing the decode unit to stall on a mix of double precision and single precision floating point instructions in an instruction stream. While the invention has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the invention as disclosed herein. Accordingly, the scope of the invention should be limited only by the attached claims. Patent Citations
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