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Publication numberUS7200832 B2
Publication typeGrant
Publication dateApr 3, 2007
Filing dateMar 26, 2004
Priority dateMar 26, 2004
Fee statusPaid
Also published asUS20050229132
Publication numberUS 7200832 B2, US 7200832B2, US-B2-7200832, US7200832 B2, US7200832B2
InventorsDerrick Sai Tang Butt, Bruce C Cochrane, Hui Yin Seto, William W Lau, Thomas E Mccarthy
Original AssigneeLsi Logic Corp
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
Macro cell for integrated circuit physical layer interface
US 7200832 B2
Abstract
A macro cell is provided for an integrated circuit design having an input-output (IO) region with a plurality of IO buffer cells physically dispersed with other cells in IO slots along an interface portion of the IO region. The macro cell includes a plurality of macro cell IO signal slots that are physically dispersed so as to substantially align with the IO buffer cells in the interface portion. The macro cell also includes an interface definition having a plurality of interface IO signal nets, which are routed to corresponding ones of the plurality of macro cell signal slots. The macro cell is adapted to be instantiated as a unit in the integrated circuit design.
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Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5036473 *Oct 4, 1989Jul 30, 1991Mentor Graphics CorporationMethod of using electronically reconfigurable logic circuits
US6449760 *Nov 30, 2000Sep 10, 2002Lsi Logic CorporationPin placement method for integrated circuits
US6734046 *Oct 3, 2002May 11, 2004Reshape, Inc.Method of customizing and using maps in generating the padring layout design
US6763028 *Jan 10, 2001Jul 13, 2004Fujitsu LimitedTransceiver apparatus
US6823501 *Oct 3, 2002Nov 23, 2004Reshape, Inc.Method of generating the padring layout design using automation
US6894530 *Apr 28, 2003May 17, 2005Lattice Semiconductor CorporationProgrammable and fixed logic circuitry for high-speed interfaces
US6903575 *Apr 28, 2003Jun 7, 2005Lattice Semiconductor CorporationScalable device architecture for high-speed interfaces
US6941536 *Sep 6, 2001Sep 6, 2005Hitachi, Ltd.Method for identifying semiconductor integrated circuit device, method for manufacturing semiconductor integrated circuit device, semiconductor integrated circuit device and semiconductor chip
US6970966 *Mar 7, 2002Nov 29, 2005Italtel S.P.A.System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
US20030236939 *May 16, 2003Dec 25, 2003Bendik KlevelandHigh-speed chip-to-chip communication interface
US20050097493 *Oct 29, 2003May 5, 2005Lsi Logic CorporationGate reuse methodology for diffused cell-based IP blocks in platform-based silicon products
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7369069 *Jul 7, 2006May 6, 2008Hitachi, Ltd.Semiconductor device
US7557607May 14, 2007Jul 7, 2009Xilinx, Inc.Interface device reset
US7573295May 14, 2007Aug 11, 2009Xilinx, Inc.Hard macro-to-user logic interface
US7626418 *May 14, 2007Dec 1, 2009Xilinx, Inc.Configurable interface
US7702840May 14, 2007Apr 20, 2010Xilinx, Inc.Interface device lane configuration
US8051228 *Nov 13, 2008Nov 1, 2011International Business Machines CorporationPhysical interface macros (PHYS) supporting heterogeneous electrical properties
US8332552 *Nov 13, 2008Dec 11, 2012International Business Machines CorporationSupporting multiple high bandwidth I/O controllers on a single chip
Classifications
U.S. Classification326/30
International ClassificationG06F17/50
Cooperative ClassificationG06F17/5045
European ClassificationG06F17/50D
Legal Events
DateCodeEventDescription
Jun 6, 2014ASAssignment
Owner name: LSI CORPORATION, CALIFORNIA
Free format text: CHANGE OF NAME;ASSIGNOR:LSI LOGIC CORPORATION;REEL/FRAME:033102/0270
Effective date: 20070406
May 8, 2014ASAssignment
Free format text: PATENT SECURITY AGREEMENT;ASSIGNORS:LSI CORPORATION;AGERE SYSTEMS LLC;REEL/FRAME:032856/0031
Effective date: 20140506
Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG
Sep 27, 2010FPAYFee payment
Year of fee payment: 4
Jul 23, 2004ASAssignment
Owner name: LSI LOGIC CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BUTT, DERRICK SAI TANG;COCHRANE, BRUCE C.;SETO, HUI YIN;AND OTHERS;REEL/FRAME:015601/0485;SIGNING DATES FROM 20040714 TO 20040717