|Publication number||US7205673 B1|
|Application number||US 11/283,044|
|Publication date||Apr 17, 2007|
|Filing date||Nov 18, 2005|
|Priority date||Nov 18, 2005|
|Publication number||11283044, 283044, US 7205673 B1, US 7205673B1, US-B1-7205673, US7205673 B1, US7205673B1|
|Inventors||Jayanthi Pallinti, Dilip Vijay, Hemanshu Bhatt, Sey-Shing Sun, Hong Ying, Chiyi Kao|
|Original Assignee||Lsi Logic Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (11), Referenced by (2), Classifications (48), Legal Events (4) |
|External Links: USPTO, USPTO Assignment, Espacenet|
Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing
US 7205673 B1
A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.
1. A bond pad structure for engaging a gold ball, comprising:
a layer of copper;
a layer of aluminum disposed above the copper layer and configured for engagement with the gold ball, wherein said layer of aluminum is doped only with Si.
2. The bond pad structure as recited in claim 1, wherein the layer of aluminum is doped such that the growth of intermetallic compound (IMC) is controlled to a nominal level in spite of high tensile stresses on the wafer.
3. The bond pad structure as recited in claim 1, wherein the layer of aluminum is doped with Si, thereby reducing the overall tensile stresses, wherein the gold-aluminum interface is altered, thus enabling a uniform and thin intermetallic compound (IMC) formation.
The present invention generally relates to wire bonds, and more specifically relates to pad structures and passivation schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing.
It has been observed that some post wire bonded dies that have undergone Cu/Low-K metallization show signature of ‘open’ fails after several hours of HTS (high temperature storage). Failure analysis on such parts shows cracks at the interface of intermetallic compound (IMC) and gold bond. FIG. 1 shows an X-SEM of a bonded die with IMC cracking.
Historically, IMC cracking in Au—Al wirebonds have been attributed to several causes including contamination on the surface of the Al-pads, incompatible film properties of the Al-films, presence of halides in the molding compounds, excessive levels of voids in the molding compounds and poorly optimized bonding and molding conditions. However, in the case of wire bond devices with Cu/Low-k metallization, the cracking of IMC persists despite careful control of the above-mentioned factors. Through a cumulative set of deductive experiments and use advanced analytical techniques, it has been determined that the cracking of IMC wire bond devices with Cu/Low-k metallization is a strong function of the tensile stresses in the film. It has been found that the unusually high tensile stresses generated in the Cu/Low-K stacks can drive excessive diffusion of Al into the Au bonds leading to very thick and Al-rich IMC phases. The unstable Al-rich phases eventually undergo reverse phase transformations to Au-rich phases; the associated volume change (very large˜30%) in such phase transformations can result in voiding and eventual cracking of the IMC. The way to prevent this issue then is to tailor the stresses in the Cu/Low-K stacks so that the Al-diffusion rates are controlled to a low enough level that the stable Au-rich phases are formed preferably when compared to Al-rich phases. This will prevent any tendencies for phase transformation in the system.
The present invention addresses the stress related issues that cause the IMC cracking and methods to eliminate the IMC cracking by controlling the macro stresses in the wafer. During Cu/Low-k processing, it has been found that there is cumulative stress buildup in wafers due to intrinsic stresses in metal and dielectric films and due to various thermal cycles. Thermal stresses are generated due to a mismatch between the temperature coefficients of expansion between metal, dielectric films and substrate, as illustrated in the following table:
||Coefficient of thermal expansion for
||various film (per degree Celsius)
Intrinsic stresses are generated during deposition. The stress state can be evaluated with freestanding films (or films on flexible substrates). Some general observations regarding stresses in thin films is provided below for reference:
- 1. Tensile: typically, an upward curve is generated due to repulsive forces between tapered grains in zone 1 structure formed by evaporation or sputtering with high pressure and low power.
- 2. Compressive: typically, a downward curve is generated due to atomic peening of crystal grains by reflected neutrals during sputtering.
- 3. Metals with Body Centered Cubic (BCC) structure, e.g., W, Ta (mostly refractory metals), can have extremely high compressive stress due to open lattice that allows atoms to be easily displaced.
- 4. Metals with Face Centered Cubic (FCC) structure, e.g., Cu, Al and Au (most noble metals), have very little intrinsic stress (low re-crystallization temperature).
- 5. Dielectric (CVD) films can be tensile or compressive depending on deposition parameters, e.g., temperature and plasma power.
The macro stresses in the wafer can be measured by measuring the bow in the wafer and translating the values to stresses through Poisson's equations. In general, a positive wafer gap during the wafer bow measurement indicates tensile stresses in the wafers and a negative wafer gap indicates compressive stresses. FIG. 2 shows a normalized graph with stress accumulated on a wafer at various stages in the BEOL Cu/Low-k wafer processing.
It is evident from FIG. 2 that the tensile stresses on the wafer keep increasing in the wafer as more and more metallization steps are added to the film and the wafer experiences maximum tensile stress during deposition of the Aluminum pad. Aluminum and copper are known to contribute to tensile stresses, while the dielectric films can contribute to tensile or compressive stresses based on deposition conditions like temperature, time, etc. As the tensile stresses in the wafer build-up, the wafer can bow due to the warpage or macro stress distributions from the center to the edge of the wafer. However, the local stress distribution in the Aluminum pads is harder to characterize.
OBJECTS AND SUMMARY
An object of an embodiment of the present invention is to reduce or eliminate IMC cracking in post wire bonded dies.
Another object of an embodiment of the present invention is to provide a bond pad structure which reduces or eliminates IMC cracking in post wire bonded dies.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation.
A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.
BRIEF DESCRIPTION OF THE DRAWINGS
The organization and manner of the structure and operation of the invention, together with further objects and advantages thereof, may best be understood by reference to the following description, taken in connection with the accompanying drawing, wherein:
FIG. 1 is an X-SEM of a bonded die, showing IMC cracking;
FIG. 2 is a graph which shows normalized stress on a wafer at various metallization steps in the BEOL Cu/Low-k steps, wherein a positive value for stress indicates tensile stress and a negative value for stress indicates compressive stress; and
FIG. 3 provides a cross-sectional view of a dual passivation layer scheme which is in accordance with the present invention.
While the invention may be susceptible to embodiment in different forms, there are shown in the drawings, and herein will be described in detail, specific embodiments of the invention. The present disclosure is to be considered an example of the principles of the invention, and is not intended to limit the invention to that which is illustrated and described herein.
FIG. 3 illustrates a dual passivation layer scheme which is in accordance with an embodiment of the present invention. The scheme includes oxide layers 100, barrier layers 102, a barrier layer 106, a layer of copper 108, another barrier layer 110, and a layer of aluminum 112 which is configured for bonding to a gold ball (see FIG. 1) and hence includes a pad interface 114. In accordance with the present invention, the aluminum layer includes a dopant so that the IMC formed is more uniform and the thickness is controlled in order to reduce or eliminate the IMC cracking issues in wire bonded parts during temperature cycling. Specifically, layer 112 is either:
- 1. Doped with, for example, 1–2 atomic % of Mg. The Mg along with the aluminum causes a thin Al—Mg layer to be provided at the pad interface 114. This thin film controls the growth of IMC to a more nominal level in spite of high tensile stresses on the wafer. Instead of Mg, Pd or Si can be used as a dopant with the Aluminum.
- 2. Doped with elements like Cu or Si, which reduces the overall tensile stresses and also slightly alters the gold-aluminum interface (pad interface 114), thus enabling a uniform and thin IMC formation. This reduces or eliminates any voiding or cracking which would otherwise form at the wire bond interface (see FIG. 1).
The present invention provides that a dopant or a combination of dopants is used, with the aluminum, to both control the tensile stresses and also slightly alter the gold-aluminum interface, thus enabling a uniform and thin IMC formation, thereby reducing or eliminating any voiding or cracking which would otherwise occur at the wire bond interface.
While embodiments of the present invention are shown and described, it is envisioned that those skilled in the art may devise various modifications of the present invention without departing from the spirit and scope of the appended claims.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US6110823 *||Jun 3, 1998||Aug 29, 2000||Formfactor, Inc.||Method of modifying the thickness of a plating on a member by creating a temperature gradient on the member, applications for employing such a method, and structures resulting from such a method|
|US6232662 *||Jul 2, 1999||May 15, 2001||Texas Instruments Incorporated||System and method for bonding over active integrated circuits|
|US6384486 *||Dec 10, 1999||May 7, 2002||Texas Instruments Incorporated||Bonding over integrated circuits|
|US6413851 *||Jun 12, 2001||Jul 2, 2002||Advanced Interconnect Technology, Ltd.||Method of fabrication of barrier cap for under bump metal|
|US6507041 *||Jan 2, 2001||Jan 14, 2003||Nichia Chemical Industries, Ltd.||Gallium nitride-based III-V group compound semiconductor|
|US6515373 *||Dec 28, 2000||Feb 4, 2003||Infineon Technologies Ag||Cu-pad/bonded/Cu-wire with self-passivating Cu-alloys|
|US6703069 *||Sep 30, 2002||Mar 9, 2004||Intel Corporation||Under bump metallurgy for lead-tin bump over copper pad|
|US6854637 *||Feb 20, 2003||Feb 15, 2005||Freescale Semiconductor, Inc.||Wirebonding insulated wire|
|US6936923 *||May 16, 2002||Aug 30, 2005||Taiwan Semiconductor Manufacturing Co., Ltd.||Method to form very a fine pitch solder bump using methods of electroplating|
|US6998690 *||Jul 1, 2003||Feb 14, 2006||Nichia Corporation||Gallium nitride based III-V group compound semiconductor device and method of producing the same|
|US20060091536 *||Nov 2, 2004||May 4, 2006||Tai-Chun Huang||Bond pad structure with stress-buffering layer capping interconnection metal layer|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US8101871||May 26, 2009||Jan 24, 2012||Lsi Corporation||Aluminum bond pads with enhanced wire bond stability|
|EP2256803A1 *||May 25, 2010||Dec 1, 2010||LSI Corporation||Aluminum bond pads with enhanced wire bond stability|
| || |
|U.S. Classification||257/786, 257/E25.029, 257/738, 257/762, 257/690, 257/784, 257/E23.078, 257/E23.021, 257/E23.159, 257/E23.024, 257/E25.011, 257/737, 257/E23.025, 257/735|
|International Classification||H01L23/48, H01L23/52, H01L29/40|
|Cooperative Classification||H01L2924/01013, H01L2924/01012, H01L2224/48453, H01L2924/01073, H01L2924/01075, H01L2224/04042, H01L2224/45144, H01L2224/48624, H01L24/45, H01L2224/48507, H01L2924/01082, H01L2924/01079, H01L23/53219, H01L2224/48463, H01L2924/01074, H01L2924/01022, H01L24/05, H01L2924/01046, H01L24/48, H01L2924/01327, H01L2924/0105, H01L2224/05624, H01L2224/05147, H01L2924/04953, H01L2924/01014, H01L2924/01029, H01L2924/01033, H01L2924/01019|
|European Classification||H01L24/48, H01L24/05, H01L23/532M1A2|
|Oct 8, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Dec 23, 2008||CC||Certificate of correction|
|Dec 27, 2005||AS||Assignment|
Owner name: LSI LOGIC CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RANGANATHAN, RAMASWAMY;LOW, QWAI;REEL/FRAME:017396/0884
Effective date: 20051212
|Nov 18, 2005||AS||Assignment|
Owner name: LSI LOGIC CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PALLINTI, JAYANTHI;VIJAY, DILIP;BHATT, HEMANSHU;AND OTHERS;REEL/FRAME:017266/0501
Effective date: 20051114