Search Images Maps Play YouTube News Gmail Drive More »
Sign in
Screen reader users: click this link for accessible mode. Accessible mode has the same essential features but works better with your reader.

Patents

  1. Advanced Patent Search
Publication numberUS7216285 B2
Publication typeGrant
Application numberUS 10/039,585
Publication dateMay 8, 2007
Filing dateJan 4, 2002
Priority dateNov 9, 2001
Fee statusPaid
Also published asUS7418648, US8161359, US20030093752, US20060161832
Publication number039585, 10039585, US 7216285 B2, US 7216285B2, US-B2-7216285, US7216285 B2, US7216285B2
InventorsHongyi Hubert Chen
Original AssigneeMarvell International Ltd.
Export CitationBiBTeX, EndNote, RefMan
External Links: USPTO, USPTO Assignment, Espacenet
System and method for generating cyclic redundancy check
US 7216285 B2
Abstract
A method for generating a Cyclic Redundancy Check (CRC) in a system including steps of creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate, and programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero. The step of programming is based on a pre-selected polynomial key word.
Images(5)
Previous page
Next page
Claims(80)
1. A method for generating a Cyclic Redundancy Check (CRC) in a system comprising the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero,
wherein the step of programming is based on a pre-selected polynomial key word.
2. The method as recited in claim 1, further comprising:
using a first set of multiplexers in conjunction with a first set of selection inputs for selecting at least one input for shifting data to a next shift register of the plurality of registers,
wherein the at least one input is a member of a set of inputs that includes an output from an adjacent logic gate and a straight shift input from an adjacent register of the plurality of registers.
3. The method as recited in claim 1, further comprising:
using a second set of multiplexers in conjunction with a second set of selection inputs for selecting at least one input to a corresponding logic gate,
wherein the at least one input is a member of a set of inputs that includes a primary input and a feedback input.
4. The method as recited in claim 1, further comprising:
using a second set of multiplexers in conjunction with a second set of selection inputs for selecting a final output from among output from the plurality of registers.
5. The method as recited in claim 1, wherein the plurality of registers are shift registers.
6. The computer program of claim 5, wherein each of the M logically combining steps comprises the step of exclusive or'ing the respective stored first signal with a corresponding one of the input signal and the selected signal.
7. A method for generating a Cyclic Redundancy Check (CRC) in a system, comprising the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero,
wherein the step of programming is based on a pre-selected polynomial key word, and
wherein the step of programming comprises:
programming a first set of selection inputs, wherein:
the step of programming the first set of selection inputs is based on the pre-selected polynomial key word;
the first set of selection inputs is associated with:
selecting corresponding input from each of the logic gates; and
a shift logic that is associated with the plurality of registers.
8. A method for generating a Cyclic Redundancy Check (CRC) in a system, comprising the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero,
wherein the step of programming is based on a pre-selected polynomial key word, and
wherein the step of programming comprises:
programming a second set of selection inputs, wherein:
the second set of selection inputs is associated with selecting corresponding input to each of the logic gates;
the second set of selection inputs is associated with the selecting a final output from among output from the plurality of registers; and
the step of programming the second set of selection inputs is based on the pre-selected polynomial key word.
9. A method for generating a Cyclic Redundancy Check (CRC) generator in a system comprising the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a first set of selection inputs, wherein:
the step of programming the first set of selection inputs is based on a pre-selected polynomial that is associated with the CRC generator;
the first set of selection inputs is associated with:
selecting corresponding input from each of the one or more logic gates; and
a shift logic that is associated with the plurality of registers; and programming a second set of selection inputs, wherein:
the second set of selection inputs is associated with selecting corresponding input to each logic gate;
the second set of selection inputs is associated with selecting a final output from among output from the plurality of registers; and
the step of programming the second set of selection inputs is based on the pre-selected polynomial that is associated with the CRC generator.
10. The method as recited in claim 9, further comprising:
using a first set of multiplexers in conjunction with the first set of selection inputs for selecting at least one input for shifting to a next register of the plurality of registers,
wherein the at least one input is a member of a set of inputs that includes an output from an adjacent logic gate and a straight shift from an adjacent register of the plurality of registers.
11. The method as recited in claim 9, further comprising:
using a second set of multiplexers in conjunction with the second set of selection inputs for selecting at least one input to a corresponding logic gate,
wherein the at least one input is a member of a set of inputs that includes a primary input and a feedback input.
12. The method as recited in claim 9, further comprising:
using a second set of multiplexers in conjunction with the second set of selection inputs for selecting the final output from among output from the plurality of registers.
13. The method as recited in claim 9, wherein the plurality of registers are shift registers.
14. A computer-readable medium carrying one or more sequences of instructions for generating a Cyclic Redundancy Check (CRC) generator in a system, which instructions, when executed by one or more processors, cause the one or more processors to carry out the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero,
wherein the step of programming is based on a pre-selected polynomial key word.
15. A computer-readable medium carrying one or more sequences of instructions for generating a Cyclic Redundancy Check (CRC) generator in a system, which instructions, when executed by one or more processors, cause the one or more processors to carry out the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a first set of selection inputs, wherein:
the step of programming the first set of selection inputs is based on a pre-selected polynomial that is associated with the CRC generator;
the first set of selection inputs is associated with:
selecting corresponding input from each of the one or more logic gates; and
a shift logic that is associated with the plurality of registers; and
programming a second set of selection inputs, wherein:
the second set of selection inputs is associated with selecting corresponding input to each logic gate;
the second set of selection inputs is associated with selecting a final output from among output from the plurality of registers; and
the step of programming the second set of selection inputs is based on the pre-selected polynomial that is associated with the CRC generator.
16. An apparatus for creating a Cyclic Redundancy Check (CRC) generator in a system, comprising:
means for creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
means for programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero,
wherein the step of programming is based on a pre-selected polynomial key word.
17. An apparatus for creating a Cyclic Redundancy Check (CRC) generator in a system, comprising:
means for creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
means for programming a first set of selection inputs, wherein:
the step of programming the first set of selection inputs is based on a pre-selected polynomial that is associated with the CRC generator;
the first set of selection in puts is associated with:
selecting corresponding input from each of the one or more logic gates; and
a shift logic that is associated with the plurality of registers; and
means for programming a second set of selection inputs, wherein:
the second set of selection inputs is associated with selecting corresponding input to each logic gate;
the second set of selection inputs is associated with selecting a final output from among output from the plurality of registers; and
means for the step of programming the second set of selection inputs is based on the pre-selected polynomial that is associated with the CRC generator.
18. An apparatus for creating a Cyclic Redundancy Check (CRC) generator in a system, comprising:
a processor;
one or more stored sequences of instructions which, when executed by the processor, cause the processor to carry out the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a subset of the plurality of registers to have a value of zero and programming a corresponding subset of the logic gates to have a value of zero,
wherein the step of programming is based on a pre-selected polynomial key word.
19. An apparatus for creating a Cyclic Redundancy Check (CRC) generator in a system, comprising:
a processor;
one or more stored sequences of instructions which, when executed by the processor, cause the processor to carry out the steps of:
creating a circuit comprising a plurality of registers wherein each of the plurality of registers is associated with a corresponding logic gate; and
programming a first set of selection inputs wherein:
the step of programming the first set of selection inputs is based on a pre-selected polynomial that is associated with the CRC generator;
the first set of selection inputs is associated with:
selecting corresponding input from each of the one or more logic gates; and
a shift logic that is associated with the plurality of registers; and
programming a second set of selection inputs, wherein:
the second set of selection inputs is associated with selecting corresponding input to each logic gate;
the second set of selection inputs is associated with selecting a final output from among out put from the plurality of registers; and
the step of programming the second set of selection inputs is based on the pre-selected polynomial that is associated with the CRC generator.
20. A cyclic redundancy check (CRC) generator for generating CRC codes, comprising:
a first set of N storage elements,
wherein a first selection signal is configured to select a subset of the first set of N storage elements, and
wherein each storage element of the subset of the first set of N storage elements corresponds to a term of a pre-selected CRC polynomial keyword; and
M logic circuits,
wherein an input of each of the M logic circuits is in communication with an output of a corresponding one of the first set of N storage elements, and
wherein a second selection signal is configured to select an output of one storage element of the subset of the first set of N storage elements corresponding to a length of the pre-selected CRC polynomial keyword.
21. The CRC generator of claim 20, wherein each storage element of the first set of N storage elements corresponds to a term of an Nth-order CRC polynomial keyword, and
wherein the length of the pre-selected CRC polynomial keyword is at most N.
22. The CRC generator of claim 20, comprising:
a first plurality of selector circuits,
wherein each selector circuit of the first plurality of selector circuits is configured to output one of an output of a corresponding one of the M logic circuits and an output of a corresponding one of the first set of N storage elements, and
wherein each selector circuit of the first plurality of selector circuits is configured to receive the first selection signal based upon the pre-selected CRC polynomial keyword.
23. The CRC generator of claim 22, comprising:
a second set of N storage elements,
wherein each storage element of the second set of N storage elements is in communication with a corresponding one of the first set of N storage elements, and
wherein each storage element of the second set of N storage elements is configured to provide the first selection signal to the corresponding one of the first set of N storage elements based upon the pre-selected CRC polynomial keyword.
24. The CRC generator of claim 23, wherein each storage element of the second set of N storage elements comprises one of a register and a buffer element.
25. The CRC generator of claim 22, comprising:
a second plurality of selector circuits,
wherein each selector circuit of the second plurality of selector circuits is configured to output one of an output of a first subset of the first set of N storage elements and an output of a second subset of the first set of N storage elements, and
wherein one of the second plurality of selector circuits receives the second selection signal to select the output of the first subset of the first set of N storage elements for output.
26. The CRC generator of claim 25, comprising:
a third set of selector circuits,
wherein the output of each selector circuit of the third set of selector circuits is in communication with an input of a corresponding one of the M logic circuits,
wherein each selector circuit of the third set of selector circuits is configured to output one of an output of a corresponding one of the second set of selector circuits and an input signal, and
wherein one of the third plurality of selector circuits receives the second selection signal to select the input signal for output.
27. The CRC generator of claim 26, wherein each selector circuit comprises a multiplexer.
28. The CRC generator of claim 20, comprising:
an output selector circuit,
wherein inputs of the output selector circuit are in communication with outputs of each storage element of the first set of N storage elements, and
wherein the output selector circuit is configured to receive the second selection signal to select the output of the one storage element of the subset of the first set of N storage elements as the output of the CRC generator for the pre-selected CRC polynomial keyword.
29. The CRC generator of claim 28, wherein the output selector circuit comprises a multiplexer.
30. The CRC generator of claim 20, wherein an input of one of the M logic circuits is in communication with an input signal.
31. The CRC generator of claim 20, wherein each storage element of the first set of N storage elements comprises one of a shift register and a buffer.
32. The CRC generator of claim 20, wherein each of the M logic circuits comprises an XOR gate.
33. The CRC generator of claim 20, wherein M is equal to N.
34. A cyclic redundancy check (CRC) generator for generating CRC codes, comprising:
a first set of N means for storing data,
wherein a first selection signal is configured to select a subset of the first set of N data storing means, and
wherein each data storing means of the subset of the first set of N data storing means corresponds to a term of a pre-selected CRC polynomial keyword; and
M logic circuit means,
wherein an input of each of the M logic circuit means is in communication with an output of a corresponding one of the first set of N data storing means, and
wherein a second selection signal is configured to select an output of one data storing means of the subset of the first set of data storing means corresponding to a length of the pre-selected CRC polynomial keyword.
35. The CRC generator of claim 34, wherein each data storing means of the first set of N data storing means corresponds to a term of an Nth-order CRC polynomial keyword, and
wherein the length of the pre-selected CRC polynomial keyword is at most N.
36. The CRC generator of claim 34, comprising:
a first plurality of means for signal selecting,
wherein each signal selecting means of the first plurality of signal selecting means is configured to output one of an output of a corresponding one of the M logic circuit means and an output of a corresponding one of the first set of N data storing means, and
wherein each signal selecting means of the first plurality of signal selecting means is configured to receive the first selection signal based upon the pre-selected CRC polynomial keyword.
37. The CRC generator of claim 36, comprising:
a second set of N means for storing data,
wherein each data storing means of the second set of N data storing means is in communication with a corresponding one of the first set of N data storing means, and
wherein each data storing means of the second set of N data storing means is configured to provide the first selection signal to the corresponding one of the first set of N data storing means based upon the pre-selected CRC polynomial keyword.
38. The CRC generator of claim 37, wherein each data storing means of the second set of N data storing means comprises one of a means for shifting data and a means for buffering data.
39. The CRC generator of claim 36, comprising:
a second plurality of means for signal selecting,
wherein each signal selecting means of the second plurality of signal selecting means is configured to output one of an output of a first subset of the first set of N data storing means and an output of a second subset of the first set of N data storing means, and
wherein one of the second plurality of signal selecting means receives the second selection signal to select the output of the first subset of the first set of N data storing means for output.
40. The CRC generator of claim 39, comprising:
a third set of means for signal selecting,
wherein the output of each signal selecting means of the third set of signal selecting means is in communication with an input of a corresponding one of the M logic circuit means,
wherein each signal selecting means of the third set of signal selecting means is configured to output one of an output of a corresponding one of the second set of signal selecting means and an input signal, and
wherein one of the third plurality of signal selecting means receives the second selection signal to select the input signal for output.
41. The CRC generator of claim 40, wherein each signal selecting means comprises a multiplexer means.
42. The CRC generator of claim 34, comprising:
an output means for signal selecting,
wherein inputs of the output signal selecting means are in communication with outputs of each data storing means of the first set of N data storing means, and
wherein the output signal selecting means is configured to receive the second selection signal to select the output of the one data storing means of the subset of the first set of N data storing means as the output of the CRC generator for the pre-selected CRC polynomial keyword.
43. The CRC generator of claim 42, wherein the output signal selecting means comprises a multiplexer means.
44. The CRC generator of claim 34, wherein an input of one of the M logic circuit means is in communication with an input signal.
45. The CRC generator of claim 34, wherein each data storing means of the first set of N data storing means comprises one of a means for shifting data and a means for buffering data.
46. The CRC generator of claim 34, wherein each of the M logic circuit means comprises an XOR gate means.
47. The CRC generator of claim 34, wherein M is equal to N.
48. A method of generating cyclic redundancy check (CRC) codes, comprising the steps of:
a.) storing a first signal N times;
b.) logically combining each stored first signal with one of an input signal and a selected signal M times;
c.) selecting a subset of the N storing steps in response to a first selection signal, wherein each storing step of the subset of the N storing steps corresponds to a term of a pre-selected CRC polynomial; and
d.) selecting an output of one storing step of the subset of N storing steps corresponding to a length of the pre-selected CRC polynomial keyword, in response to a second selection signal.
49. The method of claim 48, wherein each storing step of the N storing steps corresponds to a term of an Nth-order CRC polynomial keyword, and
wherein the length of the pre-selected CRC polynomial keyword is at most N.
50. The method of claim 49, comprising the step of:
e.) selecting one of an output of a corresponding one of the M logically combining steps and an output of a corresponding one of the N storing steps in response to the first selection signal.
51. The method of claim 50, comprising the step of:
f.) selecting one of an output of a first subset of the N storing steps and an output of a second subset of the N storing steps, in response to the second selection signal.
52. The method of claim 51, comprising the step of:
g.) selecting one of an output of step (f) and an input signal to form the selected signal, in response to the second selection signal.
53. The method of claim 48, comprising the step of:
e.) selecting the output of the one of the storing steps of the subset of N storing steps as the output of the pre-selected CRC polynomial keyword, in response to the second selection signal.
54. The method of claim 48, comprising the step of:
e.) receiving an input signal at one of the M logically combining steps.
55. The method of claim 48, wherein each of the N storing steps comprises the step of shifting the first signal.
56. The method of claim 48, wherein each of the M logically combining steps comprises the step of exclusive or'ing the respective stored first signal with a corresponding one of the input signal and the selected signal.
57. The method of claim 48, wherein M is equal to N.
58. A computer program for generating cyclic redundancy check (CRC) codes, wherein the computer program performs the steps of:
a.) controlling storing of a first signal N times;
b.) logically combining each stored first signal with one of an input signal and a selected signal M times;
c.) providing a first selection signal to select a subset of the N storing steps, wherein each storing step of the subset of the N storing steps corresponds to a term of a pre-selected CRC polynomial; and
d.) providing a second selection signal to select an output of one storing step of the subset of N storing steps corresponding to a length of the pre-selected CRC polynomial keyword.
59. The computer program of claim 58, wherein each storing step of the N storing steps corresponds to a term of an Nth-order CRC polynomial keyword, and
wherein the length of the pre-selected CRC polynomial keyword is at most N.
60. The computer program of claim 59, wherein the computer program performs the step of:
e.) providing the first selection signal to select one of an output of a corresponding one of the M logically combining steps and an output of a corresponding one of the N storing steps.
61. The computer program of claim 60, wherein the computer program performs the step of:
f.) providing the second selection signal to select one of an output of a first subset of the N storing steps and an output of a second subset of the N storing steps.
62. The computer program of claim 61, comprising the step of:
g.) providing the second selection signal to select one of an output of step (f) and an input signal to form the selected signal.
63. The computer program of claim 58, wherein the computer program performs the step of:
e.) providing the second selection signal to select the output of the one of storing steps of the subset of the N storing steps as the output of the pre-selected CRC polynomial keyword.
64. The computer program of claim 58, wherein the computer program performs the step of:
e.) providing an input signal at one of the M logically combining steps.
65. The computer program of claim 58, wherein each of the N storing steps comprises the step of shifting the first signal.
66. The computer program of claim 58, wherein M is equal to N.
67. A cyclic redundancy check (CRC) generator for generating CRC codes, comprising:
N CRC subcircuits,
wherein each of the N CRC subcircuits comprises:
a storage element;
a logic circuit in communication with the storage element; and
a first selector circuit in communication with an output of the storage element and an output of the logic circuit,
wherein an input of a storage element of an nth one of the N CRC subcircuits is in communication with an output of a first selector circuit of an n−1th one of the N CRC subcircuits,
wherein a first selection signal is configured to select a subset of the N CRC subcircuits, and
wherein each storage element of the subset of the N CRC subcircuits corresponds to a term of a pre-selected CRC polynomial keyword;
M selector subcircuits,
wherein each of the M selector subcircuits comprises:
a second selector circuit,
wherein a first input of the second selector circuit of an mth one of the M selector subcircuits is in communication with an output of a second selector circuit of an m+1th one of the M selector subcircuits, and
wherein a second input of the second selector circuit of the mth one of the M selector subcircuits is in communication with an output of a first selector circuit of the nth one of the N CRC subcircuits; and
a third selector circuit,
wherein a first input of the third selector circuit of the mth one of the M selector subcircuits is in communication with an output of the second selector circuit of the mth one of the M selector subcircuits, and
wherein a second input of the third selector circuit of the mth one of the M selector subcircuits is in communication with an input signal,
wherein the second and third selector circuits of one of the M selector subcircuits receive a second selection signal to select the second input of the respective second and third selector circuits for output; and
an output selector circuit,
wherein inputs of the output selector circuit are in communication with outputs of each storage element of the N CRC subcircuits, and
wherein the output selector circuit receives the second selection signal to select the output of one storage element of the subset of the N CRC subcircuits corresponding to a length of the pre-selected CRC polynomial keyword.
68. The CRC generator of claim 67, wherein M is equal to N−1, and
wherein an output of an Nth CRC subcircuit is in communication with the first input of the second selector circuit of the Mth selector subcircuit.
69. The CRC generator of claim 67, wherein each storage element comprises one of a shift register and a buffer.
70. The CRC generator of claim 67, wherein each logic circuit comprises an XOR gate.
71. The CRC generator of claim 67, wherein each of the M selector subcircuits comprises a multiplexer subcircuit, and
wherein each of the first, second and third selector circuits comprises a multiplexer.
72. A cyclic redundancy check (CRC) generator for generating CRC codes, comprising:
N CRC subcircuit means,
wherein each of the N CRC subcircuit means comprises:
a means for storing data;
a logic circuit means in communication with the data storing means;
a first means for signal selecting in communication with an output of the data storing means and an output of the logic circuit means,
wherein an input of a data storing means of an nth one of the N CRC subcircuit means is in communication with an output of a first signal selecting means of an n−1th one of the N CRC subcircuit means,
wherein a first selection signal is configured to select a subset of the N CRC subcircuit means, and
wherein each data storing means of the subset of the N CRC subcircuit means corresponds to a term of a pre-selected CRC polynomial keyword;
M selector subcircuit means,
wherein each of the M selector subcircuit means comprises:
a second means for signal selecting,
wherein a first input of the second signal selecting means of an mth one of the M selector subcircuit means is in communication with an output of a second signal selecting means of an m+1th one of the M selector subcircuit means, and
wherein a second input of the second signal selecting means of the mth one of the M selector subcircuit means is in communication with an output of a first signal selecting means of the nth one of the N CRC subcircuit means; and
a third means for signal selecting,
wherein a first input of the third signal selecting means of the mth one of the M selector subcircuit means is in communication with an output of the second signal selecting means of the mth one of the M selector subcircuit means, and
wherein a second input of the third signal selecting means of the mth one of the M selector subcircuit means is in communication with an input signal,
wherein the second and third signal selecting means of one of the M selector subcircuit means receive a second selection signal to select the second input of the respective second and third signal selecting means for output; and
an output means for signal selecting,
wherein inputs of the output signal selecting means are in communication with outputs of each data storing means of the N CRC subcircuit means, and
wherein the output signal selecting means receives the second selection signal to select the output of one data storing means of the subset of the N CRC subcircuit means corresponding to a length of the pre-selected CRC polynomial keyword.
73. The CRC generator of claim 72, wherein M is equal to N−1, and
wherein an output of an Nth CRC subcircuit means is in communication with the first input of the second signal selecting means of the Mth selector subcircuit means.
74. The CRC generator of claim 72, wherein each data storing means comprises one of a means for shifting data and a means for buffering data.
75. The CRC generator of claim 72, wherein each logic circuit means comprises an XOR gate means.
76. The CRC generator of claim 72, wherein each of the M selector subcircuit means comprises a multiplexer subcircuit means, and
wherein each of the first, second and third signal selecting means comprises a multiplexer means.
77. A method of generating cyclic redundancy check (CRC) codes, comprising the steps of:
a.) shifting a first signal N times,
b.) exclusive or'ing each shifted first signal with one of an input signal and a selected signal M times;
c.) selecting one of an output of a corresponding one of the M exclusive or'ing steps and an output of a corresponding one of the N storing steps, in response to a first selection signal,
wherein an input of an nth one of the N shifting steps is in communication with an output of an n−1th one of the N selecting steps of step (c);
d.) selecting, M times, one of an output of a first subset of the N storing steps and an output of a second subset of the N storing steps, in response to a second selection signal,
wherein a first input of an mth one of the selecting steps of step (d) is in communication with an output of an m+1th one of the selecting steps of step (d), and
wherein a second input of the mth one of the selecting steps of step (d) is in communication with an output of an nth one of the selecting steps of step (c);
e.) selecting, M times, one of an output of step (d) and an input signal to form the selected signal, in response to the second selection signal;
f.) selecting a subset of the N storing steps in response to the first selection signal,
wherein each storing step of the subset of the N storing steps corresponds to a term of a pre-selected CRC polynomial; and
g.) selecting an output of one storing step of the subset of N storing steps corresponding to a length of the pre-selected CRC polynomial keyword as the output of the pre-selected CRC polynomial keyword, in response to the second selection signal.
78. The method of claim 77, wherein M is equal to N−1, and
wherein an output of an Nth selecting step of step (c) is in communication with the first input of an Mth selecting step of step (d).
79. A computer program for generating cyclic redundancy check (CRC) codes, wherein the computer program performs the steps of:
a.) controlling shifting of a first signal N times,
b.) exclusive or'ing each shifted first signal with one of an input signal and a selected signal M times;
c.) providing a first selection signal to select one of an output of a corresponding one of the M exclusive or'ing steps and an output of a corresponding one of the N storing steps,
wherein an input of an nth one of the N shifting steps is in communication with an output of an n−1th one of the N selectings of step (c);
d.) providing a second selection signal to select, M times, one of an output of a first subset of the N storing steps and an output of a second subset of the N storing steps,
wherein a first input of an mth one of the selectings of step (d) is in communication with an output of an m+1th one of the selectings of step (d), and
wherein a second input of the mth one of the selectings of step (d) is in communication with an output of an nth one of the selectings of step (c);
e.) providing the second selection signal to select, M times, one of an output of the selecting of step (d) and an input signal to form the selected signal;
f.) providing the first selection signal to select a subset of the N storing steps,
wherein each storing step of the subset of the N storing steps corresponds to a term of a pre-selected CRC polynomial; and
g.) providing the second selection signal to select an output of one storing step of the subset of N storing steps corresponding to a length of the pre-selected CRC polynomial keyword as the output of the pre-selected CRC polynomial keyword.
80. The method of claim 79, wherein M is equal to N−1, and
wherein an output of an Nth selecting of step (c) is in communication with the first input of an Mth selecting of step (d).
Description
CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. Provisional Patent Application Ser. No. 60/338,137, filed Nov. 9, 2001, entitled, “SYSTEM AND METHOD FOR GENERATING A CYCLIC REDUNDANCY CHECK.”

FIELD OF THE INVENTION

The invention generally relates to electronic systems. The invention relates more specifically to systems and methods for generating cyclic redundancy check.

BACKGROUND OF THE INVENTION

A popular method for error detection for digital signals is the Cyclic Redundancy Check (CRC). CRC works by treating the message string that is sent between a transmitter and a receiver as a single binary word. The single binary word is divided by a key word that is agreed upon by both the transmitter and the receiver ahead of time. The remainder that is left after dividing the single binary word by the key word is known as a check word. The transmitter sends both the message string and the check word to the receiver. The receiver then verifies the data by dividing the data by the key word. If the remainder, obtained by dividing the data by the key word, matches the check word, then the receiver can be sure that the data is indeed the correct message string from the transmitter.

In the context of CRC, key words are usually numbers and are presented in the form of polynomials whose coefficients are in the form of the binary bits of the key word. A popular key word is X16+X12+X5+1 known as the X25 standard. Key words will herein be referred to as polynomial key words.

CRC is often implemented in hardware that is specific to a given polynomial key word. A CRC that is implemented in hardware is herein referred to as a CRC generator. Thus, a system that has to verify data using various different polynomial key words will need a separate CRC generator that is dedicated to each distinct polynomial key word. For example, FIG. 1 is a block diagram that illustrates a CRC generator that employs a 3rd order polynomial key word, X3+X2+1.

In FIG. 1, exclusive-OR gates (XOR gates) 110, 112, and 116 are communicatively coupled to each other and to corresponding shift registers 102, 104 and 106. Input 101 is initially received at XOR gate 110. The output of the CRC generator in FIG. 1 is 118.

FIG. 2 is block diagram that illustrates a CRC generator that employs a 1st order polynomial key word, X1+1. In FIG. 2, XOR gates 210, and 212 are communicatively coupled to each other and to corresponding shift registers 202, and 204. Input 220 is initially received at XOR gate 210. The output of the CRC generator in FIG. 2 is 222.

A system with multiple CRC generators can be unwieldy and inefficient.

Based on the foregoing, it is clearly desirable to reduce the number of CRC generators in a given system.

It is further desirable to have a programmable CRC generator so that the CRC generator can be dynamically changed to accommodate different applications.

SUMMARY OF THE INVENTION

Techniques are provided for creating a Cyclic Redundancy Check generator in a system. According to one aspect of the invention, a universal N-bit capable CRC generator is created and programmed to adapt to any given polynomial key word. According to one feature, the N-bit capable CRC generator comprises N shift registers that are associated with corresponding exclusive OR gates (XOR gates). Each of the shift registers corresponds to a term of a general Nth order polynomial key word. Thus, by nullifying a subset of the shift registers and their corresponding XOR gates, the N-bit capable CRC generator can be converted into a specific polynomial key word CRC generator. The selection of the subset of the shift registers and their corresponding XOR gates is based on the desired polynomial key word. The N-bit capable CRC generator can be re-programmed each time a new polynomial key word is desired.

In other aspects, the invention encompasses a computer apparatus, a computer readable medium, and a carrier wave configured to carry out the foregoing steps.

An advantage of using an N-bit capable CRC generator is that it can dynamically programmed to accommodate a new polynomial key word rather than having build a new CRC generator for each new polynomial key word.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

FIG. 1 is a block diagram that illustrates a prior art CRC generator that employs a 3rd order polynomial key word;

FIG. 2 is block diagram that illustrates a prior art CRC generator that employs a 1st order polynomial key word;

FIG. 3A is block diagram that illustrates an exemplary N-bit capable CRC generator;

FIG. 3B is a block diagram that illustrates the most significant bit (MSB) to the least significant bit (LSB) in relation to programmable registers;

FIG. 4 is a block diagram that illustrates the position of the MSB that is associated with a qth order polynomial key word;

FIG. 5 is a block diagram that illustrates a 3-bit capable CRC generator;

FIG. 6 is a block diagram that illustrates the position of the MSB that is associated with a X3+X2+1 key word;

FIG. 7 is a block diagram that illustrates the position of the MSB that is associated with a X1+X0 key word;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

A system and method for generating a cyclic redundancy check is described. In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the present invention. Embodiments are described herein according to the following outline:

    • 1.0 OPERATIONAL CONTEXT AND FUNCTIONAL OVERVIEW
    • 2.0 N-BIT CAPABLE CRC GENERATOR
    • 3.0 ILLUSTRATIVE EXAMPLE OF THE FLEXIBILITY OF AN N-BIT CAPABLE CRC GENERATOR
    • 5.0 EXTENSIONS AND ALTERNATIVES
      1.0 Operational Context and Functional Overview

In certain embodiments of the present invention, a universal CRC generator is used in a system that receives digital signals. The universal CRC generator can be programmed to be a specific polynomial key word CRC generator. Thus, one set of hardware can be adapted for any given polynomial key word. For example, for purposes of explanation, assume that a transmitter of a bitstream and a receiver of the same bitstream agree upon a key word that can be represented by the polynomial, X16+X12+X5+1. The universal CRC can be programmed to be an X16+X12+X5+1 polynomial key word CRC generator. Generally, an Nth polynomial key word CRC generator is also referred to as an N-bit CRC generator. Each time that the key word is changed, the universal CRCgenerator can be re-programmed to correspond to the new key word. It is to be noted that an Nth order polynomial key word has (N+1) bits.

Thus, in certain embodiments of the present invention, the universal CRC generator is a CRC generator that is capable of being a N-bit CRC generator, where N is a positive integer that is selected corresponding to the highest order polynomial key word that the universal CRC generator is expected to use. A universal generator that is capable of being an N-bit CRC generator is herein referred to as an “N-bit capable” CRC generator.

According to certain embodiments of the present invention, the universal CRC generator can be re-programmed to correspond to a new polynomial key word by programming the values of certain programmable registers that are part of the universal CRC generator and by programming certain selection inputs for multiplexers that are also part of the universal CRC generator. The programming of the registers and selection inputs for the multiplexers are explained in greater detail herein.

2.0 N-Bit Capable CRC Generator

According to certain embodiments of invention, FIG. 3A is block diagram that illustrates an N-bit capable CRC generator. An N-bit capable CRC generator is a universal CRC generator for which the highest order polynomial key word is N. Thus, an N-bit capable CRC generator can be used for polynomial key words of orders ranging from 1 to N. The N-bit CRC generator of FIG. 3A comprises the following as indicated in List A.

List A:

1) N+1 number of shift registers, namely, Xn 310, X(n−1) 312, . . . , X0 314;

2) N+1 number of exclusive-OR gates, namely, XORn 316, XOR(n−1) 318, . . . , XOR0 320;

3) 3N+1 number of multiplexers, namely, Ma n 322, Ma (n−1) 324, Mb (n−1) 326, Mc (n−1) 328, . . . , Ma 0 330, Mb 0 332, Mc 0 334; and

4) N+1 programmable registers, namely, Yn 336, Y(n−1) 338, . . . , Y0 340.

The broken line 302 in FIG. 3A indicates that the following components as indicated in List B are not shown on FIG. 3A for want of space.

List B:

1) shift registers X(n−2), X(n−3), . . . up to X1;

2) exclusive-OR gates XOR(n−2), XOR(n−3), . . . , up to XOR1;

3) multiplexes Ma (n−2), Mb (n−2), Mc (n−2), . . . , up to Ma 1, Mb 1, Mc 1;

4) programmable registers Y(n−2), Y(n−3), . . . , up to Y1;

Each of the shift registers X is communicatively coupled to a corresponding exclusive-OR gate (XOR gate) and to adjacent multiplexers M. For example, in FIG. 3A, shift register Xn 310 is communicatively coupled to a corresponding XOR gate, XORn 316. Specifically, line 368 is shown as the output from Xn 310. Line 368 is also the input to XOR gate, XORn 316. Similarly, shift register Xn−1 312 is communicatively coupled to a corresponding XOR gate, XORn−1 318, etc. Line 378 is shown as the output from Xn−1 312. Line 378 is also the input to XOR gate, XORn−1 318. However, shift register X0 314 is communicatively coupled to only one XOR gate, viz., XOR0 320. Line 390 is shown as the output from X0 314. Line 390 is also the input to XOR gate, XOR0 320.

Further, each of the shift registers X in FIG. 3A is communicatively coupled to corresponding adjacent multiplexers M. For example, shift register Xn 310 is communicatively coupled to adjacent multiplexers Ma n 322 and Ma (n−1) 324. Specifically, line 366 is shown as an output from shift register Xn 310. Line 366 is also the input to multiplexer Ma n 322. Line 372 is shown as an output from multiplexer Ma n−1 324. Line 372 is also an input to shift register Xn 310.

Similarly, shift register Xn−1 312 is communicatively coupled to adjacent multiplexers Ma n−1 324, etc. Specifically, line 376 is shown as an output from shift register Xn−1 312. Line 376 is also the input to multiplexer Ma n−1 324. Line 382 is shown as an output from multiplexer Ma n−2 (note that Ma n−2 is not shown in FIG. 3A). Line 382 is also an input to shift register Xn−1 312.

Shift register X0 314 is communicatively coupled to adjacent multiplexer Ma 0 330. Specifically, line 391 is shown as an output line from shift register X0 314. Line 391 is also an input line to multiplexer Ma 0 330. Line 393 is shown as an output line from multiplexer Mb 0 332. Line 393 is also an input line to shift register X0 314.

Further, all shift registers Xn 310, X(n−1) 312, . . . , X0 314 in FIG. 3A are communicatively coupled to multiplexer Mout 342 via lines An 344, An−1 346, . . . , up to A0 348. For example, shift register Xn 310 is connected to Mout 342 via line An 344. Shift register Xn−1 312 is connected to Mout 342 via line An−1 346, etc. Further, CRC output 350 is the output of the N-bit capable CRC generator.

Each XOR gate is additionally communicatively coupled to corresponding adjacent multiplexers. For example, in FIG. 3A, XOR gate XOR(n−1) 318 is communicatively coupled to adjacent corresponding multiplexers Ma (n−1) 324 and Mc (n−1) 328. Specifically, line 380 is shown as an input line from multiplexer Mc (n1−1) 328 to XOR gate XOR(n−1) 318. Line 374 is an output line from XOR gate XOR(n−1) 318 to multiplexer Ma (n−1) 324.

Similarly, XOR gate XOR0 320, is communicatively coupled to adjacent corresponding multiplexers Ma 0 330 and Mc 0 334, etc. Specifically, line 396 is shown as an input line from multiplexer Mc 0 334 to XOR gate XOR0 320. Line 388 is an output line from XOR gate XOR0 320 to multiplexer Ma 0 330. However, XOR gate XORn 316 is communicatively coupled to only one adjacent corresponding multiplexer Ma n 322. Line 364 is shown as an output line from XORn 316 to multiplexer Ma n 322.

Programmable registers Yn 336, Y(n−1) 338, . . . , Y0 340 are each communicatively coupled to a corresponding multiplexer. For example, programmable register Yn 336 is communicatively coupled to multiplexer Ma n 322, programmable register Y(n−1) 338 is coupled to multiplexer Ma (n−1) 324, etc.

For simplicity, programmable registers Yn 336, Y(n−1) 338, . . . , Y0 340 are collectively referred to herein as Y registers.

The Y registers are programmed based on the given polynomial key word. To explain, each Y register in the N-bit capable CRC generator is associated with one term in the general Nth-order polynomial, CnXn+Cn−1Xn−1+Cn−2Xn−2+ . . . +C2X2+C1X1+C0X0, where Cn, Cn−1, Cn−2, . . . , C2, C1, and C0 are the coefficients of the general Nth-order polynomial and are constants.

Each Y register corresponds to one coefficient of the general Nth-order polynomial. Specifically, programmable register Yn 336 in FIG. 3A corresponds to coefficient Cn, programmable register Yn−1 338 corresponds to coefficient Cn−1 and so on. The given polynomial key word is compared to the general Nth order polynomial to determine which of the coefficients of the general Nth-order polynomial are to take the value of zero in order to convert the Nth-order general polynomial into the given polynomial key word.

The Y registers that correspond to coefficients that have a value of zero are programmed to have a bit value of zero. The Y registers that correspond to coefficients that have a value of 1 are programmed to have a bit value of 1.

The value of each bit in the Y register determines which input is selected at the corresponding multiplexer to be an output. For example, if programmable register Yn 336 is programmed to have a bit value of 1, multiplexer Ma n 322 will receive the value 1 as an input from programmable register Yn 336. In FIG. 3A, it can be seen that multiplexer Ma n 322 has 2 input lines, labeled “1” and “0” respectively. Since the value 1 is received from programmable register Yn 336 multiplexer Ma n 322 will select the input line labeled “1” to be the output of Ma n 322 for a particular cycle.

FIG. 3B is a block diagram that illustrates the most significant bit (MSB) to the least significant bit (LSB) in relation to the programmable registers Y 370. Bit Bn corresponds to the value in register Yn 336, and is the MSB if the value of Yn 336 is the first occurring “1” bit. Similarly, bit Bn−1 corresponds to the value in register Yn−1 338, etc. Bit B0 corresponds to the value in register Y0 340, and is the LSB.

For ease of explanation, multiplexers with the same superscript as illustrated in FIG. 3A are said to belong to the same family. As can be seen in FIG. 3A, multiplexers that belong to the same family are communicatively coupled to form part of a feedback loop. For example, multiplexer Ma (n−1) 324 is communicatively coupled to multiplxer Mb (n−1) 326 that is in turn communicatively coupled to multiplexer Mc (n−1) 328. Multiplexer Ma 0 330 is communicatively coupled to multiplxer Mb 0 332 that is in turn communicatively coupled to multiplexer Mc 0 334. However, multiplexer Ma n 322, being the sole member in its family is communicatively coupled only to one multiplexer that belongs to another family, viz., multiplexer Mb (n−1) 326.

Selection inputs such as, Last-X(n−1) 352, Last-X(n−2) (not shown in FIG. 3A), . . . , Last-X0 354, are received as inputs into corresponding multiplexers with subscripts “b” and “c” and that belong to the same family. For example, Last-X(n−1) 352 is a selection input into multiplexers Mb (n−1) 326 and Mc (n−1) 328, and Last-X0 354 is a selection input into multiplexers Mb 0 332 and Mc 0 334, etc.

Further, all selection inputs, namely, Last-X(n−1) 352, Last-X(n−2) (not shown in FIG. 3A), . . . , Last-X0 354 are input into multiplexer Mout 342. It is to be noted that, in certain embodiments, there is no Last-Xn selection input.

For simplicity in explaining the function of the components in FIG. 3A, selection inputs such as Last-X(n−1) 352, Last-X(n−2) (not shown in FIG. 3A), . . . , Last-X0 354 are collectively referred to herein as Last-X selection inputs.

Generally, selection inputs such as, Last-X(n−1) 352, Last-X(n−2) (not shown in FIG. 3A), . . . , Last-X0 354, are programmed to be a specific value based on the most significant bit (MSB) of the Y registers. For purposes of illustration, assume that the given polynomial key word is a qth order polynomial, where q is a positive integer that is less than N. FIG. 4 is a block diagram that illustrates the position of the MSB that is associated with a qth order polynomial key word.

In FIG. 4, bit Bn has the value of the Yn register that is programmed as described herein. Bit Bn−1 has the value of the Yn−1 register, bit Bn−2 has the value of the Yn−2 register, . . . , bit Bq has the value of the Yq register, bit Bq−1 has the value of the Yq−1 register, bit Bq−2 has the value of the Yq−2 register, . . . , bit B2 has the value of the Y2 register, bit B1 has the value of the Y1 register, and bit B0 has the value of the Y0 register.

Since the given polynomial key word is a qth order polynomial, the first occurring “1” bit corresponds to the value of the Yq register. In FIG. 4, the first occurring “1” bit is in Yq register and so Yq is the MSB. Since the first “1” bit corresponds to the value of the Yq register, the selection input Last-Xq (not shown in FIG. 3A) is programmed to be equal to 1. All other selection inputs such as, Last-Xn−1 352, Last-Xn−2 (not shown in FIG. 3A), . . . , Last-X0 354, are programmed to have a value of zero.

The value of each selection input, such as Last-Xn−1 352, Last-Xn−2 (not shown in FIG. 3A), . . . , Last-X0 354 determines which input lines 362, 370, 394, 358, 392, . . . , 387, 386, 395, 358, is selected at the corresponding multiplexers, Mb n−1 Mc n−1, . . . , Mb 0, Mc 0 to be output from the multiplexers Mb n−1 Mc n−1, . . . , Mb 0, Mc 0.

For example, if selection input Last-Xn−1 352 is programmed to have the value of 1, multiplexer Mb n−1 326 and multiplexer Mc n−1 328 will each receive the value 1 as an input. In FIG. 3A, it can be seen that multiplexer Mb n−1 326 and multiplexer Mc n−1 328 each has 2 input lines, labeled “1” and “0”. Since the value 1 is received as the selection input by multiplexer Mb n−1 and multiplexer Mc n−1, multiplexer Mb n−1 and multiplexer Mc n−1 will each select the input line labeled “1” to be their output for a particular cycle.

As explained herein, there is no Last-Xn selection input because there are no multiplexers that control the primary input into the XOR gate, XORn 316. XORn 316, being the first XOR gate in an N-bit capable CRC generator will always receive the primary input.

In FIG. 3A, multiplexer Mout 342 has N+1 input lines, namely, An 344, An−1 346, . . . , up to A0 348. If selection input Last-Xn−1 352 has a value of 1, then multiplexer Mout 342 will select An−1 346 to be CRC output 350. Similarly, if Last-Xn−2 (not shown in FIG. 3A) has a value of 1, then multiplexer Mout 342 will select An−2 (not shown in FIG. 3A) to be CRC output 350, and so on.

Even though there is no Last-Xn selection input, the effect of a selection input Last-Xn can be obtained by making the selection of An 344 as the default selection when all the selection inputs, namely, Last-X(n−1) 352, Last-X(n−2) (not shown in FIG. 3A), . . . , Last-X0 354 have a value of zero.

Additionally, multiplexers with the subscript “b”, such as Mb (n−1) 326, Mb (n−2) (not shown in FIG. 3A), Mb (n−3) (not shown in FIG. 3A), . . . , Mb 0 332 are communicatively coupled to each other. Specifically, line 392 is an output line from Mb (n−1) 326. Line 392 is also an input line to Mb (n−2) (not shown in FIG. 3A). As previously explained herein, line 393 is shown as an output line from multiplexer Mb 0 332. Line 393 is also an input line to shift register X0 314.

Multiplexers with the subscript “c” each receive a primary input, P 356. For example, multiplexers Mc (n−1) 328, Mc (n−2) (not shown in FIG. 3A), Mc (n−3) (not shown in FIG. 3A), . . . , Mc 0 334 each receive a primary input, P 356. XOR gate XORn 316 also receives primary input, P 356. Typically, primary input P 356 is a bitstream that is input into the XOR gates at the rate of one bit per cycle.

All multiplexers in the N-bit capable CRC generator have 2 input lines. One input line is labeled “1” and the other input line is labeled “0” as indicated in FIG. 3A.

The arrangement of the components in List B, i.e. the components that not shown in FIG. 3A, are the same as the arrangement of the components Y(n−1) 338, XOR(n−1) 318, Ma (n−1) 324, Mb (n−1) 326, and Mc (n−1) 328 relative to each other.

3.0 Illustrative Example of the Flexibility of an N-Bit Capable CRC Generator

Typically, N is equal to 64 or larger for the universal CRC generator. However, for simplicity of explanation, assume that that N=3 for the N-bit capable CRC generator. FIG. 5 is a block diagram that illustrates a 3-bit capable CRC generator 500. A 3-bit capable CRC generator can be used for polynomial key words of orders ranging from 1 to 3.

In FIG. 5, shift register X3 506 is communicatively coupled to corresponding XOR gate, XOR3 504. Specifically, line 550 is an output line from shift register X3 506. Line 550 is also an input line to XOR gate, XOR3 504.

Further, shift register X3 506 is communicatively coupled to adjacent multiplexers Ma 3 502 and Ma 2 508. Specifically, line 548 is an output line from shift register X3 506. Line 548 is also an input line into Ma 3 502. Line 554 is output line from Ma 2 508. Line 554 is also an input line into shift register X3 506.

Similarly, shift register X2 516 is communicatively coupled to corresponding XOR gate, XOR2 514, and to adjacent multiplexers Ma 2 508 and Ma 1 518. Specifically, line 566 is an output line from shift register X2 516. Line 566 is also an input line to XOR gate, XOR2 514. Line 568 is an output line from shift register X2 516. Line 568 is also an input line into multiplexer Ma 2 508. Line 572 is output line from multiplexer Ma 1 518. Line 572 is also an input line into shift register X2 516.

Shift register X1 526 is communicatively coupled to corresponding XOR gate, XOR1 524, and to adjacent multiplexers Ma 1 518 and Ma 0 528. Specifically, line 584 is an output line from shift register X1 526. Line 584 is also an input line to XOR gate, XOR1 524. Line 586 is an output line from shift register X1 526. Line 586 is also an input line into multiplexer Ma 1 518. Line 590 is output line from multiplexer Ma 0 528. Line 590 is also an input line into shift register X1 526.

Shift register X0 536 is communicatively coupled to XOR gate, XOR0 534. In addition, shift register X0 536 is communicatively coupled to adjacent multiplexer Ma 0 528. Specifically, line 595 is an output line from shift register X0 536. Line 595 is also an input line to XOR gate, XOR0 534. Line 593 is an output line from shift register X0 536. Line 593 is also an input line into multiplexer Ma 0 528. Line 590 is output line from multiplexer Ma 0 528.

Further, all shift registers X3 506, X2 516, X1 526, X0 536 are communicatively coupled to multiplexer Mout 589 via output lines A3 546, A2 570, A1 588, and A0 591, respectively. CRC Output 534 is the output of the 3-bit capable CRC generator 500.

Each XOR gate is additionally communicatively coupled to either one or two corresponding adjacent multiplexers. In FIG. 5, XOR gate, XOR3 504 is communicatively coupled to one adjacent corresponding multiplexer Ma 3 502. Line 552 is an output line from XOR gate, XOR3 504. Line 552 is also an input line to multiplexer Ma 3 502.

Similarly, XOR gate, XOR2 514, is communicatively coupled to adjacent corresponding multiplexers Ma 2 508 and Mc 2 512. Line 564 is an output line from XOR gate, XOR2 514. Line 564 is also an input line to multiplexer Ma 2 508. Line 562 is an output line from multiplexer Mc 2 512. Line 562 is also an input line to XOR gate, XOR2 514.

XOR gate, XOR1 524, is communicatively coupled to adjacent corresponding multiplexers Ma 1 518 and Mc 1 522. Line 582 is an output line from XOR gate, XOR1 524. Line 582 is also an input line to multiplexer Ma 1 518. Line 580 is an output line from multiplexer Mc 1 522. Line 580 is also an input line to XOR gate, XOR1 524.

XOR gate, XOR0 534, is communicatively coupled to adjacent corresponding multiplexers Ma 0 528 and Mc 0 532. Line 597 is an output line from XOR gate, XOR0 534. Line 597 is also an input line to multiplexer Ma 0 528. Line 598 is an output line from multiplexer Mc 0 532. Line 598 is also an input line to XOR gate, XOR0 534.

Programmable registers Y3 538, Y2 540, Y1 542, and Y0 544 are each communicatively coupled to corresponding multiplexers Ma 3 502, Ma 2 508, Ma 1 518, Ma 0 528 respectively.

For example, programmable register Y3 502 is communicatively coupled to Ma 3 502. Similarly, programmable register Y2 540 is coupled to Ma 2 508. Programmable register Y1 532 is coupled to Ma 1 518. Programmable register Y0 544 is coupled to Ma 0 528.

For ease of explanation, multiplexers with the same superscript as illustrated in FIG. 5 are said to belong to the same family. As can be seen in FIG. 5, multiplexers that belong to the same family are communicatively coupled to form part of a feedback loop. For example, multiplexer Ma 2 508 is communicatively coupled to mulitplexer Mb 2 510 that is in turn communicatively coupled to mulitplexer Mc 2 512. Specifically, line 556 is an output line from multiplexer Ma 2 508. Line 556 is also an input line to multiplexer Mb 2 510. Line 560 is an input line from multiplexer Mb 2 510 to mulitplexer Mc 2 512.

Similarly, Ma 1 518 is communicatively coupled to Mb 1 520 that is in turn communicatively coupled to Mc 1 522. Specifically, line 574 is an output line from multiplexer Ma 1 518. Line 574 is also an input line to multiplexer Mb 1 520. Line 578 is an input line from multiplexer Mb 1 520 to mulitplexer Mc 1 522.

Ma 0 528 is communicatively coupled to Mb 0 530 that is in turn communicatively coupled to Mc 0 532. Specifically, line 592 is an output line from multiplexer Ma 0 528. Line 592 is also an input line to multiplexer Mb 0 530. Line 596 is an input line from multiplexer Mb 0 530 to mulitplexer Mc 0 532.

However, Ma 3 502, being the sole member in its family is communicatively coupled to multiplexer Mb 2 510. Line 547 is an output line from multiplexer Ma 3 502 to multiplexer Mb 2 510.

Inputs Last-X2 583, Last-X1 587, and Last-X0 585 are selection inputs into corresponding multiplexers with subscripts “b” and “c” and which belong to the same family. For example, Last-X2 583 is a selection input into multiplexers Mb 2 510 and Mc 2 512. Last-X1 587 is a selection input into multiplexers Mb 1 520 and Mc 1 522. Last-X0 585 is a selection input into multiplexers Mb 0 530 and Mc 0 532. Further, all selection inputs Last-X2 583, Last-X1 587, and Last-X0 585 are input into multiplexer Mout 589.

Additionally, multiplexers with the subscript “b”, such as Mb 2 510, Mb 1 520. Mb 0 530 are communicatively coupled to each other. Multiplexers with the subscript “c” each receive a primary input, P 501 through line 503. For example, multiplexers Mc 2 512, Mc 1 522 and, Mc 0 532 each receive a primary input, P 501. XOR gate XOR3 504 also receives primary input, P 501 through line 503. Typically, primary input P 501 is a bitstream that is to be checked for error by the CRC generator 500. Primary input P 501 is input into the XOR gates at the rate of one bit per cycle.

As a first illustration, assume that a CRC generator is needed to implement a given 320 polynomial key word of order 3. Further assume that the given polynomial is as follows:
X3+X2+1

The 3-bit capable CRC described with reference to FIG. 5 can be converted to specifically implement the polynomial key word, X3+X2+1. In other words, by programming the values of the Y registers and the Last-X selection inputs, the 3-bit capable CRC generator becomes a X3+X2+1 key word CRC generator. For purposes of explanation, the given polynomial key word is re-written to explicitly show coefficients and missing terms. Thus, the given polynomial key word, X3+X2+1, can be re-written as:
(1)X 3+(1)X 2+(0)X 1+(1)X 0

Referring to FIG. 5, programmable register Y3 538 corresponds to coefficient of X3 of the given key word polynomial. Thus, programmable register Y3 538 is programmed to have the value of 1. In response to receiving the value of 1 from programmable register Y3 538, multiplexer Ma 3 502, will select input line labeled “1”.

Similarly, programmable register Y2 540 corresponds to coefficient X2 of the given key word polynomial. Thus, programmable register Y2 540 is programmed to have the value of 1. In response to receiving the value of 1 from programmable register Y2 540, multiplexer Ma 2 508, will select input line labeled “1”.

Programmable register Y1 542 corresponds to coefficient X1 of the given key word polynomial. Thus, programmable register Y1 542 is programmed to have the value of 0. In response to receiving the value of 0 from programmable register Y1 542, multiplexer Ma 1 518, will select input line labeled “0”.

Programmable register Y0 544 corresponds to coefficient X0 of the given key word polynomial. Thus, programmable register Y0 544 is programmed to have the value of 1. In response to receiving the value of 1 from programmable register Y0 544, multiplexer Ma 0 528, will select input line labeled “1”.

The Last-X selection inputs are programmed to be a specific value based on the most significant bit (MSB). FIG. 6 is a block diagram that illustrates the position of the MSB that is associated with the polynomial key word, X3+x2+1. In FIG. 6, bit 610 has the value of the Y3 register that is programmed to have a value of 1 described above. Since the first occurring “1” bit corresponds to the value of the Y3 register, bit 610 represents the MSB.

Similarly, bit 612 has the value of the Y2 register that is programmed to have a value of 1. Bit 614 has the value of the Y1 register that is programmed to have a value of 0. Bit 616 has the value of the Y0 register that is programmed to have a value of 1. Bit 616 is the LSB.

Since the first occurring “1” bit corresponds to the value of the Y3 register, all Last-X selection inputs, namely, Last-X2 583, Last-X1 587, and Last-X1 585 in FIG. 5 are programmed to have a value of zero.

The value of each Last-X selection input determines which input is selected at the corresponding multiplexers to be output from said multiplexers. For example, since selection input Last-X2 583 is programmed to have the value of 0, multiplexer Mb 2 510 and multiplexer Mc 2 512 will each receive the value 0 as an input. In FIG. 5, it can be seen that multiplexer Mb 2 510 and multiplexer Mc 2 512 each has 2 input lines, labeled “1” and “0”. Since the value 0 is received as the selection input, multiplexer Mb 2 510 and multiplexer Mc 2 512 will each select the input line labeled “0” to be their output for a particular cycle.

In FIG. 5, multiplexer Mout 589 has 4 input lines, namely, A3 546, A2 570, A1 588, A0 591. Since all the selection inputs, namely, Last-X2 583, Last-X1 587, Last-X0 585, have the value of 0, multiplexer Mout 589 will select A3 546 to be CRC output 534.

Thus, by programming the Y registers and the Last-X selection inputs as described above, the 3-bit capable CRC generator is equivalent to the CRC generator as described in FIG. 1 herein.

Further, the same 3-bit capable CRC generator can be programmed to implement a given polynomial key word that is of an order that is lower than 3. Assume that the given polynomial is as follows:
X1+1

For purposes of explanation, the given polynomial key word, X1+1, is re-written to explicitly show coefficients and missing terms. Thus, the given polynomial key word, X1+1, can be re-written as:
(0)X 3+(0)X 2+(1)X 1+(1)X 0

In FIG. 5 programmable register Y3 538 corresponds to coefficient of X3 of the given key word polynomial. Thus, programmable register Y3 538 is programmed to have the value of 0. In response to receiving the value of 0 from programmable register Y3 538, multiplexer Ma 3 502, will select input line labeled “0”.

Similarly, programmable register Y2 540 corresponds to coefficient X2 of the given key word polynomial. Thus, programmable register Y2 540 is programmed to have the value of 0. In response to receiving the value of 0 from programmable register Y2 540, multiplexer Ma 2 508, will select input line labeled “0”.

Programmable register Y1 542 corresponds to coefficient X1 of the given key word polynomial. Thus, programmable register Y1 542 is programmed to have the value of 1. In response to receiving the value of 1 from programmable register Y1 542, multiplexer Ma 1 518, will select input line labeled “1”.

Programmable register Y0 544 corresponds to coefficient X0 of the given key word polynomial. Thus, programmable register Y0 544 is programmed to have the value of 1. In response to receiving the value of 1 from programmable register Y0 544, multiplexer Ma 0 528, will select input line labeled “1”.

The Last-X selection inputs are programmed to be a specific value based on the most significant bit (MSB) of the Y registers. FIG. 7 is a block diagram that illustrates the position of the MSB that is associated with a X1+X0 key word. In FIG. 7, bit 710 has the value of the register Y3 that is programmed to have a value of 0 described above. Similarly, bit 712 has the value of the Y2 register that is programmed to have a value of 0.

Bit 714 has the value of the Y1 register that is programmed to have a value of 1. Since the first occurring “1” bit corresponds to the value of the Y1 register, bit 714 represents the MSB. Bit 716 has the value of the Y0 register that is programmed to have a value of 1. Bit 716 is the LSB.

Since the first occurring “1” bit corresponds to the value of register Y1, selection input Last-X1 587 is programmed to have a value of 1, and selection inputs Last-X2 583 and Last-X0 585 are programmed to have a value of 0.

The value of each Last-X selection input determines which input is selected at the corresponding multiplexers to be output from said multiplexers.

Referring back to FIG. 5, since selection input Last-X2 583 has the value 0, multiplexer Mb 2 510 and multiplexer Mc 2 512 will each select the input line labeled “0” to be their output for a particular cycle. Similarly, since selection input Last-X0 585 has the value 0, multiplexer Mb 0 530 and multiplexer Mc 0 532 will each select the input line labeled “0” to be their output for a particular cycle.

In contrast, since selection input Last-X1 587 has the value 1, multiplexer Mb 1 520 and multiplexer Mc 1 522 will each select the input line labeled “1” to be their output for a particular cycle.

In FIG. 5, multiplexer Mout 589 has 4 input lines, namely, A3 546, A2 570, A1 588, A0 591. Since the selection input Last-X1 587 has the value of 1, multiplexer Mout 589 will select A1 588 to be CRC output 534.

Thus, by programming the Y registers and the Last-X selection inputs as described above, the 3-bit capable CRC generator 500 is equivalent to the CRC generator as described in FIG. 2.

5.0 Extensions and Alternatives

In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Patent Citations
Cited PatentFiling datePublication dateApplicantTitle
US5132975 *Jul 22, 1991Jul 21, 1992Grumman Aerospace CorporationVery high speed error detection network
US5598424 *Jun 14, 1994Jan 28, 1997Xilinx, Inc.Error detection structure and method for serial or parallel data stream using partial polynomial check
US5724368 *Oct 2, 1996Mar 3, 1998Cirrus Logic, Inc.Cyclical redundancy check method and apparatus
US6192498 *Oct 1, 1998Feb 20, 2001Globepan, Inc.System and method for generating error checking data in a communications system
US6295626 *Oct 20, 1998Sep 25, 2001Nortel Networks LimitedSymbol based algorithm for hardware implementation of cyclic redundancy check
US6519738 *Mar 7, 2000Feb 11, 2003International Business Machines CorporationMethod and apparatus for high-speed CRC computation based on state-variable transformation
US6560746 *Aug 25, 1999May 6, 2003Telefonaktiebolaget Lm EricssonParallel CRC generation circuit for generating a CRC code
US6631488 *Jun 30, 2000Oct 7, 2003Agilent Technologies, Inc.Configurable error detection and correction engine that has a specialized instruction set tailored for error detection and correction tasks
US6754870 *Apr 13, 2001Jun 22, 2004Matsushita Electric Industrial Co., Ltd.CRC operation unit and CRC operation method
Referenced by
Citing PatentFiling datePublication dateApplicantTitle
US7320101 *Aug 19, 2003Jan 15, 2008Altera CorporationFast parallel calculation of cyclic redundancy checks
US7418648 *Mar 21, 2006Aug 26, 2008Marvell International Ltd.System and method for generating a cyclic redundancy check
US7613991Feb 12, 2007Nov 3, 2009Altera CorporationMethod and apparatus for concurrent calculation of cyclic redundancy checks
US7653842 *Dec 15, 2004Jan 26, 2010Fluke CorporationCRC format automatic detection and setting
US7913083 *Sep 5, 2003Mar 22, 2011Telecom Italia S.P.A.Secret-key-controlled reversible circuit and corresponding method of data processing
US8161359Aug 25, 2008Apr 17, 2012Marvell International Ltd.System and method for generating a cyclic redundancy check
US8327251 *Dec 18, 2008Dec 4, 2012Sony CorporationTransmission apparatus and method, reception apparatus and method, and program
US20100031124 *Dec 18, 2008Feb 4, 2010Sony CorporationTransmission apparatus and method, reception apparatus and method, and program
Classifications
U.S. Classification714/781, 714/758, 714/807
International ClassificationG06F11/10, H03M13/09, H03M13/00
Cooperative ClassificationH03M13/6516, H03M13/09
European ClassificationH03M13/65F3, H03M13/09
Legal Events
DateCodeEventDescription
Nov 8, 2010FPAYFee payment
Year of fee payment: 4
Aug 28, 2007CCCertificate of correction
Dec 5, 2003ASAssignment
Owner name: ASICA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, HONG-YI;REEL/FRAME:014771/0383
Owner name: MARVELL INTERNATIONAL LTD., BERMUDA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ASICA, INC.;REEL/FRAME:014771/0377
Effective date: 20031125
Jan 4, 2002ASAssignment
Owner name: ASICA, INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:CHEN, HONGYI HUBERT;REEL/FRAME:012460/0444
Effective date: 20011221