|Publication number||US7217973 B2|
|Application number||US 10/962,818|
|Publication date||May 15, 2007|
|Filing date||Oct 7, 2004|
|Priority date||Oct 8, 2003|
|Also published as||US7501319, US20050045942, US20070178632|
|Publication number||10962818, 962818, US 7217973 B2, US 7217973B2, US-B2-7217973, US7217973 B2, US7217973B2|
|Inventors||Jin Hyo Jung|
|Original Assignee||Dongbu Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (8), Non-Patent Citations (2), Referenced by (1), Classifications (43), Legal Events (8)|
|External Links: USPTO, USPTO Assignment, Espacenet|
1. Field of the Invention
The present disclosure relates to a semiconductor device and a fabricating method thereof and, more particularly, to nano-scale MOS transistors with virtual source/drain extension areas and a fabricating method thereof.
2. Background of the Related Art
A conventional ion implantation method for forming a source/drain area has several shortcomings. One of these shortcomings is that implanted impurity ions can be diffused into a channel area by a later thermal treatment. Due to such a shortcoming, if the length of a gate electrode is equal to or less than 0.06 μm, a source area and a drain area may be easily connected through impurities, therefore preventing the fabrication of a MOS transistor. Even if the length of the gate electrode is more than 0.06 μm, a short channel effect may seriously occur because the shallow depth of the source/drain area is hardly formed to be less than 10 nm. Thus, to make a nano-scale transistor (i.e., below 0.1 μm) with a source/drain extension area, a virtual source/drain extension structure employing sidewall gate electrodes is drawing attention as one of alternatives.
The oxide layer 16 for insulation is formed between the gate electrode 17 and the sidewall gates 18. The gate oxide layer 15 is positioned between the sidewall gates 18 and the P-type silicon substrate 11.
When a constant voltage is applied to the sidewall gates 18, inversion layers are generated under the sidewall gates 18. The inversion layers function as source/drain extension areas in a MOS transistor. Therefore, when a voltage is applied to the main gate electrode 17, a channel will be created and current then flows between the source 12 and the drain 13.
If highly concentrated N+ ions are implanted in the polysilicon gate electrode, the difference of the work function may be about −1.0V, and the Fermi potential may be fixed between 0.4V and 0.45V. Thus, to control a threshold voltage, two methods are typically employed. One method is to adjust the amount of electric charges in a depletion area by tuning the concentration of a silicon substrate. The other is to implant N-type or P-type impurity ions into the silicon substrate.
For example, if the dopant concentration of the substrate is 1.0×1017 ions/cm3, a highly doped N+ polysilicon gate is used, the thickness of the gate oxide layer is approximately 50 Å, and no impurity ion is implanted into the surface of the substrate, the threshold voltage of a long channel transistor may be about 0.1V, and the threshold voltage of the short channel transistor may be less than 0.1V. Therefore, if a much higher voltage (e.g., 2V to 3V) than the threshold voltage is applied to the sidewall gates, a sufficient amount or depth of the inversion layers below the sidewall floating gates will be created to form source/drain extension areas.
Under the above-mentioned condition, the threshold voltage can be increased by implanting P-type impurity ions into the surface of the substrate and decreased by implanting N-type impurity ions into the surface of the substrate. Once they are implanted, the impurity ions may be diffused by a later thermal treatment. Moreover, even if the N-type impurity ions are implanted into the surface of the substrate, the threshold voltage may not fall below −1 to −2V. Therefore, a voltage has to be applied to the sidewall gates to create the virtual source/drain extension area.
However, applying a constant voltage to the sidewall gates has several problems, in that: (1) a contact should be formed on the sidewall gates; (2) the implanted ions for controlling the threshold voltage of the sidewall gates may be diffused by a later thermal treatment and affect the threshold voltage of the main gate electrode; (3) parasitic capacitance may be generated between the sidewall gates and the main gate electrode, between the sidewall gates and a body, and between the sidewall gates and the source/drain area, thereby decreasing propagation velocity of the voltage applied to the sidewall gates and thus degrading the characteristics of the transistor; (4) because a constant voltage should continue to be applied to the sidewall gates, additional leakage current may be generated, leading to an increase in power consumption; and (5) an insulating layer between the sidewall gates and the main gate electrode may deteriorate.
U.S. Pat. No. 4,698,787, to Mukherjee et al., discloses an electrically erasable programmable memory device which is programmable in the manner of an EPROM and erasable in the manner of an EEPROM. A dielectric layer between the control gate and the floating gate having a high dielectric constant is provided. A thin, uniform gate dielectric layer which demonstrates minimal trapping is provided.
U.S. Pat. No. 5,358,885, to Oku et al., discloses a method of producing a field effect transistor which can reduce the space between the over-hanging portion of a T-shaped gate electrode and the source electrode and increases the gate-to-source capacitance.
U.S. Pat. No. 6,329,248, to Yang et al., discloses a process for making split-gate semiconductor flash memory which contains an outwardly-diverging control gate stacked on, but separated from, a pair of opposing floating gates via an interpoly dielectric layer. The split-gate flash memory eliminates the over-erase problem experienced with the self-aligned ETOX flash memory cells, while allowing its cell dimension to be maintained, using the conventional photolithography technique.
Accordingly, the present invention is directed to a semiconductor device and a fabricating method thereof that obviates one or more problems due to limitations and disadvantages of the related art.
The object of the present invention is to provide a reliable semiconductor device and a fabricating method thereof which can prevent a short channel effect in a nano-scale transistor by forming an extremely thin source/drain extension area.
Another object is to avoid the juncture of the source and drain in a nano-scale gate electrode by creating a virtual source/drain extension area.
To achieve these objects and other advantages, in accordance with the purpose(s) of the invention as embodied and broadly described herein, the present invention provides a semiconductor device comprising: polysilicon gate electrodes on a semiconductor substrate; a gate oxide layer between the polysilicon gate electrodes and the semiconductor substrate; sidewall floating gates under side portions of the polysilicon gate electrodes; a block dielectric layer between the sidewall floating gates and the semiconductor substrate; a block oxide layer between the polysilicon electrodes and the sidewall floating gates; source/drain areas in the substrate on each side of the gate electrodes; and sidewall spacers adjacent to the polysilicon gate electrodes and side wall floating gates. The polysilicon gate electrode may be a ‘T’ shaped gate electrode, which means that the upper part of the polysilicon gate electrode (i.e., farthest away from the substrate) is larger in width than the lower part of the polysilicon gate electrode (i.e., closest to the substrate).
In addition, a method for fabricating a semiconductor device according to the present invention comprises: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on the lateral faces of the trenches; forming a block oxide layer on the surface of the sidewall floating gates; forming polysilicon gate electrodes at least partly in the trenches by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers adjacent to the polysilicon gate electrodes and the sidewall floating gates.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle(s) of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.
In addition, because the depth of the virtual source/drain area is approximately 5 Å, which is very shallow, a short channel effect can be prevented, even in a nano-scale transistor. Moreover, because an impurity implantation process for decreasing the threshold voltage of the sidewall floating gates is not required, the variance of the threshold voltage of the sidewall floating gates, which is generated from the ion implantation, can be avoided.
Next, a salicide layer and interconnects (metal wire) are formed on the resulting structure by later conventional, predetermined processes.
The present invention can adjust the threshold voltage of the sidewall floating gates at a required voltage (or less) by decreasing a flat band voltage and by injecting holes/electrons or electric charges into the sidewall floating gates (e.g., comprising heavily doped polysilicon). In detail, it is believed that the flat band voltage is decreased by locking up the injected holes/electrons or charges into potential wells between the sidewall floating gates and the block oxide layer.
For example, if the sidewall floating gates comprise heavily N+-doped polysilicon, the dopant concentration of the silicon substrate is 1.0×1017 ions/cm3, the thickness of the oxide layer is 90 Å, holes or positive charges of 2.0×10−6 C/cm3 are injected into the sidewall floating gates, and the N or P type impurity ions are not implanted into the main substrate, the threshold voltage of a long channel NMOS transistor may be approximately −5V. If the holes or positive charges are injected into the potential wells of the sidewall floating gates, an extremely low threshold voltage (e.g., below 0V) may be obtained. Therefore, inversion layers are formed under the sidewall floating gates without additional biases, creating a virtual source/drain extension area.
The threshold voltage can be adjusted by controlling the amount or concentration of the holes or positive charge injected into the potential wells of the sidewall floating gates. In other words, the threshold voltage of the sidewall floating gates can be decreased by increasing the injected amount of holes or the positive charges, therefore increasing the depth or amount of the inversion layers. Thus, the parasitic resistance of the virtual source/drain extension area is decreased. As a result, a nano-scale transistor having high performance and high operating current can be manufactured.
In contrast, the threshold voltage of the sidewall floating gates can be increased by decreasing the injected amount or concentration of holes or positive charges, therefore decreasing the depth or amount of the inversion layers. Thus, the parasitic resistance of the virtual source/drain extension areas is increased. As a result, a nano-scale transistor with low leakage current can be manufactured. In addition, it is believed that the increase of the threshold voltage due to the amount of the electric charges of a depletion layer can be decreased by employing high dielectric constant materials or by decreasing the thickness of the block dielectric layer.
A transistor fabricated pursuant to the process illustrated in
Accordingly, a semiconductor device and a fabricating method thereof can decrease the threshold voltage of the sidewall floating gates (e.g., at a predetermined and/or required level) by injecting electrons/holes or electric charges into the sidewall floating gates (which may comprise highly doped polysilicon). Therefore, without applying a bias to the sidewall floating gates, inversion layers are formed under the sidewall floating gates, creating the virtual source/drain extension areas. Consequently, because the formation of contacts for applying such biases can be avoided, a manufacturing process is simplified, and the space occupied by transistors may be reduced.
Moreover, because the virtual source/drain extension areas under the sidewall floating gates is extremely thin (e.g., 5 Å), the short channel effect can be prevented, even in a nano-scale polysilicon gate electrode. Thus, reliable MOS transistors having (1) high performance and high operating current, and/or (2) low leakage current can be simultaneously fabricated.
The foregoing embodiments are merely exemplary and are not to be construed as limiting the present invention. The present teachings can be readily applied to other types of devices. The description of the present invention is intended to be illustrative, and not to limit the scope of the claims. Many alternatives, modifications, and variations will be apparent to those skilled in the art.
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|U.S. Classification||257/315, 257/E21.345, 257/E21.425, 257/E21.64, 257/317, 257/E21.634, 257/E21.421, 257/E29.264, 257/E29.266, 257/E21.434, 257/E21.682, 257/E27.103, 257/E21.635|
|International Classification||H01L29/78, H01L21/265, H01L29/788, H01L21/336, H01L27/115, H01L21/8247, H01L21/8238|
|Cooperative Classification||H01L27/115, H01L27/11521, H01L29/7833, H01L29/66484, H01L29/66553, H01L29/7831, H01L21/823814, H01L29/66643, H01L21/26586, H01L29/66583, H01L21/823828, H01L21/823864|
|European Classification||H01L29/66M6T6F11B2, H01L29/66M6T6F9, H01L29/66M6T6F1, H01L29/66M6T6F11F, H01L27/115, H01L21/8238S, H01L21/8238G, H01L29/78F, H01L21/8238D, H01L29/78E, H01L27/115F4|
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