|Publication number||US7233170 B2|
|Application number||US 11/211,955|
|Publication date||Jun 19, 2007|
|Filing date||Aug 25, 2005|
|Priority date||Aug 25, 2005|
|Also published as||US20070046335|
|Publication number||11211955, 211955, US 7233170 B2, US 7233170B2, US-B2-7233170, US7233170 B2, US7233170B2|
|Inventors||Wiren Dale Becker, Anand Haridass, Bao G. Truong|
|Original Assignee||International Business Machines Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (13), Referenced by (22), Classifications (10), Legal Events (6)|
|External Links: USPTO, USPTO Assignment, Espacenet|
The present invention relates in general to board level transmission line drivers and receivers, and in particular, to methods for compensating for timing skew between differential data channels.
Digital computer systems have a history of continually increasing the speed of the processors used in the system. As computer systems have migrated towards multiprocessor systems, sharing information between processors and memory systems has also generated a requirement for increased speed for the off-chip communication networks. Designers usually have more control over on-chip communication paths than for off-chip communication paths. Off-chip communication paths are longer, have higher noise, impedance mismatches, and have more discontinuities than on-chip communication paths. Since off-chip communication paths are of lower impedance, they require more current and thus more power to drive.
When using inter-chip high-speed signaling, noise and coupling between signal lines (cross talk) affects signal quality. One way to alleviate the detrimental effects of noise and coupling is through the use of differential signaling. Differential signaling comprises sending a signal and its compliment to a differential receiver. In this manner, noise and coupling affect both the signal and the compliment equally. The differential receiver only senses the difference between the signal and its compliment as the noise and coupling represent common mode signals. Therefore, differential signaling is resistant to the effects that noise and cross talk have on signal quality. On the negative side, differential signaling increases pin count by a factor of two for each data line. Additionally, an empty wiring channel is usually added between each differential channel which further adds to the wiring inefficiency.
The structure of a printed circuit board (PCB) is sometimes not homogeneous. It is common to find a weave structure on many laminates as shown in
A differential pair having a signal and complement signal transmitted over matched transmission lines would have a received signal waveform substantially represented by the waveforms of
With net lengths of tens of centimeters, differential skew delays due to PCB laminate weaves may approach tens of picoseconds. Presently transmission data rates of 10 gigabits per second means a bit width of only 100 picoseconds. Clearly, tens of picoseconds of in-pair timing skew for differential pairs is not negligible for these high data rates. In-pair differential skew may cause asymmetric crossover and aggravate common mode sensitivities. One solution that is been proposed is to use a diagonal trace pattern as shown in
There is, therefore, a need for a signaling scheme that enables the skew between differential data channels to be compensated without complicating layout rules. The scheme must be programmable and easy to implement and modify.
The present invention uses two single ended off-chip drivers (OCD) to implement differential signal by having each data path transmit a data signal and its complement. Each of the OCDs is preceded by a programmable delay element. The input to the delay elements are coupled to the output of a two-input multiplexer (MUX) that receives the data signal for the path and a common clock signal. Under control of a select signal, either a data signal or a common clock signal is coupled to the data path comprising a transmission lines over the non-homogeneous PCB substrate. Each of the transmission lines is terminated in a suitable terminator and received in one input of a differential receiver. The two inputs to the differential receiver are also coupled to a phase detector whose output is coupled to the input of a N×1 MUX. Skew control logic generates the select signals for the driver side MUXes as well as the select signal for the receiver side N×1 MUX. The output of the N×1 MUX is coupled as a feedback error signal to the skew control logic in a single feedback channel which is used to align each differential data channel.
To align the differential data channels, each differential data channel is selected in sequence by coupling the common clock signal to the drivers of the two transmission lines and selecting the phase detector for that channel as the output of the N×1 MUX. The skew control logic then adjusts the delays in series with each driver until the phase detector output measures a predetermined amount of phase shift or delay error. Then a next differential data channel is selected and the process is repeated until all the delays for the differential data channels are set to minimize the inter-channel timing skew.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be obvious to those skilled in the art that the present invention may be practiced without such specific details. In other instances, well-known circuits may be shown in block diagram form in order not to obscure the present invention in unnecessary detail. For the most part, details concerning timing considerations and the like have been omitted inasmuch as such details are not necessary to obtain a complete understanding of the present invention and are within the skills of persons of ordinary skill in the relevant art.
Refer now to the drawings wherein depicted elements are not necessarily shown to scale and wherein like or similar elements are designated by the same reference numeral through the several views. In the following, data channel refers to a single transmission path and differential data channel refers to a pair of transmission paths. Each differential data channel comprises transmission paths for a logic signal and the complement of the logic signal coupled to a single differential receiver.
Depending on the “value” of the phase error feedback signal 805, skew controller adjusts the delays of programmable delay elements 601 and 602 until the phase error feedback 805 indicates that the timing skew between the data channels in differential data channel 1 is within a predetermined minimum value. When this value is reached, the program values of program signals 603 and 604 are latched or held while the next channel is selected for alignment. Alignment continues until differential data channel N is aligned using phase detector 804. When the alignments are completed, then skew controller 801 signals to the system (e.g., system 1300) that bus alignment is complete and the system can switch to operation mode wherein actual data signals (e.g., Data 103 and Data_b 105) are transmitted between the driver side and the receiver.
State 1: first delay signal 901 lags second delay signal 902 and PD_out 904 is a logic 1 and PD_out 905 is a logic 0.
State 2: first delay signal 901 leads second delay signal 902 and PD_out 904 is a logic 0 and PD_out 905 is a logic 1.
State 3: first delay signal 901 is in phase with second delay signal 902 and PD_out 904 is a logic 1 and PD_out 905 is a logic 1.
State 4: the phase difference between first delay signal 901 and second delay signal 902 is indeterminate and PD_out 904 is a logic 0 and PD_out 905 is a logic 0.
It is understood that other phase detector states may be used that are compatible with a skew controller 801 and still be within the scope of the present invention.
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
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|U.S. Classification||326/93, 327/158, 327/161|
|Cooperative Classification||H03K5/135, H04L25/0276, H03K5/00|
|European Classification||H03K5/00, H03K5/135, H04L25/02K3C|
|Sep 13, 2005||AS||Assignment|
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BECKER, WIREN DALE;HARIDASS, ANAND;TRUONG, BAO G.;REEL/FRAME:016783/0043;SIGNING DATES FROM 20050822 TO 20050823
|Jan 24, 2011||REMI||Maintenance fee reminder mailed|
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|May 18, 2011||FPAY||Fee payment|
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|Jul 12, 2011||AS||Assignment|
Owner name: GOOGLE INC., CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:026664/0866
Effective date: 20110503
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