|Publication number||US7233880 B2|
|Application number||US 10/660,310|
|Publication date||Jun 19, 2007|
|Filing date||Sep 11, 2003|
|Priority date||Sep 11, 2003|
|Also published as||CN1849593A, CN100573475C, DE602004004414D1, DE602004004414T2, EP1668514A1, EP1668514B1, US20050060126, US20060122805, WO2005026965A1|
|Publication number||10660310, 660310, US 7233880 B2, US 7233880B2, US-B2-7233880, US7233880 B2, US7233880B2|
|Inventors||Richard L. Coulson, Brian A. Leete|
|Original Assignee||Intel Corporation|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (24), Referenced by (4), Classifications (19), Legal Events (5)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This invention relates generally to electronic memories which may be sensitive to higher temperature environments.
In many cases, electronic memories may be subjected to higher temperature operating environments. For example, within a notebook or mobile personal computer, elevated temperatures may be encountered. Some types of memory may cease to function correctly at extended temperatures.
Ferroelectric polymer memory uses a polymer between a pair of electrodes. Ferroelectric polymer memories may be subject to voltage based disturbs at higher temperatures. At higher temperatures, a ferroelectric polymer memory may slow down its operation in order to function correctly.
This tendency to reduce speed at extended temperatures may complicate the operation of the system which relies on the ferroelectric polymer memory or other temperature sensitive memories. The slower data transfer rate may be unexpected by the rest of the system, since the remainder of the system may not be aware of the higher temperature conditions. Thus, the unexpected speed reduction may create unexpected problems in processor-based systems that rely on these memories, for example for caching purposes.
Thus, there is a need for a way to adapt processor-based systems to temperature sensitive memories.
The system 10 may include a processor 12 coupled in one architecture to a memory control hub 16. The hub 16 may in turn be coupled to an input/output control hub 18 in that architecture. The input/output control hub 18 may be coupled to a disk drive 20 and a cache memory 22. The cache memory 22 may be temperature sensitive. As examples, the temperature sensitive cache memory may be a ferroelectric polymer memory or a flash memory.
The memory 22 may include a temperature sensor 24 in one embodiment of the present invention. The temperature sensor 24 may be a silicon diode formed on or integrated into the memory 22 in one embodiment.
Although a particular architecture is illustrated in
The processor 12 may include a storage 14 that stores a cache driver 14 that executes on the processor 12. The cache driver 14 adapts the processor-based system 10 to the vagaries of the cache memory 22 and, particularly, to its temperature sensitivity. For example, in one embodiment, when the temperature rises, and the memory 22 has a slower data transfer rate, the cache driver 14 may enable the system to adapt. The driver 14 itself may adapt to make more optimal decisions about what data to cache and not cache based on its knowledge of the cache's current data rate in view of the detected temperature.
Whenever the driver 14 makes a request to the cache memory 22, a status code is returned. This status code includes whether the operation succeeded or failed, whether error correction was applied, how much was applied, and the cache's temperature environment.
The system 10 transitions from the normal operation state 26, to a reduced speed operation state 28, for example when the cache memory 22 is exposed to an elevated temperature environment called the throttle temperature range. In one embodiment, the temperature sensor 24 may detect that a higher temperature environment has been encountered. This higher or throttle temperature environment may be a temperature in the range of 60 to 80° C. in an embodiment where the cache memory 22 is a ferroelectric polymer memory.
In this throttle temperature range, the cache memory 22 may be exposed to voltage disturbs if it does not reduce its data transfer rate. A voltage disturb is a voltage that causes data to be written incorrectly. The use of the memory 22 may be adjusted for reduced speed operation, if any, at state 28. For example, in one embodiment, the cache driver 14 may avoid operations like pre-fetching or other speculative data acquisitions that may necessitate higher data transfer rates than the cache memory 22 can currently support. Also, the timing of the control logic on the memory 22 may be slowed down.
From the reduced speed operation state 28, the system may transition to an operation safe for sudden shutdown state 30. This may occur when the temperature becomes even more elevated. In one embodiment, using a cache memory 22 that is a ferroelectric polymer memory, the state 30 may be encountered at a critical temperature of 80 to 85° C.
In the state 30, the system 10 switches to a write-through caching algorithm and dirty cache lines (i.e., those that have not been written to system memory) are flushed. The system 10 may be close to the upper temperature or shutoff temperature of the cache memory 22. Thus, the cache driver 14 software or its hardware equivalent, changes algorithms so that it can shut off at any time without compromising data integrity. The driver 14 may cause the memory 22 to operate as a write-through cache rather than a write-back cache so that there is no dirty data in the cache.
The next transition, to the cache shutdown state 32, may occur at a shut-off temperature of about 85° C. in the embodiment in which the cache memory 22 is a ferroelectric polymer memory. In this transition, cache lines may be invalidated and the cache memory 22 may be shut off.
The system 10 then waits for a reduced or critical temperature range to introduce hysteresis in state 34. Alternatively, the system may wait until a reboot/resume before resuming reduced speed cache operations. From the hysteresis state 34, the system 10 may transition back to reduced speed operation state 28 by initializing a cache state, beginning the use of the cache, and using reduced speed algorithms. In the reduced speed operation state 28, with reduced temperature, the system 10 may adjust the algorithm for full speed operations, eventually returning, as indicated at F, to the normal operation state 26 at the normal temperature range.
Transitions may be spurred by the temperature sensor 24 that provides the temperature information to the cache driver 14 to appropriately control the operation of the system 10. For example, in the transition A, the temperature sensor 24 may indicate a throttle temperature range through the cache driver 14. The transition B may be initiated in response to a critical temperature range and the transition C may be indicated in response to the detection of a shutoff temperature. The transition D may be the result of a status indication of a critical temperature. The transition E may be the result of a status indication of a throttle temperature range, while the transition F may result from a status indication of a normal temperature range.
When the temperature sensed by the temperature sensor 24 is rising, the cache memory 22 is switched to write-through caching, so if the temperature rises further, and cache memory 22 shutdown is necessary, it can be done without loss of data integrity. The cache memory 22 operates in a shutdown safe mode without dirty data in the cache. The critical range is set sufficiently below the shutdown temperature to allow margin for writing the dirty data before the temperature rises to shutdown.
If the temperature reaches the shutdown temperature, the cache memory 22 is no longer used. The contents of the cache memory 22 are invalidated so that, in case of a crash and recovery, it is clear that the contents of a cache memory 22 are invalid. As the temperature cools, there are two choices in some embodiments. Under one choice, the system 10 can wait until a reboot or resume to start up the cache memory 22 again. Alternatively, the system 10 can wait until the temperature is below the critical temperature. In either case, the cache memory 22 may be reinitialized and started from empty.
Next, a check at diamond 40 determines whether or not a critical temperature has been exceeded. If so, the cache memory 22 may be switched to operate as a write-through cache as indicated in block 42. Also, any dirty lines may be flushed as indicated in block 44.
Thereafter, the driver 14 monitors for the occurrence of a shutoff temperature as determined in diamond 46. If it is detected, the cache memory 22 may be shutdown as indicated in block 48. Thereafter, the memory 22 may transition back through a hysteresis state 34 to a reduced speed operation state 28, back to normal operation as shown in
Thus, despite temperature sensitivity, some memories can be used as cache memories, for disk caching purposes for example, when the operating range is less than the possible temperatures experienced in real life usage. In one such case, the cache memory 22 may be utilized as a disk cache to cache information read off the disk drive 20.
While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.
|Cited Patent||Filing date||Publication date||Applicant||Title|
|US5091846 *||Oct 30, 1989||Feb 25, 1992||Intergraph Corporation||Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency|
|US5155843 *||Jun 29, 1990||Oct 13, 1992||Digital Equipment Corporation||Error transition mode for multi-processor system|
|US5524212 *||Apr 27, 1992||Jun 4, 1996||University Of Washington||Multiprocessor system with write generate method for updating cache|
|US5524234 *||Dec 28, 1994||Jun 4, 1996||Cyrix Corporation||Coherency for write-back cache in a system designed for write-through cache including write-back latency control|
|US5598395 *||Oct 28, 1994||Jan 28, 1997||Olympus Optical Co., Ltd.||Data loss prevention in a cache memory when the temperature of an optical recording medium is abnormal|
|US5608892 *||Jun 9, 1995||Mar 4, 1997||Alantec Corporation||Active cache for a microprocessor|
|US5664149 *||Nov 12, 1993||Sep 2, 1997||Cyrix Corporation||Coherency for write-back cache in a system designed for write-through cache using an export/invalidate protocol|
|US5719800 *||Jun 30, 1995||Feb 17, 1998||Intel Corporation||Performance throttling to reduce IC power consumption|
|US5815648 *||Nov 14, 1995||Sep 29, 1998||Eccs, Inc.||Apparatus and method for changing the cache mode dynamically in a storage array system|
|US5860111 *||Jun 29, 1995||Jan 12, 1999||National Semiconductor Corporation||Coherency for write-back cache in a system designed for write-through cache including export-on-hold|
|US5870616 *||Oct 4, 1996||Feb 9, 1999||International Business Machines Corporation||System and method for reducing power consumption in an electronic circuit|
|US5875466 *||Feb 28, 1997||Feb 23, 1999||Alantec Corporation||Active cache for a microprocessor|
|US5974438 *||Dec 31, 1996||Oct 26, 1999||Compaq Computer Corporation||Scoreboard for cached multi-thread processes|
|US6029006 *||Dec 23, 1996||Feb 22, 2000||Motorola, Inc.||Data processor with circuit for regulating instruction throughput while powered and method of operation|
|US6088799 *||Dec 11, 1997||Jul 11, 2000||International Business Machines Corporation||Security method and system for persistent storage and communications on computer network systems and computer network systems employing the same|
|US6470289 *||Aug 5, 1999||Oct 22, 2002||Compaq Information Technologies Group, L.P.||Independently controlling passive and active cooling in a computer system|
|US6662136 *||Apr 10, 2001||Dec 9, 2003||International Business Machines Corporation||Digital temperature sensor (DTS) system to monitor temperature in a memory subsystem|
|US6725342 *||Sep 26, 2000||Apr 20, 2004||Intel Corporation||Non-volatile mass storage cache coherency apparatus|
|US6941423 *||Dec 22, 2003||Sep 6, 2005||Intel Corporation||Non-volatile mass storage cache coherency apparatus|
|US6970985 *||Jul 9, 2002||Nov 29, 2005||Bluerisc Inc.||Statically speculative memory accessing|
|US20050073869 *||Sep 11, 2003||Apr 7, 2005||Gudesen Hans Gude||Method for operating a ferroelectric of electret memory device, and a device of this kind|
|EP0606779A2||Dec 30, 1993||Jul 20, 1994||Digital Equipment Corporation||Improved phase comparator|
|EP1182552A2||Oct 24, 2000||Feb 27, 2002||Texas Instruments France||Dynamic hardware configuration for energy management systems using task attributes|
|WO2004025658A1 *||Sep 10, 2003||Mar 25, 2004||Broems Per||A method for operating a ferroelectric or electret memory device, and a device of this kind|
|Citing Patent||Filing date||Publication date||Applicant||Title|
|US7669043 *||Sep 28, 2005||Feb 23, 2010||Fujitsu Limited||Memory parameter initialization based on a temperature acquired at startup|
|US8612677||Nov 7, 2012||Dec 17, 2013||Kabushiki Kaisha Toshiba||Memory system and method of writing data in a memory system|
|US8782667 *||Dec 27, 2010||Jul 15, 2014||International Business Machines Corporation||Weather adaptive environmentally hardened appliances|
|US20120167093 *||Jun 28, 2012||International Business Machines Corporation||Weather adaptive environmentally hardened appliances|
|U.S. Classification||702/186, 711/E12.04, 711/143, 711/E12.017, 714/E11.018, 711/142|
|International Classification||G06F11/00, G06F12/08, G06F11/30, G06F1/20|
|Cooperative Classification||G06F12/0802, G06F1/206, G06F11/00, G06F12/0866, G06F12/0804|
|European Classification||G06F12/08B, G06F11/00F, G06F1/20T, G06F12/08B2|
|Sep 11, 2003||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:BOULSON, RICHARD L.;LEETE, BRIAN A.;REEL/FRAME:014497/0371;SIGNING DATES FROM 20030902 TO 20030908
|Dec 16, 2010||FPAY||Fee payment|
Year of fee payment: 4
|Nov 19, 2014||FPAY||Fee payment|
Year of fee payment: 8
|Mar 16, 2015||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR RICHARD L. COULSON S NAME IS INCORRECTLY TYPED. PREVIOUSLY RECORDED ON REEL 014497 FRAME 0371. ASSIGNOR(S) HEREBY CONFIRMS THE THE USPTO INCORRECTLY TYPED ASSIGNOR RICHARD L. COULSON S NAME.;ASSIGNORS:COULSON, RICHARD L.;LEETE, BRIAN A.;SIGNING DATES FROM 20030902 TO 20030909;REEL/FRAME:035207/0591
|Mar 17, 2015||AS||Assignment|
Owner name: INTEL CORPORATION, CALIFORNIA
Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR RICHARD L. COULSON S NAME INCORRECTLY RECORDED. PREVIOUSLY RECORDED ON REEL 014497 FRAME 0371. ASSIGNOR(S) HEREBY CONFIRMS THE USPTO INCORRECTLY RECORDED ASSIGNOR RICHARD L. COULSON S NAME.;ASSIGNORS:COULSON, RICHARD L.;LEETE, BRIAN A.;SIGNING DATES FROM 20030902 TO 20030909;REEL/FRAME:035208/0844