|Publication number||US7235887 B2|
|Application number||US 10/912,861|
|Publication date||Jun 26, 2007|
|Filing date||Aug 6, 2004|
|Priority date||Aug 22, 2003|
|Also published as||US20050040514|
|Publication number||10912861, 912861, US 7235887 B2, US 7235887B2, US-B2-7235887, US7235887 B2, US7235887B2|
|Inventors||Jong-Ung Lee, Wha-Su Sin, Jong-Keun Jeon|
|Original Assignee||Samsung Electronics Co., Ltd.|
|Export Citation||BiBTeX, EndNote, RefMan|
|Patent Citations (31), Non-Patent Citations (5), Referenced by (8), Classifications (48), Legal Events (4)|
|External Links: USPTO, USPTO Assignment, Espacenet|
This U.S. non-provisional application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2003-58274 filed Aug. 22, 2003, the contents of which are incorporated by reference.
1. Field of the Invention
The present invention relates generally to electronic packaging technology and, more particularly, to semiconductor packages having improved chip-attaching structures and methods for manufacturing the semiconductor packages with improved chip-attaching reliability.
2. Description of the Related Art
In general, an electronic package or a semiconductor package is defined as the housing and interconnection of integrated circuits (also referred to as ‘semiconductor chips’, ‘chips’, or ‘die’) to form an electronic system. The functions which the package must provide include a structure to physically support the chip, a physical housing to protect the chip from the environment, an adequate means of removing heat generated by the chips or system, and electrical connections to allow signal and power access to and from the chip.
An example of a conventional semiconductor package is shown in
The chip 11 is disposed on an upper surface of the substrate 12, and the solder balls 17 are arranged on a lower surface of the substrate 12. The bonding wires 13 electrically connect chip pads 11 a of the chip 11 and substrate pads 12 a of the substrate 12. The adhesive layer 14 physically attaches and supports the chip 11 to the substrate 12. The encapsulating layer 15 protects the chip 11, the wires 13, and the upper surface of the substrate 12 from the environment.
The above-described conventional package 10 has drawbacks as follows.
First, adhesive material used for the adhesive layer 14 may often overflow beyond the boundary 11 b of the chip 11. Unfortunately, an overflowing part 14 a of the adhesive layer 14 tends to affect and contaminate the substrate pads 12 a. This may result in poor bonding of the wires 13 on the substrate pads 12 a.
Second, the chip 11 and the substrate 12 may warp due to a difference in the coefficient of thermal expansion (CTE) during a chip attaching process and may be restored after the chip attaching process. This often causes what is called an under-coverage problem where the aforementioned overflowing part 14 a enters between the chip 11 and the substrate 12.
Third, when the encapsulating layer 15 is formed, unfavorable adhesive voids may form between the chip 11 and the substrate 12. In most cases, such adhesive voids are a prime cause of low attaching reliability.
A semiconductor package comprises a chip having a top surface for chip pads and a bottom surface opposite the top surface. The top and bottom surfaces define side surfaces. The package further includes an adhesive layer provided within a chip-attaching area substantially defined by side surfaces of the chip and attaches a chip to, for example, a substrate having substrate pads. This prevents the contamination of the substrate pads by the adhesive layer. In one embodiment, the adhesive layer has at least one hole formed therethrough to expose a portion of the bottom surface of the chip. The adhesive layer may include at least one passage laterally connecting the hole to the outside. Alternatively, the adhesive layer has a plurality of adhesive parts separately disposed on the semiconductor chip.
According to another embodiment of the present invention, a method for manufacturing a semiconductor package comprises providing a substrate having a plurality of substrate pads; providing a semiconductor chip having a top surface on which a plurality of chip pads are formed, the chip having a bottom surface opposite the top surface, the top and bottom surfaces defining side surfaces; providing an adhesive layer on the substrate within a chip-attaching area substantially defined by the side surfaces of the chip, the adhesive layer having at least one hole formed therein to expose a portion of the bottom surface; and placing the chip onto the adhesive layer and attaching the chip to the substrate through the adhesive layer
The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which several preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and is not limited to the embodiments presented in this disclosure. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
In the description, well-known structures and processes have not been shown in detail to avoid obscuring the present invention. It will be appreciated that for simplicity and clarity of illustration, some elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for clarity. Like numerals are used for like and corresponding parts of the various drawings.
The chip 110 is disposed on an upper surface of the substrate 120, and the solder balls 170 are arranged on a lower surface of the substrate 120. The bonding wires 13 electrically connect chip pads 114 of the chip 110 and substrate pads 121 of the substrate 120. The adhesive layer 140 physically attaches and supports the chip 110 to the substrate 120. The encapsulating layer 150 protects the chip 110, the wires 130, and the upper surface of the substrate 120 from the environment.
The chip 110 may have a top surface 111, sometimes referred to as an active surface, on which the chip pads 114 are formed. The chip 110 further has a bottom surface 112 facing the substrate 120 and a side surface 113 connecting the top surface 111 and the bottom surface 112.
The adhesive layer 140 may have an outer periphery 141 and a hole 143 surrounded with an inner periphery 142. Thus, the hole 143 of the adhesive layer 140 can expose a corresponding portion of the substrate 120 or of the semiconductor chip 110. In one embodiment the hole extends through the adhesive layer before attaching the semiconductor chip 110 to another object such as a substrate or other chip. The adhesive layer 140 further may have at least one passage 144 laterally connecting the hole 143 to the outside of the adhesive layer 140.
The hole 143 serves to gather some of the aforementioned adhesive voids, such as those produced between the chip 110 and the substrate 120 when the encapsulating layer 150 is formed. The passage 144 provides a path that permits the adhesive voids to be exhausted outward, most likely in directions indicated by arrows in the drawing, under vacuum atmosphere, as mentioned above. This embodiment employs one hole 143 and four passages 144, however the number of them or a shape thereof is not necessarily limited to this embodiment.
The disk-like adhesive parts 240 may occupy the same relative positions as the respective chip pads 114 do. For comparison,
The present invention can be also effectively applied to other package structures, for example, three-dimensional chip stack embodiments, which are shown in
Referring to the embodiment in
Specifically, the additional adhesive layer 340 may physically attach a relatively upper chip to a relatively lower chip. The adhesive layer 340 may then be provided on the lower chip within a chip-attaching area defined by a side surface 311 of the upper chip. The adhesive layer 340 has at least one hole and at least one passage for the exhaust of the adhesive voids. Preferably, the adhesive layer 340 is composed of a plurality of disk-like adhesive parts. Further, the additional bonding wires 330 electrically connect the stacked chips 310 to the substrate 120.
As shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
Finally, a plurality of solder balls 470 may be formed on the lower surface 120 a of the substrate 120 to provide electrical connections between the package 400 and an external electronics.
While this invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
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|U.S. Classification||257/783, 257/E23.069, 257/E21.505, 257/779, 257/E21.514, 257/777, 257/781, 257/780, 257/782, 257/778, 257/784|
|International Classification||H01L23/02, H01L23/48, H01L29/40, H01L21/58, H01L23/498, H01L23/52|
|Cooperative Classification||H01L2225/0651, H01L2224/32014, H01L24/32, H01L24/83, H01L2924/01033, H01L2924/01023, H01L2924/01006, H01L2224/32145, H01L2224/48091, H01L2225/06575, H01L2224/73265, H01L2224/8592, H01L2924/07802, H01L2224/92247, H01L2924/014, H01L2224/743, H01L2224/83194, H01L23/49816, H01L2924/14, H01L2224/2919, H01L2224/32225, H01L2224/48227, H01L2924/15311, H01L24/743, H01L24/27, H01L2224/8385, H01L2924/0665|
|European Classification||H01L24/743, H01L24/32, H01L24/83, H01L24/27|
|Dec 6, 2004||AS||Assignment|
Owner name: SAMSUNG ELECTRONICS CO., LTD., KOREA, REPUBLIC OF
Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, JONG-UNG;SIN, WHA-SU;JEON, JONG-KEUN;REEL/FRAME:015429/0220
Effective date: 20040408
|Jan 31, 2011||REMI||Maintenance fee reminder mailed|
|Jun 26, 2011||LAPS||Lapse for failure to pay maintenance fees|
|Aug 16, 2011||FP||Expired due to failure to pay maintenance fee|
Effective date: 20110626