Publication number | US7236047 B2 |

Publication type | Grant |

Application number | US 11/260,176 |

Publication date | Jun 26, 2007 |

Filing date | Oct 28, 2005 |

Priority date | Aug 19, 2005 |

Fee status | Paid |

Also published as | US20070040600 |

Publication number | 11260176, 260176, US 7236047 B2, US 7236047B2, US-B2-7236047, US7236047 B2, US7236047B2 |

Inventors | Suguru Tachibana, Kazuhiro Mitsuda, Tatsuo Kato |

Original Assignee | Fujitsu Limited |

Export Citation | BiBTeX, EndNote, RefMan |

Patent Citations (9), Non-Patent Citations (1), Referenced by (24), Classifications (4), Legal Events (8) | |

External Links: USPTO, USPTO Assignment, Espacenet | |

US 7236047 B2

Abstract

A band gap circuit includes a voltage generating circuit, and a first and a second switched capacitor circuits (SCC). Operational amplifier in the first and the second SCC are connected though a coupling capacitor. Capacitance of the coupling capacitor is smaller than that of a feedback capacitor in the first SCC. A PTAT voltage is obtained by multiplying a thermal voltage by a coefficient determined based on capacitances of input capacitors and feedback capacitors in each of the first and the second SCC, and the coupling capacitor. The voltage generating circuit generates a forward bias voltage that has a negative temperature-dependency at a p-n junction. The PTAT voltage is added to the forward bias voltage to generate a reference voltage independent of temperature.

Claims(7)

1. A band gap circuit that generates a reference voltage, comprising:

a voltage generating circuit configured to generate a voltage having negative temperature dependency;

a first switched-capacitor circuit including

a first operational amplifier circuit having an input terminal and an output terminal;

a first input capacitor that is connected to the input terminal of the first operational amplifier circuit; and

a first feedback capacitor that is connected to the input terminal and the output terminal of the first operational amplifier circuit;

a second switched-capacitor circuit including

a second operational amplifier circuit having an input terminal and an output terminal;

a second input capacitor that is connected to the input terminal of the second operational amplifier circuit; and

a second feedback capacitor that is connected to the input terminal and the output terminal of the second operational amplifier circuit; and

a first coupling capacitor that capacitively couples the output terminal of the second operational amplifier circuit with the input terminal of the first operational amplifier circuit, wherein

a thermal voltage, which is a voltage proportional to absolute temperature, is multiplied by a coefficient, and a multiplied thermal voltage is added to the voltage generated by the voltage generating circuit, the coefficient being determined based on capacitances of the first input capacitor, the first feedback capacitor, the first coupling capacitor, the second input capacitor, and the second feedback capacitor,

wherein the first coupling capacitor is configured to have a capacitance smaller than a capacitance of the first feedback capacitor.

2. The band gap circuit according to claim 1 , further comprising:

a third switched-capacitor circuit including

a third operational amplifier circuit having an input terminal and an output terminal;

a third input capacitor that is connected to the input terminal of the third operational amplifier circuit; and

a third feedback capacitor that is connected to the input terminal and the output terminal of the third operational amplifier circuit; and

a second coupling capacitor that capacitively couples the output terminal of the third operational amplifier circuit with the input terminal of the second operational amplifier circuit so that capacitances are coupled, wherein

the coefficient is determined further based on capacitances of the second coupling capacitor, the third input capacitor, and the third feedback capacitor.

3. The band gap circuit according to claim 2 , wherein the second coupling capacitor is configured to have a capacitance smaller than a capacitance of the second feedback capacitor.

4. The band gap circuit according to claim 1 , further comprising:

an x-th switched-capacitor circuit including

an x-th operational amplifier circuit having an input terminal and an output terminal;

an x-th input capacitor that is connected to the input terminal of the x-th operational amplifier circuit; and

an x-th feedback capacitor that is connected to the input terminal and the output terminal of the x-th operational amplifier circuit;

an (x−1)-th operational amplifier circuit; and

an (x−1)-th coupling capacitor that capacitively couples the output terminal of the x-th operational amplifier circuit with the input terminal of the (x−1)-th operational amplifier circuit so that capacitances are coupled, where x is a positive integer that is equal to or larger than 4, wherein

the coefficient is determined further based on capacitances of the (x−1)-th coupling capacitor, the x-th input capacitor, and the x-th feedback capacitor.

5. The band gap circuit according to claim 4 , wherein the (x−1)-th coupling capacitor is configured to have a capacitance smaller than a capacitance of the x-th feedback capacitor.

6. The band gap circuit according to claim 1 , wherein the voltage generating circuit generates a voltage so that a positive-negative junction is forward biased.

7. The band gap circuit according to claim 2 , wherein each of the first operational amplifier circuit, the second operational amplifier circuit, and the third operational amplifier circuit includes an operational amplifier circuit of a folded cascode type.

Description

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-238729, filed on Aug. 19, 2005, the entire contents of which are incorporated herein by reference.

1. Field of the Invention

The present invention relates to a band gap (or bandgap) circuit based on a switched-capacitor technique.

2. Description of the Related Art

A band gap circuit is commonly used in analog integrated circuits (ICs) and complementary metal oxide semiconductor (CMOS) analog circuits as a reference-voltage circuit. The band gap circuit generates a constant reference voltage that is independent of temperature and power source voltage.

However, a band gap circuit utilizes a potential of a forward biased positive-negative (p-n) junction that has a negative temperature-dependency. In other words, the potential decreases as temperature increases. Therefore, a voltage that is proportional to absolute temperature (PTAT) is added to generated reference voltage to obtain a reference voltage that is independent of temperature.

The band gap circuits based on a switched capacitor technique (hereinafter, “switched-capacitor band gap circuit”) are known in the art. In the switched-capacitor band gap circuit, a capacitance ratio is used to obtain a desirable PTAT voltage by multiplying a thermal voltage k·T/q by a coefficient, where q is an electrical charge of electrons, k is the Boltzmann constant, and T is absolute temperature. In an integrated circuit, the capacitance ratio can be obtained at the highest accuracy. Therefore, in the switched-capacitor band gap circuit, which uses the capacitance ratio, a desirable PTAT voltage can be obtained with high accuracy based on the thermal voltage. In other words, switched-capacitor band gap circuits can generate highly accurate reference voltage.

A switched-capacitor band gap circuit shown in **1** is connected to a noninverting input (+) of an operational amplifier circuit OP**1**. A base and a collector of the PNP bipolar transistor Q**1** are connected to a ground GND. An inverting input (−) of the operational amplifier circuit OP**1** is connected to the ground GND via a capacitor C**1**.

The inverting input (−) is connected to an output of the operational amplifier circuit OP**1** via a capacitor C**2**. A switch S**1** is connected in parallel with the capacitor C**2**. A current source I**1** is connected to the emitter of the bipolar transistor Q**1** and a current source I**2** is coupled between the emitter of the bipolar transistor Q**1** and a positive power source Vdd via a switch S**2**.

The current sources I**1** and I**2** output currents I**1** and I**2** respectively. The capacitors C**1** and C**2** have capacitances C**1** and C**2** respectively. Vo is an output reference potential of the operational amplifier circuit OP**1**. N**1** and N**2** are nodes.

When a base-to-emitter voltage, which is a forward bias voltage at the p-n junction, is Vbe, a relationship between Vbe and absolute temperature T is expressed as

*Vbe=Veg−a·T* (1)

where Veg is a band gap voltage (approximately 1.2 volts (V)) of silicon, and a is temperature dependency (approximately 2 mV/° C.) of Vbe.

Furthermore, a relationship between a current I of the emitter, which is a current of a diode, and Vbe is expressed as

*I=I*0 exp(*q·Vbe/k·T*) (2)

where q is an electrical charge of electrons, and k is the Boltzmann constant.

As shown in **1** is closed and the switch S**2** is open. Since the switch S**1** is closed, a potential of the node N**2** is equal to an output potential of the operational amplifier circuit OP**1**. In addition, since the switch S**2** is open, the current I**1** flows through the PNP bipolar transistor Q**1**. A potential of the node N**2** is Vbe**1** when the base-to-emitter voltage is Vbe**1**. Consequently, an electrical charge that can be accumulated at the node N**2** while the switch S**1** is closed is C**1**×Vbe**1**.

Then, the switch S**1** is opened and the switch S**2** is closed. As the switch S**1** is open, the electrical charge of the node N**2** is conserved. In addition, currents flow into the PNP bipolar transistor Q**1** from both of the current sources I**1** and I**2**. Thus, the current flowing through the PNP bipolar transistor Q**1** increases from I**1** to I**1**+I**2**, and the potential of the node N**1** increases.

When I**1**+I**2**=m·I**1** where m is a coefficient, relationships between I**1** and Vbe**1**, and between I**2** and Vbe**2** are expressed as

*I*1*=I*0 exp(*q·Vbe*1/*k·T*) (3)

*m·I*1*=I*0 exp(*q·Vbe*2/*k·T*) (4)

where the base-to-emitter voltage when the current m·I**1** flows through the PNP bipolar transistor Q**1** is Vbe**2**.

By performing division on Equation 3 and Equation 4, the following Equation 5 is obtained.

*m*=exp(*q·Vbe*2/*k·T−qVbe*1/*k·T*) (5)

When Equation 5 is solved for ΔVbe assuming Vbe**2**−Vbe**1**=ΔVbe, Equation 6 is obtained.

Δ*Vbe*=(*k·T/q*)ln(*m*) (6)

The potential of the node N**1** increases by ΔVbe from Vbe**1** to be Vbe**2**. Therefore, if a gain of the operational amplifier circuit OP**1** is sufficiently large, the potential of the node N**2** also increases by ΔVbe to be Vbe**2**. An output potential of the operational amplifier circuit OP**1** is determined to conserve the electrical charge of the node N**2**. As the potential of the node N**2** increases, the electrical charge of the node N**2** increases. The increased amount Δq**1** is expressed as

*Δq*1*=C*1*·ΔVbe* (7)

On the other hand, if the output potential of the operational amplifier circuit OP**1** increases, the electrical charge of the node N**2** decreases. The decreased amount Δq**2** is expressed as

Δ*q*2*=C*2(Δ*Vo−ΔVbe*) (8)

where the increased amount in the output potential of the operational amplifier circuit OP**1** is ΔVo.

Since Δq**1** and Δq**2** are equal to each other, the following Equation 9 is obtained.

*C*1*·ΔVbe=C*2(Δ*Vo−ΔVbe*) (9)

When Equation 9 is solved for ΔVo, Equation 10 is obtained.

Δ*Vo=ΔVbe*+(*C*1/*C*2)*ΔVbe* (10)

Consequently, the output reference potential Vo of the operational amplifier circuit OP**1** is finally obtained by the following Equation 11.

The forward bias voltage Vbe**2** at the p-n junction has a negative temperature-dependence as shown in Equation 1. On the other hand, ΔVbe increases in proportion to temperature as shown in Equation 6. Therefore, by setting C**1**/C**2** at an appropriate value, the circuit can be designed so as to obtain the output reference potential Vo independent of temperature. In such a condition, Vo corresponds to a band gap voltage of silicon, and is 1.2 V. Thus, in the circuit shown in

A circuit shown in **2** is connected to a noninverting input (+) of an operational amplifier circuit OP**2**. A base and a collector of the PNP bipolar transistor Q**2** are connected to the ground GND. Moreover, an emitter of a PNP bipolar transistor Q**3** is connected to an inverting input (−) of the operational amplifier circuit OP**2** through a capacitor C**3**. A base and a collector of the PNP bipolar transistor Q**3** are connected to the ground GND.

The noninverting input (+) of the operational amplifier circuit OP**2** is connected to a switch S**3**. A capacitor C**4** is coupled between the switch S**3** and the inverting input (−). A switch S**4** is coupled between an output of the operational amplifier circuit OP**2** and the capacitor C**4**. A switch S**5** is coupled between the output and the inverting input (−). A current sources I**1** and nI**1** are coupled through switches S**6** and S**7** respectively, between the positive power source Vdd and each of the emitters of the PNP bipolar transistor Q**2** and Q**3**.

In the following explanation of an operation of the band gap circuit shown in **1** and nI**1** represent currents of the current sources I**1** and nI**1**, C**3** and C**4** represent capacitances of the capacitors C**3** and C**4**, and Vo represents an output reference potential of the operational amplifier circuit OP**2**. Nodes between an internal circuit and each of the noninverting input (+), the emitter of the PNP bipolar transistor Q**3**, and the inverting input (−) are nodes N**3**, N**4**, and N**5** respectively. A node between the capacitor C**4** and both of the switches S**3** and S**4** is a node N**6**. Sizes of the PNP bipolar transistors Q**2** and Q**3** are equal to each other.

As shown in **6** is closed on a side of the PNP bipolar transistor Q**2**, and the switch S**7** is closed on a side of the PNP bipolar transistor Q**3**. The switches S**3** and S**5** are closed, and the switch S**4** is open. The current I**1** flows through the PNP bipolar transistor Q**2**. A base-to-emitter voltage of the PNP bipolar transistor Q**2** is Vbe**1**. The current nI**1** flows through the PNP bipolar transistor Q**3**. A base-to-emitter voltage of the PNP bipolar transistor Q**3** is Vbe**2**.

Since the switch S**3** is closed, a potential at the node N**6** is Vbe, which is equal to a potential of the node N**3**. Moreover, since the switch S**5** is close, a potential of the node N**5** is approximately Vbe**1**, which is substantially equal to the potential of the node N**3**. It is assumed that an ideal condition in which an offset voltage becomes zero in the operational amplifier circuit OP**2** is obtained. Because a potential of the node N**4** is Vbe**2**, an electrical charge to be accumulated in the capacitor C**3** is −(Vbe**2**−Vbe**1**)C**3**. In addition, since the potentials of the nodes N**5** and N**6** are equal to each other, an electrical charge to be accumulated in the capacitor C**4** becomes zero. Therefore, an electrical charge to be accumulated in the node N**5** is −(Vbe**2**−Vbe**1**)C**3**.

When the switch S**5** is switched to be open in this condition, the electrical charge accumulated in the node N**5** is conserved. Then, the switch S**3** is switched to be open, the switch S**6** is switched to be closed on a side of the PNP bipolar transistor Q**3**, and the switch S**7** is switched to be closed on a side of the PNP bipolar transistor Q**2**. Furthermore, the switch S**4** is switched to be closed. Thus, the current nI**1** flows through the PNP bipolar transistor Q**2**. Therefore, the base-to-emitter voltage of the PNP bipolar transistor Q**2** becomes Vbe**2**. On the other hand, the current I**1** flows through the PNP bipolar transistor Q**3**. Therefore, the base-to-emitter voltage of the PNP bipolar transistor Q**3** becomes Vbe**1**.

Since the potential of the node N**3** becomes Vbe**2**, if a voltage gain of the operational amplifier circuit OP**2** is enough large, the potential of the node N**5** also becomes Vbe**2**. An output potential of the operational amplifier circuit OP**2** is determined to conserve the electrical charge of the node N**5**. The electrical charge qN**5** of the node N**5** is expressed as

*qN*5*=C*3(*Vbe*2*−Vbe*1)−(*Vo−Vbe*2)*C*4 (12)

where Vo is output potential.

As described above, the electrical charge of the node N**5** before each of the switches is switched is −(Vbe**2**−Vbe**1**)C**3**. Based on this, the following Equation 13 is obtained.

−(*Vbe*2*−Vbe*1)*C*3*=C*3(*Vbe*2*−Vbe*1)−(*Vo−Vbe*2)*C*4 (13)

When Equation 13 is solved for Vo where Vbe**2**−Vbe**1**=ΔVbe, the following Equation 14 is obtained.

*Vo=Vbe*2*+ΔVbe×*2*C*3/*C*4 (14)

In the circuit designed such that ΔVbe is generated depending on a predetermined current ratio, ΔVbe has dependency that is proportional to the absolute temperature T. Therefore, with the circuit shown in

Various other switched-capacitor band gap circuits are know in the art. A circuit disclosed in, for example, Japanese Patent Application Laid-Open No. H5-181556 is configured as follows. The circuit includes a first current source and a first diode element, a second current source and a second diode, a first switch, a second switch, a first capacitor, a second capacitor, a third switch, an amplifier, a fourth switch, and a third capacitor. The first current source and the first diode element are joined at a first node and connected in series between a first and a second voltage terminals. The second current source and the second diode element are joined at a second node and connected in series between the first and the second voltage terminals. The first and the second current sources have different currents. The first switch includes a first terminal selectively connectable to a second and a third terminals thereof. The second switch is selectably connected to a first, a second, and a third terminals. The second and third terminals are connected respectively to the second node and the second voltage terminal. The first capacitor includes a first terminal that is connected to the first terminal of the first switch. The second capacitor includes a first terminal that is connected to the first terminal of the second switch. Second terminals of the first and the second capacitors are connected in common to a third node. The third switch includes a first and a second terminals. The first terminal of the third switch is connected to the third node. The amplifier includes an input and an output, and the input is connected to the second terminal of the third switch. The fourth switch includes a first and a second terminals connected between the input and the output of the amplifier. The third capacitor includes a first terminal connected to the input of the amplifier and a second terminal connected to the output of the amplifier.

A circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 2001-154749 is configured as follows. The circuit includes a band gap circuit, a switched capacitor circuit, and a filter. The band gap circuit outputs a bandgap output voltage from a first output terminal. The switched capacitor circuit operates in response to a control clock. The filter receives the bandgap output voltage, and outputs received bandgap output voltage to a second output terminal. The bandgap output voltage is controlled based on a frequency of the control clock.

A circuit for generating a reference voltage independent of temperature disclosed in, for example, Japanese Patent Application Laid-Open No. S58-500045 is configured as follows. The circuit includes a first and a second bipolar transistors, a clock, a first and a second switched capacitors, and an amplifier. The first and the second bipolar transistors have a predetermined base voltage. The first and the second bipolar transistors are biased to different current density, and generate a first emitter voltage and a second emitter voltage at each emitter. The clock generates a first and a second clock signals that do not overlap with each other. The first switched capacitor is coupled to the base voltage in response to the first clock signal, is coupled to the first emitter voltage in response to the second clock signal, and generates a first electrical charge relating to Vbe of the first bipolar transistor. The second switched capacitor is couple to the second emitter voltage in response to the first clock signal, is couple to the first emitter voltage in response to the second clock signal, and generates a second electrical charge relating to a difference between Vbe of the first bipolar transistor and Vbe of the second bipolar transistor. The amplifier is connected to the first and the second switched capacitors, and generates a reference voltage that is proportional to a sum of the first electrical charge and the second electrical charge. Such conventional circuit is also disclosed in, for example, *IEEE JOURNAL OF SOLID-STATE CIRCUITS, *Vol. 33, No. 7, 1998, pp. 1117-1122 titled “A Switched-Current, Switched-Capacitor Temperature Sensor in 0.6− μm CMOS” by Mike Tuthill.

As described above, in the conventional switched-capacitor band gap circuit, in multiplying the thermal voltage k·T/q by a predetermined coefficient, a capacitance ratio of a switched capacitor, for example, C**1**/C**2** in Equation 11 and C**3**/C**4** in Equation 14, is used as the coefficient. Generally, to obtain the capacitance ratio with high accuracy and high reproducibility in an IC, plural units of capacitors each of which has a predetermined unit capacitance are prepared. A desirable capacitance ratio is obtained by adjusting a ratio in the number of such capacitors. Therefore, the capacitance ratio, which is the coefficient, is an integer ratio. To approximate the integer ratio to a desirable coefficient, it is preferable that the integer ratio can be set more precisely. To set the integer ratio in detail, however, it is necessary to increase the number of such capacitors. The capacitors disadvantageously occupy silicon area.

It is an object of the present invention to at least solve the above problems in the conventional technology.

A band gap circuit according to one aspect of the present invention generates a reference voltage, and includes a voltage generating circuit configured to generate a voltage having negative temperature dependency; a first switched-capacitor circuit including a first operational amplifier circuit having an input terminal and an output terminal; a first input capacitor that is connected to the input terminal of the first operational amplifier circuit; and a first feedback capacitor that is connected to the input terminal and the output terminal of the first operational amplifier circuit; a second switched-capacitor circuit including a second operational amplifier circuit having an input terminal and an output terminal; a second input capacitor that is connected to the input terminal of the second operational amplifier circuit; and a second feedback capacitor that is connected to the input terminal and the output terminal of the second operational amplifier circuit; and a first coupling capacitor that capacitively couples the output terminal of the second operational amplifier circuit with the input terminal of the first operational amplifier circuit. A thermal voltage, which is a voltage proportional to absolute temperature, is multiplied by a coefficient, and multiplied thermal voltage is added to the voltage generated by the voltage generating circuit, the coefficient being determined based on capacitances of the first input capacitor, the first feedback capacitor, the first coupling capacitor, the second input capacitor, and the second feedback capacitor.

The other objects, features, and advantages of the present invention are specifically set forth in or will become apparent from the following detailed description of the invention when read in conjunction with the accompanying drawings.

Exemplary embodiments of the present invention will be explained in detail below with reference to the accompanying drawings.

**1**, a first switched capacitor **2** and a second switched capacitor **3**, and a coupling capacitor C**7**. The voltage generating circuit **1** generates a voltage so that a p-n junction is forward biased. The coupling capacitor C**7** capacitively couples the first switched capacitor **2** and the second switched capacitor **3**.

The voltage generating circuit **1** includes, for example, three current sources I**1**, I**2**, and I**3**, and two PNP bipolar transistors Q**4** and Q**5**. A base and a collector of the PNP bipolar transistor Q**4** are connected to the ground GND. An emitter of the PNP bipolar transistor Q**4** is connected to the current source I**1** through a switch S**16**, and to the current source I**2** through a switch S**17**.

A base and a collector of the PNP bipolar transistor Q**5** are connected to the ground GND. An emitter of the PNP bipolar transistor Q**5** is connected to the current source I**3**. To the current sources I**1**, I**2**, and I**3**, a positive power is supplied from the positive power source Vdd.

The first switched capacitor circuit **2** includes an operational amplifier circuit OP**3**, two units of capacitors C**5** and C**6**, and three switches S**8**, S**9**, and S**10**. A noninverting input (+) of the operational amplifier circuit OP**3** is connected to the emitter of the PNP bipolar transistor Q**5**. A node between the noninverting input (+) and the emitter of the PNP bipolar transistor Q**5** is a node N**7**. An inverting input (−) of the operational amplifier circuit OP**3** is connected to the emitter of the PNP bipolar transistor Q**4** through the input capacitor C**5**. A node between the emitter of the PNP bipolar transistor Q**4** and an internal circuit is a node N**8**.

An output of the operational amplifier circuit OP**3** is connected to the switch S**10**. The feedback capacitor C**6** is connected between the switch S**10** and the inverting input (−) of the operational amplifier circuit OP**3**. The switch S**9** is connected between the noninverting input (+) of the operational amplifier circuit OP**3** and the feedback capacitor C**6**. A node between the switches S**9**, and S**10**, and the feedback capacitor C**6** is node N**10**. The switch S**8** is connected between the output and the inverting input (−) of the operational amplifier circuit OP**3**. A node between the switch S**8** and the inverting input (−) of the operational amplifier OP**3** is a node N**9**.

The second switched capacitor circuit **3** includes an operational amplifier circuit OP**4**, two units of capacitors C**8** and C**9**, and three switches S**13**, S**14**, and S**15**. A structure of the second switched capacitor circuit **3** is same as that of the first switched capacitor circuit **2**, and the operational amplifier circuit OP**4**, the capacitors C**8** and C**9**, and the switches S**13**, S**14**, and S**15** correspond to the operational amplifier circuit OP**3**, the capacitors C**5** and C**6**, and three switches S**8**, S**9**, and S**10** in the first switched capacitor circuit **2**. Moreover, nodes N**12** and N**13** correspond to the nodes N**9** and N**10**.

An output of the operational amplifier circuit OP**4** is connected to the switch S**12**. The coupling capacitor C**7** is connected between the switch S**12** and the inverting input (−) of the operational amplifier circuit OP**3**. A capacitance of the coupling capacitor C**7** is smaller than a capacitance of the feedback capacitor C**6**. A node between the switch S**12** and the coupling capacitor C**7** is a node N**11**. Between the node N**11** and the node N**7**, which is between the noninverting input (+) of the operational amplifier circuits OP**3** and OP**4**, the switch S**11** is connected. The switches S**8** to S**17** are formed with, for example, MOS transistors.

In the following explanation of the band gap circuit shown in **1**, I**2**, and I**3** represent currents of the current sources I**1**, I**2**, and I**3** respectively. C**5**, C**6**, C**7**, C**8**, and C**9** represent capacitances of the input capacitor C**5**, the feedback capacitor C**6**, the coupling capacitor C**7**, the input capacitor C**8**, and the feedback capacitor C**9** respectively. Moreover, Vo represents an output reference potential of the operational amplifier circuit OP**3**, and Vo**2** represents an output potential of the operational amplifier circuit OP**4**. Vo is a potential of the internal circuit required for generating Vo. It is assumed that an offset voltage is zero in the operational amplifier circuits OP**3** and OP**4**, and the sizes of the PNP bipolar transistors Q**4** and Q**5** are equal to each other.

As shown in **8**, S**9**, S**11**, S**13**, S**14**, and S**17** are closed, and the switches S**10**, S**12**, S**15**, and S**16** are open. Since the switch S**17** is closed and the switch S**16** is open, the current I**2** flows through the PNP bipolar transistor Q**4**.

When a base-to-emitter voltage of the PNP bipolar transistor Q**4** is Vbe**2**, a potential of the node N**8** is Vbe**2**. The current I**3** flows through the PNP bipolar transistor Q**5**. When a base-to-emitter voltage of the PNP bipolar transistor Q**5** is Vbe**3**, a potential of the node N**7** is Vbe**3**. Since the switch S**8** is closed, a potential of the node N**9** is equal to an output potential of the operational amplifier circuit OP**3**. Because the potential of the node N**7** and a potential of the node N**9** are substantially equal to each other, the potential of the node N**9** is substantially Vbe**3**. Since the switch S**9** is closed, a potential of the node N**10** becomes equal to that of the node N**7**, which is Vbe**3**.

Since the switch S**13** is closed, a potential of the node N**12** is equal to an output potential of the operational amplifier circuit OP**4**. Moreover, because the potentials of the nodes N**7** and N**12** are substantially equal to each other, the potential of the node N**12** is substantially Vbe**3**. Since the switch S**14** is closed, a potential of the node N**13** becomes equal to that of the node N**7**, which is Vbe**3**.

Because the potentials of the nodes N**9** and N**10** are equal, an electrical charge to be accumulated in the feedback capacitor C**6** is zero. In addition, because the potential of the node N**8** is Vbe**2** and the potential of the node N**9** is Vbe**3**, an electrical charge to be accumulated in the input capacitor C**5** is (Vbe**3**−Vbe**2**)C**5**. Therefore, an electrical charge qN**9** to be accumulated at the node N**9** is expressed as

*qN*9=(*Vbe*3*−Vbe*2)*C*5 (15)

Since both of potentials at both ends of the coupling capacitor C**7** are Vbe**3**, an electrical charge to be accumulated in the coupling capacitor C**7** is zero. Since the potentials of the nodes N**12** and N**13** are equal to each other, an electrical charge to be accumulated in the feedback capacitor C**9** is zero. Moreover, since the potential of the node N**8** is Vbe**2** and the potential of the node N**12** is Vbe**3**, an electrical charge to be accumulated in the input capacitor C**8** is (Vbe**3**−Vbe**2**)C**8**. Therefore, an electrical charge qN**12** to be accumulated in the input capacitor C**8** is expressed as

*qN*12=(*Vbe*3*−Vbe*2)*C*8 (16)

The switches S**8**, S**9**, S**11**, S**13**, S**14**, and S**17** are switched off to be open. Then, the switches S**10**, S**12**, S**15**, and S**16** are switched on to be closed. Since the switches S**8** and S**13** are open, the electrical charges at the nodes N**9** and N**12** are conserved. In addition, the current I**1** flows through the PNP bipolar transistor Q**4**. The base-to-emitter voltage of the PNP bipolar transistor Q**4** is Vbe**1**.

When I**2**=j·I**1** (where j is a coefficient) is satisfied, the base-to-emitter voltage of the PNP bipolar transistor Q**4** while a current j·I**1** is flowing therethrough is Vbe**2**. Therefore, by setting the current sources I**1** and I**2** to be I**1**<I**2**, the electric potential at the node N**8** becomes Vbe**1** from Vbe**2**. When ΔVbe=Vbe**2**−Vbe**1** is satisfied, The following Equation 17 is obtained from Equation 16.

Δ*Vbe*=(*k·T/q*)ln(*j*) (17)

On the other hand, since the electric potential at the node N**7** does not change, if a gain of the operational amplifier circuit OP**3** is sufficiently large, the electrical charge at the node N**9** also remains to be Vbe**3**. Thus, the output potential of the operational amplifier circuit OP**3** is determined so that the electrical charge of the node N**9** is conserved. In a similar manner, if a gain of the operational amplifier circuit OP**4** is sufficiently large, the electrical charge at the node N**12** remains to be Vbe**3**, the output potential of the operational amplifier circuit OP**4** is determined so that the electrical potential of the node N**12** is conserved.

Suppose that the electrical charge of the node N**8** decreases by ΔVbe, and the output potential of the operational amplifier OP**4** increases from Vbe**3** to Vo**2**. If the electrical charge at the node N**12** is acquired in this condition, supposing that the electrical charge qN**12** of the node N**12** in Equation 16 is conserved, the following Equation 18 is obtained.

(*Vbe*3*−Vbe*1)*C*8−(*Vo*2*−Vbe*3)*C*9=(*Vbe*3*−Vbe*2)*C*8 (18)

When Equation 18 is solved for Vo**2** where Vbe**2**−Vbe**1**=ΔVbe, the following Equation 19 is obtained.

*Vo*2*=Vbe*3*+ΔVbe×C*8/*C*9 (19)

Based on Equation 19, Vo**2** can be determined. The electrical charge of the node N**18** decreases by ΔVbe, and the output potential of the operational amplifier circuit OP**4** increases from Vbe**3** to Vo**2** shown in Equation 19. Moreover, suppose that the output potential of the operational amplifier circuit OP**3** increases from Vbe**3** to Vo. If the electrical charge of the node N**9** is acquired in this condition, supposing that the electrical charge qN**9** of the node N**9** in Equation 15 is conserved, the following Equation 20 is obtained.

(*Vbe*3*−Vbe*1)*C*5−(*Vo−Vbe*3)*C*6−(*Vo*2*−Vbe*3)*C*7=(*Vbe*3*−Vbe*2)*C*5 (20)

When Equation 20 is solved for Vo where Vo**2**−Vbe**3**=ΔVbe×C**8**/C**9**, the following Equation 21 is obtained.

*Vo=Vbe*3*+ΔVbe×C*5/*C*6*−ΔVbe*×(*C*7*C*8)/(*C*6*C*9) (21)

Based on Equation 21, Vo can be determined. Vbe**3** of the forward bias voltage at the p-n junction has the negative temperature-dependency in which the voltage decreases as temperature increases. On the other hand, ΔVbe increases in proportion to temperature as shown in Equation 17. Therefore, by appropriately setting values of C**5**/C**6** and (C**7**C**8**)/(C**6**C**9**), it is possible to design the circuit such that the output reference potential Vo of the operational amplifier circuit OP**3** is independent of temperature. In this case, Vo corresponds to a bandgap voltage of silicon, which is approximately 1.2 V.

Thus, according to the band gap circuit shown in

The band gap circuit according to the first embodiment shown in

For example, when capacitances of the capacitors C**3** and C**4** shown in **3**/C**4**=140/20=7. If the capacitance ratio should be modified as a result of measurement, the capacitance ratio can be modified by changing, for example, the capacitance of the capacitor C**3** to 139. Thus, the capacitance ratio can be changed to C**3**/C**4**=139/20. Difference between the capacitance ratios when the capacitance of the capacitor C**3** is 140 and 139 is 140/20−139/20=0.05.

When capacitances of the input capacitor C**5**, the feedback capacitor C**6**, the coupling capacitor C**7**, the input capacitor C**8**, and the feedback capacitor C**9** are 70, 9, 1, 70, and 10 respectively, the total capacitance is 160. The capacitance ratio by which ΔVbe is multiplied is C**5**/C**6**−(C**7**C**8**)/(C**6**C**9**) as indicated in Equation 21. Therefore, the capacitance ratio is 70/9−(1×70)/(9×10)=7.7778−0.7778=7.

If this capacitance ratio should be modified as a result of measurement, the capacitance ratio can be modified by changing, for example, the capacitance of the input capacitor C**8** to 69. Thus, the capacitance ratio can be changed to 70/9−(1×69)(9×10O)=7.7778−0.7667=7.011. Therefore, a difference between the capacitance ratios is |7−7.011|=0.01. This is ⅕ of the difference between the capacitance ratios in the conventional band gap circuit shown in

**3** and the operational amplifier circuit OP**4**. As shown in **3** and the operational amplifier circuit OP**4** are, for example, of a folded cascode type, although not particularly limited. This type of operational amplifier circuit includes a constant current source, a folded cascode circuit, and a current mirror circuit. The constant current source is formed with positive-channel metal-oxide semiconductor (PMOS) transistors PM**1** and PM**2**, and negative-channel metal-oxide semiconductor (NMOS) transistors NM**1** and NM**2**. The folded cascode circuit is formed with PMOS transistors PM**3** and PM**4**, and NMOS transistors NM**3** and NM**4**. The current mirror circuit is formed with PMOS transistors PM**5**, PM**6**, PM**7**, and PM**8**.

Vdd, GND, and OUT shown in

Since a structure of a folded-cascode-type operational amplifier circuit is a public knowledge, explanation is omitted. The operational amplifier circuits OP**3** and OP**4** are not limited to that of the folded cascode type, and may be of other types having different structures as long as the voltage amplification rate is sufficiently large.

According to the first embodiment, the coefficient can be set in more detail than the conventional technology without increasing the total number in unit capacitance. Therefore, it is possible to set the coefficient more precisely without increasing a silicon area to be occupied by the capacitors in the band gap circuit. Thus, the PTAT voltage can be generated with high accuracy, thereby increasing the accuracy of the reference voltage based on the PTAT voltage.

**4** and a coupling capacitor C**10** that couples the switched capacitor circuit C**4** to the second switched capacitor circuit **3**, in addition to other elements in the band gap circuit according to the first embodiment.

The third switched capacitor circuit **4** has the same structure as that of the first switched capacitor circuit **2**. An operational amplifier circuit OP**5**, an input capacitor C**11**, a feedback capacitor C**12**, switches S**20**, S**21**, and S**22** correspond to the operational amplifier circuit OP**3**, the input capacitor C**5**, the feedback capacitor C**6**, the switches S**8**, S**9**, and S**10** in the bandbap circuit according to the first embodiment respectively. Nodes N**15** and N**16** correspond to the nodes N**9** and N**10**.

An output of the operational amplifier circuit OPS is connected to the switch S**19**. The coupling capacitor C**10** is connected between the switch S**19** and an inverting input (−) of the operational amplifier circuit OP**5**. A capacitance of the coupling capacitor C**10** is smaller than that of the feedback capacitor C**9** in the second switched capacitor circuit **3**. A node between the switch S**19** and the coupling capacitor C**10** is a node N**14**. A switch S**18** is connected between the nodes N**14** and N**7**, in other words, between each noninverting input (+) of the operational amplifier circuits OP**3**, OP**4**, and OP**5**.

Other structures are identical to that of the band gap circuit according to the first embodiment, therefore, like reference characters refer to like elements, and explanation is omitted. The operational amplifier circuit OP**5** is, for example, of the folded cascode type shown in **18** to S**22** are formed with, for example, MOS transistors.

In the following explanation of the band gap circuit shown in **10**, C**11**, and C**12** represent capacitances of the coupling capacitor C**10**, the input capacitor C**11**, and the feedback capacitor C**12**. Moreover, Vo**3** represents an output potential of the operational amplifier circuit OP**5**. Vo**3** is a potential of the internal circuit required for generating Vo, together with Vo**2**. It is assumed that an offset voltage is zero in the operational amplifier circuits OP**5**.

As shown in **8**, S**9**, S**11**, S**13**, S**14** S**17**, S**18**, S**20**, and S**21** are closed, and the switches S**10**, S**12**, S**15**, S**16**, S**19**, and S**22** are open. In this condition, the potentials at the nodes N**7**, N**10**, N**11**, and N**13** are Vbe**3** as explained in the first embodiment. The potential of the node N**8** is Vbe**2**. The potential of the node N**9** is substantially Vbe**3**. The potential of the node N**12** is substantially equal to the output voltage of the operational amplifier circuit OP**4** to be approximately Vbe**3**.

Since the switch S**20** is closed, the potential of the node N**15** is equal to the output potential of the operational amplifier circuit OP**5**. Moreover, since the potentials of the nodes N**7** and N**15** are substantially equal, the potential of the node N**15** is also approximately Vbe**3**.

In this state, the electrical charge qN**9** to be accumulated at the node N**9** is expressed as in Equation 15. The electrical charge qN**12** to be accumulated at the node N**12** is expressed as in Equation 16.

Since both of potentials at both ends of the coupling capacitor C**10** are Vbe**3**, an electrical charge to be accumulated in the coupling capacitor C**10** is zero. Since the potentials of the nodes N**15** and N**16** are equal to each other, an electrical charge to be accumulated in the feedback capacitor C**12** is zero. Moreover, since the potential of the node N**8** is Vbe**2** and the potential of the node N**15** is Vbe**3**, an electrical charge to be accumulated in the input capacitor C**11** is (Vbe**3**−Vbe**2**)C**8**. Therefore, an electrical charge qN**15** to be accumulated in the input capacitor C**11** is expressed as

*qN*15=(*Vbe*3*−Vbe*2)*C*11 (22)

The switches S**8**, S**9**, S**11**, S**13**, S**14**, S**17**, S**18**, S**20**, and S**21** are switched off to be open. Then, the switches S**10**, S**12**, S**15**, S**16**, S**19**, and S**22** are switched on to be closed. Since the switches S**8**, S**13**, and S**20** are switched to be open, the electrical charges at the nodes N**9**, N**12**, and N**15** are conserved. In addition, the current I**1** flows through the PNP bipolar transistor Q**4**. The base-to-emitter voltage of the PNP bipolar transistor Q**4** is Vbe**1**.

When I**2**=j·I**1** (where j is a coefficient, and I**1**<I**2**) and ΔVbe=Vbe**2**−Vbe**1** are satisfied as in the first embodiment, Equation 17 is obtained as described in the first embodiment. If a gain of the operational amplifier circuit OP**3** is sufficiently large, the output potential of the operational amplifier circuit OP**3** is determined so that the electrical charge of the node N**9** is conserved. Moreover, if a gain of the operational amplifier circuit OP**4** is sufficiently large, the output potential of the operational amplifier circuit OP**3** is determined so that the electrical charge of the node N**12** is conserved. Since the electric potential at the node N**7** remains to be Vbe**3**, if a gain of the operational amplifier circuit OP**5** is sufficiently large, the electrical charge at the node N**15** also remains to be Vbe**3**. The output potential of the operational amplifier circuit OP**5** is determined so that the electrical charge of the node N**15** is conserved.

Suppose that the electrical charge of the node N**8** decreases by ΔVbe, and the output potential of the operational amplifier OP**5** increases from Vbe**3** to Vo**3**. If the electrical charge at the node N**15** is acquired in this condition, supposing that the electrical charge qN**15** of the node N**15** in Equation 16 is conserved, the following Equation 23 is obtained.

(*Vbe*3*−Vbe*1)*C*11−(*Vo*3*−Vbe*3)*C*12=(*Vbe*3*−Vbe*2)*C*11 (23)

When Equation 23 is solved for Vo**3** where Vbe**2**−Vbe**1**=ΔVbe, the following Equation 24 is obtained.

*Vo*3*=Vbe*3*+ΔVbe×C*11/*C*12 (24)

Based on Equation 24, Vo**3** can be determined. The electrical charge of the node N**8** decreases by ΔVbe, and the output potential of the operational amplifier circuit OP**5** increases from Vbe**3** to Vo**3** shown in Equation 24. Moreover, suppose that the output potential of the operational amplifier circuit OP**4** increases from Vbe**3** to Vo**2**. If the electrical charge of the node N**12** is acquired in this condition, supposing that the electrical charge qN**12** of the node N**12** in Equation 16 is conserved, the following Equation 25 is obtained.

(*Vbe*3*−Vbe*1)*C*8−(*Vo*2*−Vbe*3)*C*9−(*Vo*3*−Vbe*3)*C*10=(*Vbe*3*−Vbe*2)*C*8 (25)

When Equation 25 is solved for Vo**2** where Vo**3**−Vbe**3**=ΔVbe×C**11**/C**12**, the following Equation 26 is obtained.

*Vo*2*=Vbe*3*+ΔVbe×C*8/*C*9*−ΔVbe*×(*C*10*C*11)/(*C*9*C*12) (26)

Based on Equation 26, Vo**2** can be determined. The electrical charge of the node N**8** decreases by ΔVbe, and the output potential of the operational amplifier circuit OP**4** increases from Vbe**3** to Vo**2** shown in Equation 26. Moreover, suppose that the output potential of the operational amplifier circuit OP**3** increases from Vbe**3** to Vo. If the electrical charge of the node N**9** is acquired in this condition, supposing that the electrical charge qN**9** of the node N**9** in Equation 15 is conserved, Equation 20 described previously is obtained.

Since Vo**2**−Vbe**3**=ΔVbe×C**8**/C**9**−ΔVbe×(C**10**C**11**)/(C**9**C**12**) is obtained from Equation 26, when Equation 20 is solved for Vo, the following Equation 27 is obtained.

*Vo=Vbe*3*+ΔVbe×C*5/*C*6*−ΔVbe*×(*C*7*C*8)/(*C*6*C*9)+Δ*Vbe*×(*C*7*C*10*C*11)/(*C*6*C*9*C*12) (27)

Based on Equation 27, Vo can be determined. By setting C**5**/C**6**, (C**7**C**8**)/(C**6**C**9**), and (C**7**C**10**C**11**)/(C**6**C**9**C**12**) appropriately, the circuit can be designed so as to obtain the output reference potential Vo of the operational amplifier circuit OP**3** independent of temperature. In such a condition, Vo corresponds to a bandgap voltage of silicon, and is 1.2 V. Thus, according to the band gap circuit shown in

In the following explanation of an example of setting the coefficient more precisely, it is assumed that the capacitance ratio required is 7:1 for the conveniences' sake, although the capacitance ratio to be required in an actual use varies depending on conditions. The capacitance of each capacitor is indicated in the brackets shown near each capacitor in

When capacitances of the input capacitor C**5**, the feedback capacitors C**6**, the coupling capacitor C**7**, the input capacitor C**8**, the feedback capacitor C**9**, the coupling capacitor C**10**, the input capacitor C**11**, and the feedback capacitor C**12** are 42, 5, 1, 42, 5, 1, 42, and 6 respectively, the total capacitance is 144. From Equation 27, the capacitance ratio by which ΔVbe is multiplied is C**5**/C**6**−(C**7**C**8**)/(C**6**C**9**)+(C**7**C**10**C**11**)/(C**6**C**9**C**12**). Therefore, the capacitance ratio is 42/5−(1×42)/(5×5)+(1×1×42)/(5×5×6)=8.4−4.68+0.28=7.

If the capacitance ratio should be modified as a result of measurement, the capacitance ratio can be modified by changing, for example, the capacitance of the capacitor C**11** to 41. Thus, the capacitance ratio can be changed to 42/5−(1×42)/(5×5)+(1×1×41)/(5×5×6)=8.4−4.68+0.2733=6.9933. A difference between the capacitance ratios is |7−6.9933|=0.0067. Since the difference achieved in the conventional band gap circuit is 0.05 as explained in the first embodiment, this is approximately 1/7 of the difference in the case of the conventional band gap circuit shown in

According to the second embodiment, the coefficient can be set in more precise than the conventional technology without increasing the total number of unit capacitances forming each of the capacitors C**5**, C**6**, C**7**, C**8**, C**9**, C**10**, C**11**, and C**12**. Therefore, it is possible to set the coefficient more precisely without increasing silicon area to be occupied by the capacitors in the band gap circuit. Moreover, the coefficient can be set in more precise than a case in the first embodiment. Thus, the PTAT voltage can be generated with high accuracy, thereby increasing the accuracy of the reference voltage based on the PTAT voltage.

The various other embodiments are possible. For example, the voltage generating circuit **1**, the first switched capacitor circuit **2**, the second switched capacitor circuit **3**, and the third switched capacitor circuit **4** can have configurations other than those explained above. Moreover, in a similar arrangement in which the third switched capacitor circuit **4** is connected to the second switched capacitor circuit **3**, four or more switched capacitor circuits may be provided. The more the switched capacitor circuits are provided, in the more precise value the coefficient can be obtained, thereby increasing the accuracy of the reference voltage.

According to the embodiments described above, it is possible to set a coefficient, by which a thermal voltage k·T/q is multiplied, precisely without increasing silicon area to be occupied by capacitors in a circuit.

Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Patent Citations

Cited Patent | Filing date | Publication date | Applicant | Title |
---|---|---|---|---|

US5352972 * | Mar 31, 1992 | Oct 4, 1994 | Sgs-Thomson Microelectronics, S.R.L. | Sampled band-gap voltage reference circuit |

US5563504 | May 9, 1994 | Oct 8, 1996 | Analog Devices, Inc. | Switching bandgap voltage reference |

US5867012 * | Aug 14, 1997 | Feb 2, 1999 | Analog Devices, Inc. | Switching bandgap reference circuit with compounded ΔV.sub.βΕ |

US6215353 * | May 24, 1999 | Apr 10, 2001 | Pairgain Technologies, Inc. | Stable voltage reference circuit |

US6819163 * | Mar 27, 2003 | Nov 16, 2004 | Ami Semiconductor, Inc. | Switched capacitor voltage reference circuits using transconductance circuit to generate reference voltage |

JP2001154749A | Title not available | |||

JPH05181556A | Title not available | |||

JPS58500045A | Title not available | |||

WO1982002806A1 | Jan 25, 1982 | Aug 19, 1982 | Inc Motorola | Switched capacitor bandgap reference |

Non-Patent Citations

Reference | ||
---|---|---|

1 | Mike Tuthill; "A Switched-Current, Switched-Capacitor Temperature Sensor in 0.6-mum CMOS"; IEEE Journal of Solid-State Circuits; vol. 33, No. 7, Jul. 1998. |

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Classifications

U.S. Classification | 327/539 |

International Classification | G05F1/10 |

Cooperative Classification | G05F3/30 |

European Classification | G05F3/30 |

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